1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cortex_a57.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/console.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <drivers/arm/gic_common.h> 16 #include <drivers/arm/gicv2.h> 17 #include <bl31/interrupt_mgmt.h> 18 19 #include <bpmp.h> 20 #include <flowctrl.h> 21 #include <memctrl.h> 22 #include <plat/common/platform.h> 23 #include <security_engine.h> 24 #include <tegra_def.h> 25 #include <tegra_platform.h> 26 #include <tegra_private.h> 27 28 /* sets of MMIO ranges setup */ 29 #define MMIO_RANGE_0_ADDR 0x50000000 30 #define MMIO_RANGE_1_ADDR 0x60000000 31 #define MMIO_RANGE_2_ADDR 0x70000000 32 #define MMIO_RANGE_SIZE 0x200000 33 34 /* 35 * Table of regions to map using the MMU. 36 */ 37 static const mmap_region_t tegra_mmap[] = { 38 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 39 MT_DEVICE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 41 MT_DEVICE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 {0} 47 }; 48 49 /******************************************************************************* 50 * Set up the pagetables as per the platform memory map & initialize the MMU 51 ******************************************************************************/ 52 const mmap_region_t *plat_get_mmio_map(void) 53 { 54 /* Add the map region for security engine SE2 */ 55 if (tegra_chipid_is_t210_b01()) { 56 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 57 (uint64_t)TEGRA_SE2_BASE, 58 (uint64_t)TEGRA_SE2_RANGE_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE); 60 } 61 62 /* MMIO space */ 63 return tegra_mmap; 64 } 65 66 /******************************************************************************* 67 * The Tegra power domain tree has a single system level power domain i.e. a 68 * single root node. The first entry in the power domain descriptor specifies 69 * the number of power domains at the highest power level. 70 ******************************************************************************* 71 */ 72 const unsigned char tegra_power_domain_tree_desc[] = { 73 /* No of root nodes */ 74 1, 75 /* No of clusters */ 76 PLATFORM_CLUSTER_COUNT, 77 /* No of CPU cores - cluster0 */ 78 PLATFORM_MAX_CPUS_PER_CLUSTER, 79 /* No of CPU cores - cluster1 */ 80 PLATFORM_MAX_CPUS_PER_CLUSTER 81 }; 82 83 /******************************************************************************* 84 * This function returns the Tegra default topology tree information. 85 ******************************************************************************/ 86 const unsigned char *plat_get_power_domain_tree_desc(void) 87 { 88 return tegra_power_domain_tree_desc; 89 } 90 91 /******************************************************************************* 92 * Handler to get the System Counter Frequency 93 ******************************************************************************/ 94 unsigned int plat_get_syscnt_freq2(void) 95 { 96 return 19200000; 97 } 98 99 /******************************************************************************* 100 * Maximum supported UART controllers 101 ******************************************************************************/ 102 #define TEGRA210_MAX_UART_PORTS 5 103 104 /******************************************************************************* 105 * This variable holds the UART port base addresses 106 ******************************************************************************/ 107 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 108 0, /* undefined - treated as an error case */ 109 TEGRA_UARTA_BASE, 110 TEGRA_UARTB_BASE, 111 TEGRA_UARTC_BASE, 112 TEGRA_UARTD_BASE, 113 TEGRA_UARTE_BASE, 114 }; 115 116 /******************************************************************************* 117 * Enable console corresponding to the console ID 118 ******************************************************************************/ 119 void plat_enable_console(int32_t id) 120 { 121 static console_16550_t uart_console; 122 uint32_t console_clock; 123 124 if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) { 125 /* 126 * Reference clock used by the FPGAs is a lot slower. 127 */ 128 if (tegra_platform_is_fpga()) { 129 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 130 } else { 131 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 132 } 133 134 (void)console_16550_register(tegra210_uart_addresses[id], 135 console_clock, 136 TEGRA_CONSOLE_BAUDRATE, 137 &uart_console); 138 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT | 139 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 140 } 141 } 142 143 /******************************************************************************* 144 * Handler for early platform setup 145 ******************************************************************************/ 146 void plat_early_platform_setup(void) 147 { 148 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 149 uint64_t val; 150 151 /* platform parameter passed by the previous bootloader */ 152 if (plat_params->l2_ecc_parity_prot_dis != 1) { 153 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 154 val = read_l2ctlr_el1(); 155 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 156 write_l2ctlr_el1(val); 157 } 158 159 /* Initialize security engine driver */ 160 if (tegra_chipid_is_t210_b01()) { 161 tegra_se_init(); 162 } 163 } 164 165 /* Secure IRQs for Tegra186 */ 166 static const interrupt_prop_t tegra210_interrupt_props[] = { 167 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY, 168 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 169 }; 170 171 void plat_late_platform_setup(void) 172 { 173 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 174 uint64_t sc7entry_end, offset; 175 int ret; 176 uint32_t val; 177 178 /* memmap TZDRAM area containing the SC7 Entry Firmware */ 179 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { 180 181 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE); 182 183 /* 184 * Verify that the SC7 entry firmware resides inside the TZDRAM 185 * aperture, _before_ the BL31 code and the start address is 186 * exactly 1MB from BL31 base. 187 */ 188 189 /* sc7entry-fw must be _before_ BL31 base */ 190 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); 191 192 sc7entry_end = plat_params->sc7entry_fw_base + 193 plat_params->sc7entry_fw_size; 194 assert(sc7entry_end < plat_params->tzdram_base); 195 196 /* sc7entry-fw start must be exactly 1MB behind BL31 base */ 197 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; 198 assert(offset == 0x100000); 199 200 /* secure TZDRAM area */ 201 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, 202 plat_params->tzdram_size + offset); 203 204 /* power off BPMP processor until SC7 entry */ 205 tegra_fc_bpmp_off(); 206 207 /* memmap SC7 entry firmware code */ 208 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base, 209 plat_params->sc7entry_fw_base, 210 plat_params->sc7entry_fw_size, 211 MT_SECURE | MT_RO_DATA); 212 assert(ret == 0); 213 214 /* restrict PMC access to secure world */ 215 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); 216 val |= PMC_SECURITY_EN_BIT; 217 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); 218 } 219 } 220 221 /******************************************************************************* 222 * Initialize the GIC and SGIs 223 ******************************************************************************/ 224 void plat_gic_setup(void) 225 { 226 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props)); 227 tegra_gic_init(); 228 229 /* Enable handling for FIQs */ 230 tegra_fiq_handler_setup(); 231 232 /* 233 * Enable routing watchdog FIQs from the flow controller to 234 * the GICD. 235 */ 236 tegra_fc_enable_fiq_to_ccplex_routing(); 237 } 238