1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <denver.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/psci/psci.h> 19 #include <mce.h> 20 #include <mce_private.h> 21 #include <plat/common/platform.h> 22 #include <se.h> 23 #include <smmu.h> 24 #include <t194_nvg.h> 25 #include <tegra194_private.h> 26 #include <tegra_platform.h> 27 #include <tegra_private.h> 28 29 extern void tegra194_cpu_reset_handler(void); 30 extern uint32_t __tegra194_cpu_reset_handler_data, 31 __tegra194_cpu_reset_handler_end; 32 33 /* TZDRAM offset for saving SMMU context */ 34 #define TEGRA194_SMMU_CTX_OFFSET 16U 35 36 /* state id mask */ 37 #define TEGRA194_STATE_ID_MASK 0xFU 38 /* constants to get power state's wake time */ 39 #define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U 40 #define TEGRA194_WAKE_TIME_SHIFT 4U 41 /* default core wake mask for CPU_SUSPEND */ 42 #define TEGRA194_CORE_WAKE_MASK 0x180cU 43 44 static struct t19x_psci_percpu_data { 45 uint32_t wake_time; 46 } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; 47 48 /* 49 * tegra_fake_system_suspend acts as a boolean var controlling whether 50 * we are going to take fake system suspend code or normal system suspend code 51 * path. This variable is set inside the sip call handlers, when the kernel 52 * requests an SIP call to set the suspend debug flags. 53 */ 54 bool tegra_fake_system_suspend; 55 56 int32_t tegra_soc_validate_power_state(uint32_t power_state, 57 psci_power_state_t *req_state) 58 { 59 uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & 60 TEGRA194_STATE_ID_MASK; 61 uint32_t cpu = plat_my_core_pos(); 62 int32_t ret = PSCI_E_SUCCESS; 63 64 /* save the core wake time (in TSC ticks)*/ 65 t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK) 66 << TEGRA194_WAKE_TIME_SHIFT; 67 68 /* 69 * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that 70 * the correct value is read in tegra_soc_pwr_domain_suspend(), which 71 * is called with caches disabled. It is possible to read a stale value 72 * from DRAM in that function, because the L2 cache is not flushed 73 * unless the cluster is entering CC6/CC7. 74 */ 75 clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], 76 sizeof(t19x_percpu_data[cpu])); 77 78 /* Sanity check the requested state id */ 79 switch (state_id) { 80 case PSTATE_ID_CORE_IDLE: 81 case PSTATE_ID_CORE_POWERDN: 82 83 /* Core powerdown request */ 84 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 85 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 86 87 break; 88 89 default: 90 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 91 ret = PSCI_E_INVALID_PARAMS; 92 break; 93 } 94 95 return ret; 96 } 97 98 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 99 { 100 const plat_local_state_t *pwr_domain_state; 101 uint8_t stateid_afflvl0, stateid_afflvl2; 102 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 103 uint64_t smmu_ctx_base; 104 uint32_t val; 105 mce_cstate_info_t sc7_cstate_info = { 106 .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, 107 .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, 108 .system_state_force = 1U, 109 .update_wake_mask = 1U, 110 }; 111 uint32_t cpu = plat_my_core_pos(); 112 int32_t ret = 0; 113 114 /* get the state ID */ 115 pwr_domain_state = target_state->pwr_domain_state; 116 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 117 TEGRA194_STATE_ID_MASK; 118 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 119 TEGRA194_STATE_ID_MASK; 120 121 if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || 122 (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { 123 124 /* Enter CPU idle/powerdown */ 125 val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? 126 (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; 127 ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, 128 percpu_data[cpu].wake_time, 0); 129 assert(ret == 0); 130 131 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 132 133 /* save 'Secure Boot' Processor Feature Config Register */ 134 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 135 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); 136 137 /* save SMMU context */ 138 smmu_ctx_base = params_from_bl2->tzdram_base + 139 tegra194_get_smmu_ctx_offset(); 140 tegra_smmu_save_context((uintptr_t)smmu_ctx_base); 141 142 /* 143 * Suspend SE, RNG1 and PKA1 only on silcon and fpga, 144 * since VDK does not support atomic se ctx save 145 */ 146 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 147 ret = tegra_se_suspend(); 148 assert(ret == 0); 149 } 150 151 if (!tegra_fake_system_suspend) { 152 153 /* Prepare for system suspend */ 154 mce_update_cstate_info(&sc7_cstate_info); 155 156 do { 157 val = (uint32_t)mce_command_handler( 158 (uint32_t)MCE_CMD_IS_SC7_ALLOWED, 159 (uint32_t)TEGRA_NVG_CORE_C7, 160 MCE_CORE_SLEEP_TIME_INFINITE, 161 0U); 162 } while (val == 0U); 163 164 /* Instruct the MCE to enter system suspend state */ 165 ret = mce_command_handler( 166 (uint64_t)MCE_CMD_ENTER_CSTATE, 167 (uint64_t)TEGRA_NVG_CORE_C7, 168 MCE_CORE_SLEEP_TIME_INFINITE, 169 0U); 170 assert(ret == 0); 171 172 /* set system suspend state for house-keeping */ 173 tegra194_set_system_suspend_entry(); 174 } 175 } else { 176 ; /* do nothing */ 177 } 178 179 return PSCI_E_SUCCESS; 180 } 181 182 /******************************************************************************* 183 * Helper function to check if this is the last ON CPU in the cluster 184 ******************************************************************************/ 185 static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, 186 uint32_t ncpu) 187 { 188 plat_local_state_t target; 189 bool last_on_cpu = true; 190 uint32_t num_cpus = ncpu, pos = 0; 191 192 do { 193 target = states[pos]; 194 if (target != PLAT_MAX_OFF_STATE) { 195 last_on_cpu = false; 196 } 197 --num_cpus; 198 pos++; 199 } while (num_cpus != 0U); 200 201 return last_on_cpu; 202 } 203 204 /******************************************************************************* 205 * Helper function to get target power state for the cluster 206 ******************************************************************************/ 207 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, 208 uint32_t ncpu) 209 { 210 uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; 211 plat_local_state_t target = states[core_pos]; 212 mce_cstate_info_t cstate_info = { 0 }; 213 214 /* CPU suspend */ 215 if (target == PSTATE_ID_CORE_POWERDN) { 216 217 /* Program default wake mask */ 218 cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; 219 cstate_info.update_wake_mask = 1; 220 mce_update_cstate_info(&cstate_info); 221 } 222 223 /* CPU off */ 224 if (target == PLAT_MAX_OFF_STATE) { 225 226 /* Enable cluster powerdn from last CPU in the cluster */ 227 if (tegra_last_on_cpu_in_cluster(states, ncpu)) { 228 229 /* Enable CC6 state and turn off wake mask */ 230 cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; 231 cstate_info.update_wake_mask = 1U; 232 mce_update_cstate_info(&cstate_info); 233 234 } else { 235 236 /* Turn off wake_mask */ 237 cstate_info.update_wake_mask = 1U; 238 mce_update_cstate_info(&cstate_info); 239 target = PSCI_LOCAL_STATE_RUN; 240 } 241 } 242 243 return target; 244 } 245 246 /******************************************************************************* 247 * Platform handler to calculate the proper target power level at the 248 * specified affinity level 249 ******************************************************************************/ 250 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 251 const plat_local_state_t *states, 252 uint32_t ncpu) 253 { 254 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 255 uint32_t cpu = plat_my_core_pos(); 256 257 /* System Suspend */ 258 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { 259 target = PSTATE_ID_SOC_POWERDN; 260 } 261 262 /* CPU off, CPU suspend */ 263 if (lvl == (uint32_t)MPIDR_AFFLVL1) { 264 target = tegra_get_afflvl1_pwr_state(states, ncpu); 265 } 266 267 /* target cluster/system state */ 268 return target; 269 } 270 271 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 272 { 273 const plat_local_state_t *pwr_domain_state = 274 target_state->pwr_domain_state; 275 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 276 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 277 TEGRA194_STATE_ID_MASK; 278 uint64_t val; 279 u_register_t ns_sctlr_el1; 280 281 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 282 /* 283 * The TZRAM loses power when we enter system suspend. To 284 * allow graceful exit from system suspend, we need to copy 285 * BL3-1 over to TZDRAM. 286 */ 287 val = params_from_bl2->tzdram_base + 288 tegra194_get_cpu_reset_handler_size(); 289 memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 290 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); 291 292 /* 293 * In fake suspend mode, ensure that the loopback procedure 294 * towards system suspend exit is started, instead of calling 295 * WFI. This is done by disabling both MMU's of EL1 & El3 296 * and calling tegra_secure_entrypoint(). 297 */ 298 if (tegra_fake_system_suspend) { 299 300 /* 301 * Disable EL1's MMU. 302 */ 303 ns_sctlr_el1 = read_sctlr_el1(); 304 ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT)); 305 write_sctlr_el1(ns_sctlr_el1); 306 307 /* 308 * Disable MMU to power up the CPU in a "clean" 309 * state 310 */ 311 disable_mmu_el3(); 312 tegra_secure_entrypoint(); 313 panic(); 314 } 315 } 316 317 return PSCI_E_SUCCESS; 318 } 319 320 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) 321 { 322 uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; 323 uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 324 MPIDR_AFFINITY_BITS; 325 int32_t ret = 0; 326 327 if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { 328 ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); 329 return PSCI_E_NOT_PRESENT; 330 } 331 332 /* construct the target CPU # */ 333 target_cpu += (target_cluster << 1U); 334 335 ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); 336 if (ret < 0) { 337 return PSCI_E_DENIED; 338 } 339 340 return PSCI_E_SUCCESS; 341 } 342 343 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 344 { 345 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 346 347 /* 348 * Reset power state info for CPUs when onlining, we set 349 * deepest power when offlining a core but that may not be 350 * requested by non-secure sw which controls idle states. It 351 * will re-init this info from non-secure software when the 352 * core come online. 353 */ 354 355 /* 356 * Check if we are exiting from deep sleep and restore SE 357 * context if we are. 358 */ 359 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 360 361 /* 362 * Enable strict checking after programming the GSC for 363 * enabling TZSRAM and TZDRAM 364 */ 365 mce_enable_strict_checking(); 366 367 /* Init SMMU */ 368 tegra_smmu_init(); 369 370 /* Resume SE, RNG1 and PKA1 */ 371 tegra_se_resume(); 372 373 /* 374 * Reset power state info for the last core doing SC7 375 * entry and exit, we set deepest power state as CC7 376 * and SC7 for SC7 entry which may not be requested by 377 * non-secure SW which controls idle states. 378 */ 379 } 380 381 return PSCI_E_SUCCESS; 382 } 383 384 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 385 { 386 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 387 int32_t ret = 0; 388 389 (void)target_state; 390 391 /* Disable Denver's DCO operations */ 392 if (impl == DENVER_IMPL) { 393 denver_disable_dco(); 394 } 395 396 /* Turn off CPU */ 397 ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, 398 (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); 399 assert(ret == 0); 400 401 return PSCI_E_SUCCESS; 402 } 403 404 __dead2 void tegra_soc_prepare_system_off(void) 405 { 406 /* System power off */ 407 408 /* SC8 */ 409 410 wfi(); 411 412 /* wait for the system to power down */ 413 for (;;) { 414 ; 415 } 416 } 417 418 int32_t tegra_soc_prepare_system_reset(void) 419 { 420 return PSCI_E_SUCCESS; 421 } 422