1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #endif 29 30 /******************************************************************************* 31 * CHIP ID 32 ******************************************************************************/ 33 #define STM32MP157C_PART_NB U(0x05000000) 34 #define STM32MP157A_PART_NB U(0x05000001) 35 #define STM32MP153C_PART_NB U(0x05000024) 36 #define STM32MP153A_PART_NB U(0x05000025) 37 #define STM32MP151C_PART_NB U(0x0500002E) 38 #define STM32MP151A_PART_NB U(0x0500002F) 39 40 #define STM32MP1_REV_B U(0x2000) 41 42 /******************************************************************************* 43 * PACKAGE ID 44 ******************************************************************************/ 45 #define PKG_AA_LFBGA448 U(4) 46 #define PKG_AB_LFBGA354 U(3) 47 #define PKG_AC_TFBGA361 U(2) 48 #define PKG_AD_TFBGA257 U(1) 49 50 /******************************************************************************* 51 * STM32MP1 memory map related constants 52 ******************************************************************************/ 53 #define STM32MP_ROM_BASE U(0x00000000) 54 #define STM32MP_ROM_SIZE U(0x00020000) 55 56 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 57 #define STM32MP_SYSRAM_SIZE U(0x00040000) 58 59 /* DDR configuration */ 60 #define STM32MP_DDR_BASE U(0xC0000000) 61 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 62 #ifdef AARCH32_SP_OPTEE 63 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 64 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 65 #endif 66 67 /* DDR power initializations */ 68 #ifndef __ASSEMBLER__ 69 enum ddr_type { 70 STM32MP_DDR3, 71 STM32MP_LPDDR2, 72 STM32MP_LPDDR3 73 }; 74 #endif 75 76 /* Section used inside TF binaries */ 77 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 78 /* 256 Octets reserved for header */ 79 #define STM32MP_HEADER_SIZE U(0x00000100) 80 81 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 82 STM32MP_PARAM_LOAD_SIZE + \ 83 STM32MP_HEADER_SIZE) 84 85 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 86 (STM32MP_PARAM_LOAD_SIZE + \ 87 STM32MP_HEADER_SIZE)) 88 89 #ifdef AARCH32_SP_OPTEE 90 #define STM32MP_BL32_SIZE U(0) 91 92 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 93 94 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 95 STM32MP_OPTEE_BASE) 96 #else 97 #if STACK_PROTECTOR_ENABLED 98 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 99 #else 100 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 101 #endif 102 #endif 103 104 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 105 STM32MP_SYSRAM_SIZE - \ 106 STM32MP_BL32_SIZE) 107 108 #ifdef AARCH32_SP_OPTEE 109 #if STACK_PROTECTOR_ENABLED 110 #define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ 111 #else 112 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ 113 #endif 114 #else 115 #if STACK_PROTECTOR_ENABLED 116 #define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ 117 #else 118 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ 119 #endif 120 #endif 121 122 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 123 STM32MP_BL2_SIZE) 124 125 /* BL2 and BL32/sp_min require 5 tables */ 126 #define MAX_XLAT_TABLES 5 127 128 /* 129 * MAX_MMAP_REGIONS is usually: 130 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 131 */ 132 #if defined(IMAGE_BL2) 133 #define MAX_MMAP_REGIONS 11 134 #endif 135 #if defined(IMAGE_BL32) 136 #define MAX_MMAP_REGIONS 6 137 #endif 138 139 /* DTB initialization value */ 140 #define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */ 141 142 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 143 STM32MP_DTB_SIZE) 144 145 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 146 147 /******************************************************************************* 148 * STM32MP1 device/io map related constants (used for MMU) 149 ******************************************************************************/ 150 #define STM32MP1_DEVICE1_BASE U(0x40000000) 151 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 152 153 #define STM32MP1_DEVICE2_BASE U(0x80000000) 154 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 155 156 /******************************************************************************* 157 * STM32MP1 RCC 158 ******************************************************************************/ 159 #define RCC_BASE U(0x50000000) 160 161 /******************************************************************************* 162 * STM32MP1 PWR 163 ******************************************************************************/ 164 #define PWR_BASE U(0x50001000) 165 166 /******************************************************************************* 167 * STM32MP1 GPIO 168 ******************************************************************************/ 169 #define GPIOA_BASE U(0x50002000) 170 #define GPIOB_BASE U(0x50003000) 171 #define GPIOC_BASE U(0x50004000) 172 #define GPIOD_BASE U(0x50005000) 173 #define GPIOE_BASE U(0x50006000) 174 #define GPIOF_BASE U(0x50007000) 175 #define GPIOG_BASE U(0x50008000) 176 #define GPIOH_BASE U(0x50009000) 177 #define GPIOI_BASE U(0x5000A000) 178 #define GPIOJ_BASE U(0x5000B000) 179 #define GPIOK_BASE U(0x5000C000) 180 #define GPIOZ_BASE U(0x54004000) 181 #define GPIO_BANK_OFFSET U(0x1000) 182 183 /* Bank IDs used in GPIO driver API */ 184 #define GPIO_BANK_A U(0) 185 #define GPIO_BANK_B U(1) 186 #define GPIO_BANK_C U(2) 187 #define GPIO_BANK_D U(3) 188 #define GPIO_BANK_E U(4) 189 #define GPIO_BANK_F U(5) 190 #define GPIO_BANK_G U(6) 191 #define GPIO_BANK_H U(7) 192 #define GPIO_BANK_I U(8) 193 #define GPIO_BANK_J U(9) 194 #define GPIO_BANK_K U(10) 195 #define GPIO_BANK_Z U(25) 196 197 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 198 199 /******************************************************************************* 200 * STM32MP1 UART 201 ******************************************************************************/ 202 #define USART1_BASE U(0x5C000000) 203 #define USART2_BASE U(0x4000E000) 204 #define USART3_BASE U(0x4000F000) 205 #define UART4_BASE U(0x40010000) 206 #define UART5_BASE U(0x40011000) 207 #define USART6_BASE U(0x44003000) 208 #define UART7_BASE U(0x40018000) 209 #define UART8_BASE U(0x40019000) 210 #define STM32MP_UART_BAUDRATE U(115200) 211 212 /* For UART crash console */ 213 #define STM32MP_DEBUG_USART_BASE UART4_BASE 214 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 215 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 216 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 217 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 218 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 219 #define DEBUG_UART_TX_GPIO_PORT 11 220 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 221 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 222 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 223 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 224 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 225 226 /******************************************************************************* 227 * STM32MP1 TZC (TZ400) 228 ******************************************************************************/ 229 #define STM32MP1_TZC_BASE U(0x5C006000) 230 231 #define STM32MP1_TZC_A7_ID U(0) 232 #define STM32MP1_TZC_M4_ID U(1) 233 #define STM32MP1_TZC_LCD_ID U(3) 234 #define STM32MP1_TZC_GPU_ID U(4) 235 #define STM32MP1_TZC_MDMA_ID U(5) 236 #define STM32MP1_TZC_DMA_ID U(6) 237 #define STM32MP1_TZC_USB_HOST_ID U(7) 238 #define STM32MP1_TZC_USB_OTG_ID U(8) 239 #define STM32MP1_TZC_SDMMC_ID U(9) 240 #define STM32MP1_TZC_ETH_ID U(10) 241 #define STM32MP1_TZC_DAP_ID U(15) 242 243 #define STM32MP1_FILTER_BIT_ALL U(3) 244 245 /******************************************************************************* 246 * STM32MP1 SDMMC 247 ******************************************************************************/ 248 #define STM32MP_SDMMC1_BASE U(0x58005000) 249 #define STM32MP_SDMMC2_BASE U(0x58007000) 250 #define STM32MP_SDMMC3_BASE U(0x48004000) 251 252 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 253 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 254 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 255 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 256 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 257 258 /******************************************************************************* 259 * STM32MP1 BSEC / OTP 260 ******************************************************************************/ 261 #define STM32MP1_OTP_MAX_ID 0x5FU 262 #define STM32MP1_UPPER_OTP_START 0x20U 263 264 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 265 266 /* OTP offsets */ 267 #define DATA0_OTP U(0) 268 #define PART_NUMBER_OTP U(1) 269 #define PACKAGE_OTP U(16) 270 #define HW2_OTP U(18) 271 272 /* OTP mask */ 273 /* DATA0 */ 274 #define DATA0_OTP_SECURED BIT(6) 275 276 /* PART NUMBER */ 277 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 278 #define PART_NUMBER_OTP_PART_SHIFT 0 279 280 /* PACKAGE */ 281 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 282 #define PACKAGE_OTP_PKG_SHIFT 27 283 284 /* IWDG OTP */ 285 #define HW2_OTP_IWDG_HW_POS U(3) 286 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 287 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 288 289 /* HW2 OTP */ 290 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 291 292 /******************************************************************************* 293 * STM32MP1 TAMP 294 ******************************************************************************/ 295 #define TAMP_BASE U(0x5C00A000) 296 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 297 298 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 299 static inline uint32_t tamp_bkpr(uint32_t idx) 300 { 301 return TAMP_BKP_REGISTER_BASE + (idx << 2); 302 } 303 #endif 304 305 /******************************************************************************* 306 * STM32MP1 DDRCTRL 307 ******************************************************************************/ 308 #define DDRCTRL_BASE U(0x5A003000) 309 310 /******************************************************************************* 311 * STM32MP1 DDRPHYC 312 ******************************************************************************/ 313 #define DDRPHYC_BASE U(0x5A004000) 314 315 /******************************************************************************* 316 * STM32MP1 IWDG 317 ******************************************************************************/ 318 #define IWDG_MAX_INSTANCE U(2) 319 #define IWDG1_INST U(0) 320 #define IWDG2_INST U(1) 321 322 #define IWDG1_BASE U(0x5C003000) 323 #define IWDG2_BASE U(0x5A002000) 324 325 /******************************************************************************* 326 * STM32MP1 I2C4 327 ******************************************************************************/ 328 #define I2C4_BASE U(0x5C002000) 329 330 /******************************************************************************* 331 * STM32MP1 DBGMCU 332 ******************************************************************************/ 333 #define DBGMCU_BASE U(0x50081000) 334 335 /******************************************************************************* 336 * Device Tree defines 337 ******************************************************************************/ 338 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 339 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 340 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 341 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 342 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 343 344 #endif /* STM32MP1_DEF_H */ 345