1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "agilex_clock_manager.h" 19 #include "agilex_memory_controller.h" 20 #include "agilex_pinmux.h" 21 #include "agilex_reset_manager.h" 22 #include "agilex_system_manager.h" 23 #include "ccu/ncore_ccu.h" 24 #include "qspi/cadence_qspi.h" 25 #include "socfpga_handoff.h" 26 #include "socfpga_mailbox.h" 27 #include "socfpga_private.h" 28 #include "wdt/watchdog.h" 29 30 31 const mmap_region_t agilex_plat_mmap[] = { 32 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 33 MT_MEMORY | MT_RW | MT_NS), 34 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 35 MT_DEVICE | MT_RW | MT_NS), 36 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 37 MT_DEVICE | MT_RW | MT_SECURE), 38 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 39 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 41 MT_DEVICE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 43 MT_DEVICE | MT_RW | MT_NS), 44 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 45 MT_DEVICE | MT_RW | MT_NS), 46 {0}, 47 }; 48 49 boot_source_type boot_source; 50 51 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 52 u_register_t x2, u_register_t x4) 53 { 54 static console_16550_t console; 55 handoff reverse_handoff_ptr; 56 57 generic_delay_timer_init(); 58 59 if (socfpga_get_handoff(&reverse_handoff_ptr)) 60 return; 61 config_pinmux(&reverse_handoff_ptr); 62 boot_source = reverse_handoff_ptr.boot_source; 63 config_clkmgr_handoff(&reverse_handoff_ptr); 64 65 enable_nonsecure_access(); 66 deassert_peripheral_reset(); 67 config_hps_hs_before_warm_reset(); 68 69 watchdog_init(get_wdt_clk()); 70 71 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 72 &console); 73 74 socfpga_delay_timer_init(); 75 init_ncore_ccu(); 76 init_hard_memory_controller(); 77 enable_ns_bridge_access(); 78 } 79 80 81 void bl2_el3_plat_arch_setup(void) 82 { 83 84 struct mmc_device_info info; 85 const mmap_region_t bl_regions[] = { 86 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 87 MT_MEMORY | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 89 MT_CODE | MT_SECURE), 90 MAP_REGION_FLAT(BL_RO_DATA_BASE, 91 BL_RO_DATA_END - BL_RO_DATA_BASE, 92 MT_RO_DATA | MT_SECURE), 93 #if USE_COHERENT_MEM_BAR 94 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 95 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 96 MT_DEVICE | MT_RW | MT_SECURE), 97 #endif 98 {0}, 99 }; 100 101 setup_page_tables(bl_regions, agilex_plat_mmap); 102 103 enable_mmu_el3(0); 104 105 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 106 107 info.mmc_dev_type = MMC_IS_SD; 108 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 109 110 mailbox_init(); 111 112 switch (boot_source) { 113 case BOOT_SOURCE_SDMMC: 114 dw_mmc_init(¶ms, &info); 115 socfpga_io_setup(boot_source); 116 break; 117 118 case BOOT_SOURCE_QSPI: 119 mailbox_set_qspi_open(); 120 mailbox_set_qspi_direct(); 121 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 122 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 123 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 124 socfpga_io_setup(boot_source); 125 break; 126 127 default: 128 ERROR("Unsupported boot source\n"); 129 panic(); 130 break; 131 } 132 } 133 134 uint32_t get_spsr_for_bl33_entry(void) 135 { 136 unsigned long el_status; 137 unsigned int mode; 138 uint32_t spsr; 139 140 /* Figure out what mode we enter the non-secure world in */ 141 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 142 el_status &= ID_AA64PFR0_ELX_MASK; 143 144 mode = (el_status) ? MODE_EL2 : MODE_EL1; 145 146 /* 147 * TODO: Consider the possibility of specifying the SPSR in 148 * the FIP ToC and allowing the platform to have a say as 149 * well. 150 */ 151 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 152 return spsr; 153 } 154 155 156 int bl2_plat_handle_post_image_load(unsigned int image_id) 157 { 158 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 159 160 switch (image_id) { 161 case BL33_IMAGE_ID: 162 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 163 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 164 break; 165 default: 166 break; 167 } 168 169 return 0; 170 } 171 172 /******************************************************************************* 173 * Perform any BL3-1 platform setup code 174 ******************************************************************************/ 175 void bl2_platform_setup(void) 176 { 177 } 178 179