1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/utils.h> 26 #include <plat/common/platform.h> 27 #include <smccc_helpers.h> 28 29 30 /******************************************************************************* 31 * Context management library initialisation routine. This library is used by 32 * runtime services to share pointers to 'cpu_context' structures for the secure 33 * and non-secure states. Management of the structures and their associated 34 * memory is not done by the context management library e.g. the PSCI service 35 * manages the cpu context used for entry from and exit to the non-secure state. 36 * The Secure payload dispatcher service manages the context(s) corresponding to 37 * the secure state. It also uses this library to get access to the non-secure 38 * state cpu context pointers. 39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 40 * which will used for programming an entry into a lower EL. The same context 41 * will used to save state upon exception entry from that EL. 42 ******************************************************************************/ 43 void __init cm_init(void) 44 { 45 /* 46 * The context management library has only global data to intialize, but 47 * that will be done when the BSS is zeroed out 48 */ 49 } 50 51 /******************************************************************************* 52 * The following function initializes the cpu_context 'ctx' for 53 * first use, and sets the initial entrypoint state as specified by the 54 * entry_point_info structure. 55 * 56 * The security state to initialize is determined by the SECURE attribute 57 * of the entry_point_info. 58 * 59 * The EE and ST attributes are used to configure the endianness and secure 60 * timer availability for the new execution context. 61 * 62 * To prepare the register state for entry call cm_prepare_el3_exit() and 63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 64 * cm_e1_sysreg_context_restore(). 65 ******************************************************************************/ 66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 67 { 68 unsigned int security_state; 69 uint32_t scr_el3; 70 el3_state_t *state; 71 gp_regs_t *gp_regs; 72 u_register_t sctlr_elx, actlr_elx; 73 74 assert(ctx != NULL); 75 76 security_state = GET_SECURITY_STATE(ep->h.attr); 77 78 /* Clear any residual register values from the context */ 79 zeromem(ctx, sizeof(*ctx)); 80 81 /* 82 * SCR_EL3 was initialised during reset sequence in macro 83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 84 * affect the next EL. 85 * 86 * The following fields are initially set to zero and then updated to 87 * the required value depending on the state of the SPSR_EL3 and the 88 * Security state and entrypoint attributes of the next EL. 89 */ 90 scr_el3 = (uint32_t)read_scr(); 91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 92 SCR_ST_BIT | SCR_HCE_BIT); 93 /* 94 * SCR_NS: Set the security state of the next EL. 95 */ 96 if (security_state != SECURE) 97 scr_el3 |= SCR_NS_BIT; 98 /* 99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 100 * Exception level as specified by SPSR. 101 */ 102 if (GET_RW(ep->spsr) == MODE_RW_64) 103 scr_el3 |= SCR_RW_BIT; 104 /* 105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 106 * Secure timer registers to EL3, from AArch64 state only, if specified 107 * by the entrypoint attributes. 108 */ 109 if (EP_GET_ST(ep->h.attr) != 0U) 110 scr_el3 |= SCR_ST_BIT; 111 112 #if !HANDLE_EA_EL3_FIRST 113 /* 114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 115 * to EL3 when executing at a lower EL. When executing at EL3, External 116 * Aborts are taken to EL3. 117 */ 118 scr_el3 &= ~SCR_EA_BIT; 119 #endif 120 121 #if FAULT_INJECTION_SUPPORT 122 /* Enable fault injection from lower ELs */ 123 scr_el3 |= SCR_FIEN_BIT; 124 #endif 125 126 #if !CTX_INCLUDE_PAUTH_REGS 127 /* 128 * If the pointer authentication registers aren't saved during world 129 * switches the value of the registers can be leaked from the Secure to 130 * the Non-secure world. To prevent this, rather than enabling pointer 131 * authentication everywhere, we only enable it in the Non-secure world. 132 * 133 * If the Secure world wants to use pointer authentication, 134 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 135 */ 136 if (security_state == NON_SECURE) 137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 138 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 139 140 /* 141 * Enable MTE support. Support is enabled unilaterally for the normal 142 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 143 * set. 144 */ 145 #if CTX_INCLUDE_MTE_REGS 146 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 147 scr_el3 |= SCR_ATA_BIT; 148 #else 149 unsigned int mte = get_armv8_5_mte_support(); 150 if (mte == MTE_IMPLEMENTED_EL0) { 151 /* 152 * Can enable MTE across both worlds as no MTE registers are 153 * used 154 */ 155 scr_el3 |= SCR_ATA_BIT; 156 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 157 /* 158 * Can only enable MTE in Non-Secure world without register 159 * saving 160 */ 161 scr_el3 |= SCR_ATA_BIT; 162 } 163 #endif 164 165 #ifdef IMAGE_BL31 166 /* 167 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 168 * indicated by the interrupt routing model for BL31. 169 */ 170 scr_el3 |= get_scr_el3_from_routing_model(security_state); 171 #endif 172 173 /* 174 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 175 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 176 * next mode is Hyp. 177 */ 178 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 179 || ((GET_RW(ep->spsr) != MODE_RW_64) 180 && (GET_M32(ep->spsr) == MODE32_hyp))) { 181 scr_el3 |= SCR_HCE_BIT; 182 } 183 184 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 185 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) 186 scr_el3 |= SCR_EEL2_BIT; 187 188 /* 189 * Initialise SCTLR_EL1 to the reset value corresponding to the target 190 * execution state setting all fields rather than relying of the hw. 191 * Some fields have architecturally UNKNOWN reset values and these are 192 * set to zero. 193 * 194 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 195 * 196 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 197 * required by PSCI specification) 198 */ 199 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 200 if (GET_RW(ep->spsr) == MODE_RW_64) 201 sctlr_elx |= SCTLR_EL1_RES1; 202 else { 203 /* 204 * If the target execution state is AArch32 then the following 205 * fields need to be set. 206 * 207 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 208 * instructions are not trapped to EL1. 209 * 210 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 211 * instructions are not trapped to EL1. 212 * 213 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 214 * CP15DMB, CP15DSB, and CP15ISB instructions. 215 */ 216 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 217 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 218 } 219 220 #if ERRATA_A75_764081 221 /* 222 * If workaround of errata 764081 for Cortex-A75 is used then set 223 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 224 */ 225 sctlr_elx |= SCTLR_IESB_BIT; 226 #endif 227 228 /* 229 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 230 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 231 * are not part of the stored cpu_context. 232 */ 233 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 234 235 /* 236 * Base the context ACTLR_EL1 on the current value, as it is 237 * implementation defined. The context restore process will write 238 * the value from the context to the actual register and can cause 239 * problems for processor cores that don't expect certain bits to 240 * be zero. 241 */ 242 actlr_elx = read_actlr_el1(); 243 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 244 245 /* 246 * Populate EL3 state so that we've the right context 247 * before doing ERET 248 */ 249 state = get_el3state_ctx(ctx); 250 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 251 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 252 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 253 254 /* 255 * Store the X0-X7 value from the entrypoint into the context 256 * Use memcpy as we are in control of the layout of the structures 257 */ 258 gp_regs = get_gpregs_ctx(ctx); 259 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 260 } 261 262 /******************************************************************************* 263 * Enable architecture extensions on first entry to Non-secure world. 264 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 265 * it is zero. 266 ******************************************************************************/ 267 static void enable_extensions_nonsecure(bool el2_unused) 268 { 269 #if IMAGE_BL31 270 #if ENABLE_SPE_FOR_LOWER_ELS 271 spe_enable(el2_unused); 272 #endif 273 274 #if ENABLE_AMU 275 amu_enable(el2_unused); 276 #endif 277 278 #if ENABLE_SVE_FOR_NS 279 sve_enable(el2_unused); 280 #endif 281 282 #if ENABLE_MPAM_FOR_LOWER_ELS 283 mpam_enable(el2_unused); 284 #endif 285 #endif 286 } 287 288 /******************************************************************************* 289 * The following function initializes the cpu_context for a CPU specified by 290 * its `cpu_idx` for first use, and sets the initial entrypoint state as 291 * specified by the entry_point_info structure. 292 ******************************************************************************/ 293 void cm_init_context_by_index(unsigned int cpu_idx, 294 const entry_point_info_t *ep) 295 { 296 cpu_context_t *ctx; 297 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 298 cm_setup_context(ctx, ep); 299 } 300 301 /******************************************************************************* 302 * The following function initializes the cpu_context for the current CPU 303 * for first use, and sets the initial entrypoint state as specified by the 304 * entry_point_info structure. 305 ******************************************************************************/ 306 void cm_init_my_context(const entry_point_info_t *ep) 307 { 308 cpu_context_t *ctx; 309 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 310 cm_setup_context(ctx, ep); 311 } 312 313 /******************************************************************************* 314 * Prepare the CPU system registers for first entry into secure or normal world 315 * 316 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 317 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 318 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 319 * For all entries, the EL1 registers are initialized from the cpu_context 320 ******************************************************************************/ 321 void cm_prepare_el3_exit(uint32_t security_state) 322 { 323 uint32_t sctlr_elx, scr_el3, mdcr_el2; 324 cpu_context_t *ctx = cm_get_context(security_state); 325 bool el2_unused = false; 326 uint64_t hcr_el2 = 0U; 327 328 assert(ctx != NULL); 329 330 if (security_state == NON_SECURE) { 331 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 332 CTX_SCR_EL3); 333 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 334 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 335 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 336 CTX_SCTLR_EL1); 337 sctlr_elx &= SCTLR_EE_BIT; 338 sctlr_elx |= SCTLR_EL2_RES1; 339 #if ERRATA_A75_764081 340 /* 341 * If workaround of errata 764081 for Cortex-A75 is used 342 * then set SCTLR_EL2.IESB to enable Implicit Error 343 * Synchronization Barrier. 344 */ 345 sctlr_elx |= SCTLR_IESB_BIT; 346 #endif 347 write_sctlr_el2(sctlr_elx); 348 } else if (el_implemented(2) != EL_IMPL_NONE) { 349 el2_unused = true; 350 351 /* 352 * EL2 present but unused, need to disable safely. 353 * SCTLR_EL2 can be ignored in this case. 354 * 355 * Set EL2 register width appropriately: Set HCR_EL2 356 * field to match SCR_EL3.RW. 357 */ 358 if ((scr_el3 & SCR_RW_BIT) != 0U) 359 hcr_el2 |= HCR_RW_BIT; 360 361 /* 362 * For Armv8.3 pointer authentication feature, disable 363 * traps to EL2 when accessing key registers or using 364 * pointer authentication instructions from lower ELs. 365 */ 366 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 367 368 write_hcr_el2(hcr_el2); 369 370 /* 371 * Initialise CPTR_EL2 setting all fields rather than 372 * relying on the hw. All fields have architecturally 373 * UNKNOWN reset values. 374 * 375 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 376 * accesses to the CPACR_EL1 or CPACR from both 377 * Execution states do not trap to EL2. 378 * 379 * CPTR_EL2.TTA: Set to zero so that Non-secure System 380 * register accesses to the trace registers from both 381 * Execution states do not trap to EL2. 382 * 383 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 384 * to SIMD and floating-point functionality from both 385 * Execution states do not trap to EL2. 386 */ 387 write_cptr_el2(CPTR_EL2_RESET_VAL & 388 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 389 | CPTR_EL2_TFP_BIT)); 390 391 /* 392 * Initialise CNTHCTL_EL2. All fields are 393 * architecturally UNKNOWN on reset and are set to zero 394 * except for field(s) listed below. 395 * 396 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 397 * Hyp mode of Non-secure EL0 and EL1 accesses to the 398 * physical timer registers. 399 * 400 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 401 * Hyp mode of Non-secure EL0 and EL1 accesses to the 402 * physical counter registers. 403 */ 404 write_cnthctl_el2(CNTHCTL_RESET_VAL | 405 EL1PCEN_BIT | EL1PCTEN_BIT); 406 407 /* 408 * Initialise CNTVOFF_EL2 to zero as it resets to an 409 * architecturally UNKNOWN value. 410 */ 411 write_cntvoff_el2(0); 412 413 /* 414 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 415 * MPIDR_EL1 respectively. 416 */ 417 write_vpidr_el2(read_midr_el1()); 418 write_vmpidr_el2(read_mpidr_el1()); 419 420 /* 421 * Initialise VTTBR_EL2. All fields are architecturally 422 * UNKNOWN on reset. 423 * 424 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 425 * 2 address translation is disabled, cache maintenance 426 * operations depend on the VMID. 427 * 428 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 429 * translation is disabled. 430 */ 431 write_vttbr_el2(VTTBR_RESET_VAL & 432 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 433 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 434 435 /* 436 * Initialise MDCR_EL2, setting all fields rather than 437 * relying on hw. Some fields are architecturally 438 * UNKNOWN on reset. 439 * 440 * MDCR_EL2.HLP: Set to one so that event counter 441 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 442 * occurs on the increment that changes 443 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 444 * implemented. This bit is RES0 in versions of the 445 * architecture earlier than ARMv8.5, setting it to 1 446 * doesn't have any effect on them. 447 * 448 * MDCR_EL2.TTRF: Set to zero so that access to Trace 449 * Filter Control register TRFCR_EL1 at EL1 is not 450 * trapped to EL2. This bit is RES0 in versions of 451 * the architecture earlier than ARMv8.4. 452 * 453 * MDCR_EL2.HPMD: Set to one so that event counting is 454 * prohibited at EL2. This bit is RES0 in versions of 455 * the architecture earlier than ARMv8.1, setting it 456 * to 1 doesn't have any effect on them. 457 * 458 * MDCR_EL2.TPMS: Set to zero so that accesses to 459 * Statistical Profiling control registers from EL1 460 * do not trap to EL2. This bit is RES0 when SPE is 461 * not implemented. 462 * 463 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 464 * EL1 System register accesses to the Debug ROM 465 * registers are not trapped to EL2. 466 * 467 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 468 * System register accesses to the powerdown debug 469 * registers are not trapped to EL2. 470 * 471 * MDCR_EL2.TDA: Set to zero so that System register 472 * accesses to the debug registers do not trap to EL2. 473 * 474 * MDCR_EL2.TDE: Set to zero so that debug exceptions 475 * are not routed to EL2. 476 * 477 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 478 * Monitors. 479 * 480 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 481 * EL1 accesses to all Performance Monitors registers 482 * are not trapped to EL2. 483 * 484 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 485 * and EL1 accesses to the PMCR_EL0 or PMCR are not 486 * trapped to EL2. 487 * 488 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 489 * architecturally-defined reset value. 490 */ 491 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 492 MDCR_EL2_HPMD) | 493 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 494 >> PMCR_EL0_N_SHIFT)) & 495 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 496 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 497 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 498 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 499 MDCR_EL2_TPMCR_BIT); 500 501 write_mdcr_el2(mdcr_el2); 502 503 /* 504 * Initialise HSTR_EL2. All fields are architecturally 505 * UNKNOWN on reset. 506 * 507 * HSTR_EL2.T<n>: Set all these fields to zero so that 508 * Non-secure EL0 or EL1 accesses to System registers 509 * do not trap to EL2. 510 */ 511 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 512 /* 513 * Initialise CNTHP_CTL_EL2. All fields are 514 * architecturally UNKNOWN on reset. 515 * 516 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 517 * physical timer and prevent timer interrupts. 518 */ 519 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 520 ~(CNTHP_CTL_ENABLE_BIT)); 521 } 522 enable_extensions_nonsecure(el2_unused); 523 } 524 525 cm_el1_sysregs_context_restore(security_state); 526 cm_set_next_eret_context(security_state); 527 } 528 529 /******************************************************************************* 530 * The next four functions are used by runtime services to save and restore 531 * EL1 context on the 'cpu_context' structure for the specified security 532 * state. 533 ******************************************************************************/ 534 void cm_el1_sysregs_context_save(uint32_t security_state) 535 { 536 cpu_context_t *ctx; 537 538 ctx = cm_get_context(security_state); 539 assert(ctx != NULL); 540 541 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 542 543 #if IMAGE_BL31 544 if (security_state == SECURE) 545 PUBLISH_EVENT(cm_exited_secure_world); 546 else 547 PUBLISH_EVENT(cm_exited_normal_world); 548 #endif 549 } 550 551 void cm_el1_sysregs_context_restore(uint32_t security_state) 552 { 553 cpu_context_t *ctx; 554 555 ctx = cm_get_context(security_state); 556 assert(ctx != NULL); 557 558 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 559 560 #if IMAGE_BL31 561 if (security_state == SECURE) 562 PUBLISH_EVENT(cm_entering_secure_world); 563 else 564 PUBLISH_EVENT(cm_entering_normal_world); 565 #endif 566 } 567 568 /******************************************************************************* 569 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 570 * given security state with the given entrypoint 571 ******************************************************************************/ 572 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 573 { 574 cpu_context_t *ctx; 575 el3_state_t *state; 576 577 ctx = cm_get_context(security_state); 578 assert(ctx != NULL); 579 580 /* Populate EL3 state so that ERET jumps to the correct entry */ 581 state = get_el3state_ctx(ctx); 582 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 583 } 584 585 /******************************************************************************* 586 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 587 * pertaining to the given security state 588 ******************************************************************************/ 589 void cm_set_elr_spsr_el3(uint32_t security_state, 590 uintptr_t entrypoint, uint32_t spsr) 591 { 592 cpu_context_t *ctx; 593 el3_state_t *state; 594 595 ctx = cm_get_context(security_state); 596 assert(ctx != NULL); 597 598 /* Populate EL3 state so that ERET jumps to the correct entry */ 599 state = get_el3state_ctx(ctx); 600 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 601 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 602 } 603 604 /******************************************************************************* 605 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 606 * pertaining to the given security state using the value and bit position 607 * specified in the parameters. It preserves all other bits. 608 ******************************************************************************/ 609 void cm_write_scr_el3_bit(uint32_t security_state, 610 uint32_t bit_pos, 611 uint32_t value) 612 { 613 cpu_context_t *ctx; 614 el3_state_t *state; 615 uint32_t scr_el3; 616 617 ctx = cm_get_context(security_state); 618 assert(ctx != NULL); 619 620 /* Ensure that the bit position is a valid one */ 621 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 622 623 /* Ensure that the 'value' is only a bit wide */ 624 assert(value <= 1U); 625 626 /* 627 * Get the SCR_EL3 value from the cpu context, clear the desired bit 628 * and set it to its new value. 629 */ 630 state = get_el3state_ctx(ctx); 631 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 632 scr_el3 &= ~(1U << bit_pos); 633 scr_el3 |= value << bit_pos; 634 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 635 } 636 637 /******************************************************************************* 638 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 639 * given security state. 640 ******************************************************************************/ 641 uint32_t cm_get_scr_el3(uint32_t security_state) 642 { 643 cpu_context_t *ctx; 644 el3_state_t *state; 645 646 ctx = cm_get_context(security_state); 647 assert(ctx != NULL); 648 649 /* Populate EL3 state so that ERET jumps to the correct entry */ 650 state = get_el3state_ctx(ctx); 651 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 652 } 653 654 /******************************************************************************* 655 * This function is used to program the context that's used for exception 656 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 657 * the required security state 658 ******************************************************************************/ 659 void cm_set_next_eret_context(uint32_t security_state) 660 { 661 cpu_context_t *ctx; 662 663 ctx = cm_get_context(security_state); 664 assert(ctx != NULL); 665 666 cm_set_next_context(ctx); 667 } 668