| 204fd991 | 29-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "errata: workaround for Cortex A77 errata 1791578" into integration |
| 0c5e7d1c | 22-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is conf
feat(sve): enable SVE for the secure world
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD.
ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the
platform. SVE is configured during initial setup and then uses EL3
context save/restore routine to switch between SVE configurations for
different contexts.
Reset value of CPTR_EL3 changed to be most restrictive by default.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
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| 1a691455 | 30-Apr-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https
errata: workaround for Cortex A78 errata 1821534
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and
r1p0 of the A78 processor core, it is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/603e3733492bde1625aa8780
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
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| 3f0bec7c | 03-May-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
h
errata: workaround for Cortex A77 errata 1791578
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the A77 processor core, it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib4b963144f880002de308def12744b982d3df868
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| 2a008779 | 16-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
fea
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
refactor(plat/st): export functions to get SoC information
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
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| 2ea8d419 | 28-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs" into integration |
| c6ac4df6 | 18-May-2021 |
johpow01 <john.powell@arm.com> |
fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John
fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
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| 96b0596e | 20-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
The definitions of SMCCC_ARCH_SOC_ID SoC version return bits are defined
in SMC Calling Convention [1]. Add the masks and shifts for JEP-106 ban
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
The definitions of SMCCC_ARCH_SOC_ID SoC version return bits are defined
in SMC Calling Convention [1]. Add the masks and shifts for JEP-106 bank
index, JEP-106 identification code, and Implementation defined SoC ID.
Add a macro to easily set JEP-106 fields.
[1] https://developer.arm.com/documentation/den0028/latest/
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iecbd09f6de6728de89dc746d2d1981a5a97a8ab7
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| a1cedadf | 22-Apr-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(hw_crc): add support for HW computed CRC
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are en
feat(hw_crc): add support for HW computed CRC
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).
HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.
HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.
HW CRC calculation support will be used in the upcoming
firmware update patches.
Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 81579422 | 27-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I36e45c0a,I69c21293 into integration
* changes:
plat/qemu: add "max" cpu support
Add support for QEMU "max" CPU |
| 97bc7f0d | 20-Apr-2021 |
johpow01 <john.powell@arm.com> |
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from othe
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
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| 5d764e05 | 10-Mar-2021 |
Leif Lindholm <leif@nuviainc.com> |
Add support for QEMU "max" CPU
Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.
Chang
Add support for QEMU "max" CPU
Enable basic support for QEMU "max" CPU.
The "max" CPU does not attampt to emulate any specific CPU, but rather
just enables all the functions emulated by QEMU.
Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
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| e729595f | 07-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "Fix: Remove save/restore of EL2 timer registers" into integration |
| a7cf2743 | 31-Mar-2021 |
Max Shvetsov <maksims.svecovs@arm.com> |
Fix: Remove save/restore of EL2 timer registers
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following register
Fix: Remove save/restore of EL2 timer registers
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
cnthps_ctl_el2
cnthps_tval_el2
cnthps_cval_el2
cnthvs_ctl_el2
cnthvs_tval_el2
cnthvs_cval_el2
cnthp_ctl_el2
cnthp_cval_el2
cnthp_tval_el2
cnthv_ctl_el2
cnthv_cval_el2
cnthv_tval_el2
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
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| 0a144dd4 | 16-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56 |
| e5fa7459 | 29-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu ELP CPU lib" into integration |
| cb090c19 | 15-Mar-2021 |
johpow01 <john.powell@arm.com> |
Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93 |
| 447a42e7 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc9
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
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| 614c14e7 | 18-Nov-2020 |
Usama Arif <usama.arif@arm.com> |
cpus: add Matterhorn ELP ARM cpu library
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com> |
| 8ef06b6c | 02-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu CPU lib" into integration |
| ef4c1e19 | 02-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Enable v8.6 AMU enhancements (FEAT_AMUv1p1)" into integration |
| aaabf978 | 15-Oct-2020 |
johpow01 <john.powell@arm.com> |
Add Makalu CPU lib
Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d |
| 873d4241 | 02-Oct-2020 |
johpow01 <john.powell@arm.com> |
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
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| eb18ce32 | 16-Oct-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve th
plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.
To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.
This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.
Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| d56b957c | 28-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
libc: Import strtoull from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, t
libc: Import strtoull from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.
Also made small changes to fit into TF-A project. Added the source
files to the libc makefile
[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution
Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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