1# 2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7RESET_TO_BL31 := 1 8ifeq (${RESET_TO_BL31}, 0) 9$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") 10endif 11 12ifeq (${ENABLE_PIE}, 1) 13override SEPARATE_CODE_AND_RODATA := 1 14endif 15 16CTX_INCLUDE_AARCH32_REGS := 0 17ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 18$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 19endif 20 21ifeq (${TRUSTED_BOARD_BOOT}, 1) 22$(error "TRUSTED_BOARD_BOOT must be disabled") 23endif 24 25ifndef PRELOADED_BL33_BASE 26$(error "PRELOADED_BL33_BASE is not set") 27endif 28 29ifndef FPGA_PRELOADED_DTB_BASE 30$(error "FPGA_PRELOADED_DTB_BASE is not set") 31else 32$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) 33endif 34 35# Treating this as a memory-constrained port for now 36USE_COHERENT_MEM := 0 37 38# This can be overridden depending on CPU(s) used in the FPGA image 39HW_ASSISTED_COHERENCY := 1 40 41FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 42 43# select a different set of CPU files, depending on whether we compile for 44# hardware assisted coherency cores or not 45ifeq (${HW_ASSISTED_COHERENCY}, 0) 46# Cores used without DSU 47 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 48 lib/cpus/aarch64/cortex_a53.S \ 49 lib/cpus/aarch64/cortex_a57.S \ 50 lib/cpus/aarch64/cortex_a72.S \ 51 lib/cpus/aarch64/cortex_a73.S 52else 53# AArch64-only cores 54 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 55 lib/cpus/aarch64/cortex_a76ae.S \ 56 lib/cpus/aarch64/cortex_a77.S \ 57 lib/cpus/aarch64/neoverse_n1.S \ 58 lib/cpus/aarch64/neoverse_e1.S \ 59 lib/cpus/aarch64/neoverse_zeus.S \ 60 lib/cpus/aarch64/cortex_hercules.S \ 61 lib/cpus/aarch64/cortex_hercules_ae.S \ 62 lib/cpus/aarch64/cortex_a65.S \ 63 lib/cpus/aarch64/cortex_a65ae.S 64# AArch64/AArch32 cores 65 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 66 lib/cpus/aarch64/cortex_a75.S 67endif 68 69# GIC-600 configuration 70GICV3_IMPL := GIC600 71 72# Include GICv3 driver files 73include drivers/arm/gic/v3/gicv3.mk 74 75FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ 76 plat/common/plat_gicv3.c \ 77 plat/arm/board/arm_fpga/fpga_gicv3.c 78 79PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include 80 81PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S 82 83BL31_SOURCES += drivers/delay_timer/delay_timer.c \ 84 drivers/delay_timer/generic_delay_timer.c \ 85 drivers/arm/pl011/${ARCH}/pl011_console.S \ 86 plat/common/plat_psci_common.c \ 87 plat/arm/board/arm_fpga/fpga_pm.c \ 88 plat/arm/board/arm_fpga/fpga_topology.c \ 89 plat/arm/board/arm_fpga/fpga_console.c \ 90 plat/arm/board/arm_fpga/fpga_bl31_setup.c \ 91 ${FPGA_CPU_LIBS} \ 92 ${FPGA_GIC_SOURCES} 93 94all: bl31 95