1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91 92 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 93 and resulting PAuth/BTI features. 94 95 +-------+--------------+-------+-----+ 96 | Value | GCC option | PAuth | BTI | 97 +=======+==============+=======+=====+ 98 | 0 | none | N | N | 99 +-------+--------------+-------+-----+ 100 | 1 | standard | Y | Y | 101 +-------+--------------+-------+-----+ 102 | 2 | pac-ret | Y | N | 103 +-------+--------------+-------+-----+ 104 | 3 | pac-ret+leaf | Y | N | 105 +-------+--------------+-------+-----+ 106 107 This option defaults to 0 and this is an experimental feature. 108 Note that Pointer Authentication is enabled for Non-secure world 109 irrespective of the value of this option if the CPU supports it. 110 111- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 112 compilation of each build. It must be set to a C string (including quotes 113 where applicable). Defaults to a string that contains the time and date of 114 the compilation. 115 116- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 117 build to be uniquely identified. Defaults to the current git commit id. 118 119- ``CFLAGS``: Extra user options appended on the compiler's command line in 120 addition to the options set by the build system. 121 122- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 123 release several CPUs out of reset. It can take either 0 (several CPUs may be 124 brought up) or 1 (only one CPU will ever be brought up during cold reset). 125 Default is 0. If the platform always brings up a single CPU, there is no 126 need to distinguish between primary and secondary CPUs and the boot path can 127 be optimised. The ``plat_is_my_cpu_primary()`` and 128 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 129 to be implemented in this case. 130 131- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 132 Defaults to ``tbbr``. 133 134- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 135 register state when an unexpected exception occurs during execution of 136 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 137 this is only enabled for a debug build of the firmware. 138 139- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 140 certificate generation tool to create new keys in case no valid keys are 141 present or specified. Allowed options are '0' or '1'. Default is '1'. 142 143- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 144 the AArch32 system registers to be included when saving and restoring the 145 CPU context. The option must be set to 0 for AArch64-only platforms (that 146 is on hardware that does not implement AArch32, or at least not at EL1 and 147 higher ELs). Default value is 1. 148 149- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 150 operations when entering/exiting an EL2 execution context. This is of primary 151 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 152 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 153 ``SPMD_SPM_AT_SEL2`` is set. 154 155- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 156 registers to be included when saving and restoring the CPU context. Default 157 is 0. 158 159- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 160 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 161 registers to be included when saving and restoring the CPU context as 162 part of world switch. Default value is 0 and this is an experimental feature. 163 Note that Pointer Authentication is enabled for Non-secure world irrespective 164 of the value of this flag if the CPU supports it. 165 166- ``DEBUG``: Chooses between a debug and release build. It can take either 0 167 (release) or 1 (debug) as values. 0 is the default. 168 169- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 170 authenticated decryption algorithm to be used to decrypt firmware/s during 171 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 172 this flag is ``none`` to disable firmware decryption which is an optional 173 feature as per TBBR. Also, it is an experimental feature. 174 175- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 176 of the binary image. If set to 1, then only the ELF image is built. 177 0 is the default. 178 179- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 180 Board Boot authentication at runtime. This option is meant to be enabled only 181 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 182 flag has to be enabled. 0 is the default. 183 184- ``E``: Boolean option to make warnings into errors. Default is 1. 185 186- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 187 the normal boot flow. It must specify the entry point address of the EL3 188 payload. Please refer to the "Booting an EL3 payload" section for more 189 details. 190 191- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 192 This is an optional architectural feature available on v8.4 onwards. Some 193 v8.2 implementations also implement an AMU and this option can be used to 194 enable this feature on those systems as well. Default is 0. 195 196- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 197 are compiled out. For debug builds, this option defaults to 1, and calls to 198 ``assert()`` are left in place. For release builds, this option defaults to 0 199 and calls to ``assert()`` function are compiled out. This option can be set 200 independently of ``DEBUG``. It can also be used to hide any auxiliary code 201 that is only required for the assertion and does not fit in the assertion 202 itself. 203 204- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 205 dumps or not. It is supported in both AArch64 and AArch32. However, in 206 AArch32 the format of the frame records are not defined in the AAPCS and they 207 are defined by the implementation. This implementation of backtrace only 208 supports the format used by GCC when T32 interworking is disabled. For this 209 reason enabling this option in AArch32 will force the compiler to only 210 generate A32 code. This option is enabled by default only in AArch64 debug 211 builds, but this behaviour can be overridden in each platform's Makefile or 212 in the build command line. 213 214- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 215 support in GCC for TF-A. This option is currently only supported for 216 AArch64. Default is 0. 217 218- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 219 feature. MPAM is an optional Armv8.4 extension that enables various memory 220 system components and resources to define partitions; software running at 221 various ELs can assign themselves to desired partition to control their 222 performance aspects. 223 224 When this option is set to ``1``, EL3 allows lower ELs to access their own 225 MPAM registers without trapping into EL3. This option doesn't make use of 226 partitioning in EL3, however. Platform initialisation code should configure 227 and use partitions in EL3 as required. This option defaults to ``0``. 228 229- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 230 support within generic code in TF-A. This option is currently only supported 231 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 232 233- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 234 Measurement Framework(PMF). Default is 0. 235 236- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 237 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 238 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 239 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 240 software. 241 242- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 243 instrumentation which injects timestamp collection points into TF-A to 244 allow runtime performance to be measured. Currently, only PSCI is 245 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 246 as well. Default is 0. 247 248- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 249 extensions. This is an optional architectural feature for AArch64. 250 The default is 1 but is automatically disabled when the target architecture 251 is AArch32. 252 253- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 254 (SVE) for the Non-secure world only. SVE is an optional architectural feature 255 for AArch64. Note that when SVE is enabled for the Non-secure world, access 256 to SIMD and floating-point functionality from the Secure world is disabled. 257 This is to avoid corruption of the Non-secure world data in the Z-registers 258 which are aliased by the SIMD and FP registers. The build option is not 259 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 260 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 261 1. The default is 1 but is automatically disabled when the target 262 architecture is AArch32. 263 264- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 265 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 266 default value is set to "none". "strong" is the recommended stack protection 267 level if this feature is desired. "none" disables the stack protection. For 268 all values other than "none", the ``plat_get_stack_protector_canary()`` 269 platform hook needs to be implemented. The value is passed as the last 270 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 271 272- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 273 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 274 experimental. 275 276- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 277 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 278 experimental. 279 280- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 281 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 282 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 283 284- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 285 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 286 build flag which is marked as experimental. 287 288- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 289 deprecated platform APIs, helper functions or drivers within Trusted 290 Firmware as error. It can take the value 1 (flag the use of deprecated 291 APIs as error) or 0. The default is 0. 292 293- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 294 targeted at EL3. When set ``0`` (default), no exceptions are expected or 295 handled at EL3, and a panic will result. This is supported only for AArch64 296 builds. 297 298- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 299 injection from lower ELs, and this build option enables lower ELs to use 300 Error Records accessed via System Registers to inject faults. This is 301 applicable only to AArch64 builds. 302 303 This feature is intended for testing purposes only, and is advisable to keep 304 disabled for production images. 305 306- ``FIP_NAME``: This is an optional build option which specifies the FIP 307 filename for the ``fip`` target. Default is ``fip.bin``. 308 309- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 310 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 311 312- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 313 314 :: 315 316 0: Encryption is done with Secret Symmetric Key (SSK) which is common 317 for a class of devices. 318 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 319 unique per device. 320 321 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 322 experimental. 323 324- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 325 tool to create certificates as per the Chain of Trust described in 326 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 327 include the certificates in the FIP and FWU_FIP. Default value is '0'. 328 329 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 330 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 331 the corresponding certificates, and to include those certificates in the 332 FIP and FWU_FIP. 333 334 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 335 images will not include support for Trusted Board Boot. The FIP will still 336 include the corresponding certificates. This FIP can be used to verify the 337 Chain of Trust on the host machine through other mechanisms. 338 339 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 340 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 341 will not include the corresponding certificates, causing a boot failure. 342 343- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 344 inherent support for specific EL3 type interrupts. Setting this build option 345 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 346 by `platform abstraction layer`__ and `Interrupt Management Framework`__. 347 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 348 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 349 the Secure Payload interrupts needs to be synchronously handed over to Secure 350 EL1 for handling. The default value of this option is ``0``, which means the 351 Group 0 interrupts are assumed to be handled by Secure EL1. 352 353 .. __: platform-interrupt-controller-API.rst 354 .. __: interrupt-framework-design.rst 355 356- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 357 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 358 ``0`` (default), these exceptions will be trapped in the current exception 359 level (or in EL1 if the current exception level is EL0). 360 361- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 362 software operations are required for CPUs to enter and exit coherency. 363 However, newer systems exist where CPUs' entry to and exit from coherency 364 is managed in hardware. Such systems require software to only initiate these 365 operations, and the rest is managed in hardware, minimizing active software 366 management. In such systems, this boolean option enables TF-A to carry out 367 build and run-time optimizations during boot and power management operations. 368 This option defaults to 0 and if it is enabled, then it implies 369 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 370 371 If this flag is disabled while the platform which TF-A is compiled for 372 includes cores that manage coherency in hardware, then a compilation error is 373 generated. This is based on the fact that a system cannot have, at the same 374 time, cores that manage coherency in hardware and cores that don't. In other 375 words, a platform cannot have, at the same time, cores that require 376 ``HW_ASSISTED_COHERENCY=1`` and cores that require 377 ``HW_ASSISTED_COHERENCY=0``. 378 379 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 380 translation library (xlat tables v2) must be used; version 1 of translation 381 library is not supported. 382 383- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 384 bottom, higher addresses at the top. This buid flag can be set to '1' to 385 invert this behavior. Lower addresses will be printed at the top and higher 386 addresses at the bottom. 387 388- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 389 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 390 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 391 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 392 images. 393 394- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 395 used for generating the PKCS keys and subsequent signing of the certificate. 396 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 397 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 398 compliant and is retained only for compatibility. The default value of this 399 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 400 401- ``KEY_SIZE``: This build flag enables the user to select the key size for 402 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 403 depend on the chosen algorithm and the cryptographic module. 404 405 +-----------+------------------------------------+ 406 | KEY_ALG | Possible key sizes | 407 +===========+====================================+ 408 | rsa | 1024 , 2048 (default), 3072, 4096* | 409 +-----------+------------------------------------+ 410 | ecdsa | unavailable | 411 +-----------+------------------------------------+ 412 413 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 414 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 415 416- ``HASH_ALG``: This build flag enables the user to select the secure hash 417 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 418 The default value of this flag is ``sha256``. 419 420- ``LDFLAGS``: Extra user options appended to the linkers' command line in 421 addition to the one set by the build system. 422 423- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 424 output compiled into the build. This should be one of the following: 425 426 :: 427 428 0 (LOG_LEVEL_NONE) 429 10 (LOG_LEVEL_ERROR) 430 20 (LOG_LEVEL_NOTICE) 431 30 (LOG_LEVEL_WARNING) 432 40 (LOG_LEVEL_INFO) 433 50 (LOG_LEVEL_VERBOSE) 434 435 All log output up to and including the selected log level is compiled into 436 the build. The default value is 40 in debug builds and 20 in release builds. 437 438- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 439 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. 440 This option defaults to 0 and is an experimental feature in the stage of 441 development. 442 443- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 444 specifies the file that contains the Non-Trusted World private key in PEM 445 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 446 447- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 448 optional. It is only needed if the platform makefile specifies that it 449 is required in order to build the ``fwu_fip`` target. 450 451- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 452 contents upon world switch. It can take either 0 (don't save and restore) or 453 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 454 wants the timer registers to be saved and restored. 455 456- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 457 for the BL image. It can be either 0 (include) or 1 (remove). The default 458 value is 0. 459 460- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 461 the underlying hardware is not a full PL011 UART but a minimally compliant 462 generic UART, which is a subset of the PL011. The driver will not access 463 any register that is not part of the SBSA generic UART specification. 464 Default value is 0 (a full PL011 compliant UART is present). 465 466- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 467 must be subdirectory of any depth under ``plat/``, and must contain a 468 platform makefile named ``platform.mk``. For example, to build TF-A for the 469 Arm Juno board, select PLAT=juno. 470 471- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 472 instead of the normal boot flow. When defined, it must specify the entry 473 point address for the preloaded BL33 image. This option is incompatible with 474 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 475 over ``PRELOADED_BL33_BASE``. 476 477- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 478 vector address can be programmed or is fixed on the platform. It can take 479 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 480 programmable reset address, it is expected that a CPU will start executing 481 code directly at the right address, both on a cold and warm reset. In this 482 case, there is no need to identify the entrypoint on boot and the boot path 483 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 484 does not need to be implemented in this case. 485 486- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 487 possible for the PSCI power-state parameter: original and extended State-ID 488 formats. This flag if set to 1, configures the generic PSCI layer to use the 489 extended format. The default value of this flag is 0, which means by default 490 the original power-state format is used by the PSCI implementation. This flag 491 should be specified by the platform makefile and it governs the return value 492 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 493 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 494 set to 1 as well. 495 496- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 497 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 498 or later CPUs. 499 500 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 501 set to ``1``. 502 503 This option is disabled by default. 504 505- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 506 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 507 entrypoint) or 1 (CPU reset to BL31 entrypoint). 508 The default value is 0. 509 510- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 511 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 512 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 513 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 514 515- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 516 file that contains the ROT private key in PEM format and enforces public key 517 hash generation. If ``SAVE_KEYS=1``, this 518 file name will be used to save the key. 519 520- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 521 certificate generation tool to save the keys used to establish the Chain of 522 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 523 524- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 525 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 526 target. 527 528- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 529 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 530 this file name will be used to save the key. 531 532- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 533 optional. It is only needed if the platform makefile specifies that it 534 is required in order to build the ``fwu_fip`` target. 535 536- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 537 Delegated Exception Interface to BL31 image. This defaults to ``0``. 538 539 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 540 set to ``1``. 541 542- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 543 isolated on separate memory pages. This is a trade-off between security and 544 memory usage. See "Isolating code and read-only data on separate memory 545 pages" section in :ref:`Firmware Design`. This flag is disabled by default 546 and affects all BL images. 547 548- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 549 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 550 allocated in RAM discontiguous from the loaded firmware image. When set, the 551 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and 552 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 553 sections are placed in RAM immediately following the loaded firmware image. 554 555- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 556 This build option is only valid if ``ARCH=aarch64``. The value should be 557 the path to the directory containing the SPD source, relative to 558 ``services/spd/``; the directory is expected to contain a makefile called 559 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 560 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 561 cannot be enabled when the ``SPM_MM`` option is enabled. 562 563- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 564 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 565 execution in BL1 just before handing over to BL31. At this point, all 566 firmware images have been loaded in memory, and the MMU and caches are 567 turned off. Refer to the "Debugging options" section for more details. 568 569- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 570 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 571 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 572 extension. This is the default when enabling the SPM Dispatcher. When 573 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 574 state. This latter configuration supports pre-Armv8.4 platforms (aka not 575 implementing the Armv8.4-SecEL2 extension). 576 577- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 578 Partition Manager (SPM) implementation. The default value is ``0`` 579 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 580 enabled (``SPD=spmd``). 581 582- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 583 description of secure partitions. The build system will parse this file and 584 package all secure partition blobs into the FIP. This file is not 585 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 586 587- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 588 secure interrupts (caught through the FIQ line). Platforms can enable 589 this directive if they need to handle such interruption. When enabled, 590 the FIQ are handled in monitor mode and non secure world is not allowed 591 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 592 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 593 594- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 595 Boot feature. When set to '1', BL1 and BL2 images include support to load 596 and verify the certificates and images in a FIP, and BL1 includes support 597 for the Firmware Update. The default value is '0'. Generation and inclusion 598 of certificates in the FIP and FWU_FIP depends upon the value of the 599 ``GENERATE_COT`` option. 600 601 .. warning:: 602 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 603 already exist in disk, they will be overwritten without further notice. 604 605- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 606 specifies the file that contains the Trusted World private key in PEM 607 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 608 609- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 610 synchronous, (see "Initializing a BL32 Image" section in 611 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 612 synchronous method) or 1 (BL32 is initialized using asynchronous method). 613 Default is 0. 614 615- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 616 routing model which routes non-secure interrupts asynchronously from TSP 617 to EL3 causing immediate preemption of TSP. The EL3 is responsible 618 for saving and restoring the TSP context in this routing model. The 619 default routing model (when the value is 0) is to route non-secure 620 interrupts to TSP allowing it to save its context and hand over 621 synchronously to EL3 via an SMC. 622 623 .. note:: 624 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 625 must also be set to ``1``. 626 627- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 628 linker. When the ``LINKER`` build variable points to the armlink linker, 629 this flag is enabled automatically. To enable support for armlink, platforms 630 will have to provide a scatter file for the BL image. Currently, Tegra 631 platforms use the armlink support to compile BL3-1 images. 632 633- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 634 memory region in the BL memory map or not (see "Use of Coherent memory in 635 TF-A" section in :ref:`Firmware Design`). It can take the value 1 636 (Coherent memory region is included) or 0 (Coherent memory region is 637 excluded). Default is 1. 638 639- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 640 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 641 Default is 0. 642 643- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 644 firmware configuration framework. This will move the io_policies into a 645 configuration device tree, instead of static structure in the code base. 646 647 648- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 649 This feature creates a library of functions to be placed in ROM and thus 650 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 651 is 0. 652 653- ``V``: Verbose build. If assigned anything other than 0, the build commands 654 are printed. Default is 0. 655 656- ``VERSION_STRING``: String used in the log output for each TF-A image. 657 Defaults to a string formed by concatenating the version number, build type 658 and build string. 659 660- ``W``: Warning level. Some compiler warning options of interest have been 661 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 662 each level enabling more warning options. Default is 0. 663 664- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 665 the CPU after warm boot. This is applicable for platforms which do not 666 require interconnect programming to enable cache coherency (eg: single 667 cluster platforms). If this option is enabled, then warm boot path 668 enables D-caches immediately after enabling MMU. This option defaults to 0. 669 670- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 671 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 672 default value of this flag is ``no``. Note this option must be enabled only 673 for ARM architecture greater than Armv8.5-A. 674 675GICv3 driver options 676-------------------- 677 678GICv3 driver files are included using directive: 679 680``include drivers/arm/gic/v3/gicv3.mk`` 681 682The driver can be configured with the following options set in the platform 683makefile: 684 685- ``GICV3_IMPL``: Selects between GIC-500 and GIC-600 variants of GICv3. 686 This option can take values GIC500 and GIC600 with default set to GIC500. 687 688- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 689 functionality. This option defaults to 0 690 691- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 692 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 693 functions. This is required for FVP platform which need to simulate GIC save 694 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 695 696Debugging options 697----------------- 698 699To compile a debug version and make the build more verbose use 700 701.. code:: shell 702 703 make PLAT=<platform> DEBUG=1 V=1 all 704 705AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 706example DS-5) might not support this and may need an older version of DWARF 707symbols to be emitted by GCC. This can be achieved by using the 708``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 709version to 2 is recommended for DS-5 versions older than 5.16. 710 711When debugging logic problems it might also be useful to disable all compiler 712optimizations by using ``-O0``. 713 714.. warning:: 715 Using ``-O0`` could cause output images to be larger and base addresses 716 might need to be recalculated (see the **Memory layout on Arm development 717 platforms** section in the :ref:`Firmware Design`). 718 719Extra debug options can be passed to the build system by setting ``CFLAGS`` or 720``LDFLAGS``: 721 722.. code:: shell 723 724 CFLAGS='-O0 -gdwarf-2' \ 725 make PLAT=<platform> DEBUG=1 V=1 all 726 727Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 728ignored as the linker is called directly. 729 730It is also possible to introduce an infinite loop to help in debugging the 731post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 732``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 733section. In this case, the developer may take control of the target using a 734debugger when indicated by the console output. When using DS-5, the following 735commands can be used: 736 737:: 738 739 # Stop target execution 740 interrupt 741 742 # 743 # Prepare your debugging environment, e.g. set breakpoints 744 # 745 746 # Jump over the debug loop 747 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 748 749 # Resume execution 750 continue 751 752-------------- 753 754*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 755