1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/gicv3.h> 8 #include <drivers/arm/gic_common.h> 9 10 #include <plat/common/platform.h> 11 #include <platform_def.h> 12 13 static const interrupt_prop_t fpga_interrupt_props[] = { 14 PLATFORM_G1S_PROPS(INTR_GROUP1S), 15 PLATFORM_G0_PROPS(INTR_GROUP0) 16 }; 17 18 static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 19 20 static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr) 21 { 22 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 23 } 24 25 static const gicv3_driver_data_t fpga_gicv3_driver_data = { 26 .gicd_base = GICD_BASE, 27 .gicr_base = GICR_BASE, 28 .interrupt_props = fpga_interrupt_props, 29 .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props), 30 .rdistif_num = PLATFORM_CORE_COUNT, 31 .rdistif_base_addrs = fpga_rdistif_base_addrs, 32 .mpidr_to_core_pos = fpga_mpidr_to_core_pos 33 }; 34 35 void plat_fpga_gic_init(void) 36 { 37 gicv3_driver_init(&fpga_gicv3_driver_data); 38 gicv3_distif_init(); 39 gicv3_rdistif_init(plat_my_core_pos()); 40 gicv3_cpuif_enable(plat_my_core_pos()); 41 } 42 43 void fpga_pwr_gic_on_finish(void) 44 { 45 gicv3_rdistif_init(plat_my_core_pos()); 46 gicv3_cpuif_enable(plat_my_core_pos()); 47 } 48 49 void fpga_pwr_gic_off(void) 50 { 51 gicv3_cpuif_disable(plat_my_core_pos()); 52 gicv3_rdistif_off(plat_my_core_pos()); 53 } 54