1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/auth/auth_mod.h> 18 #include <drivers/console.h> 19 #include <lib/cpus/errata_report.h> 20 #include <lib/utils.h> 21 #include <plat/common/platform.h> 22 #include <smccc_helpers.h> 23 #include <tools_share/uuid.h> 24 25 #include "bl1_private.h" 26 27 /* BL1 Service UUID */ 28 DEFINE_SVC_UUID2(bl1_svc_uid, 29 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, 30 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 31 32 static void bl1_load_bl2(void); 33 34 #if ENABLE_PAUTH 35 uint64_t bl1_apiakey[2]; 36 #endif 37 38 /******************************************************************************* 39 * Helper utility to calculate the BL2 memory layout taking into consideration 40 * the BL1 RW data assuming that it is at the top of the memory layout. 41 ******************************************************************************/ 42 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 43 meminfo_t *bl2_mem_layout) 44 { 45 assert(bl1_mem_layout != NULL); 46 assert(bl2_mem_layout != NULL); 47 48 /* 49 * Remove BL1 RW data from the scope of memory visible to BL2. 50 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 51 */ 52 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 53 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 54 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 55 56 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); 57 } 58 59 /******************************************************************************* 60 * Setup function for BL1. 61 ******************************************************************************/ 62 void bl1_setup(void) 63 { 64 /* Perform early platform-specific setup */ 65 bl1_early_platform_setup(); 66 67 /* Perform late platform-specific setup */ 68 bl1_plat_arch_setup(); 69 70 #if CTX_INCLUDE_PAUTH_REGS 71 /* 72 * Assert that the ARMv8.3-PAuth registers are present or an access 73 * fault will be triggered when they are being saved or restored. 74 */ 75 assert(is_armv8_3_pauth_present()); 76 #endif /* CTX_INCLUDE_PAUTH_REGS */ 77 } 78 79 /******************************************************************************* 80 * Function to perform late architectural and platform specific initialization. 81 * It also queries the platform to load and run next BL image. Only called 82 * by the primary cpu after a cold boot. 83 ******************************************************************************/ 84 void bl1_main(void) 85 { 86 unsigned int image_id; 87 88 /* Announce our arrival */ 89 NOTICE(FIRMWARE_WELCOME_STR); 90 NOTICE("BL1: %s\n", version_string); 91 NOTICE("BL1: %s\n", build_message); 92 93 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); 94 95 print_errata_status(); 96 97 #if ENABLE_ASSERTIONS 98 u_register_t val; 99 /* 100 * Ensure that MMU/Caches and coherency are turned on 101 */ 102 #ifdef __aarch64__ 103 val = read_sctlr_el3(); 104 #else 105 val = read_sctlr(); 106 #endif 107 assert((val & SCTLR_M_BIT) != 0); 108 assert((val & SCTLR_C_BIT) != 0); 109 assert((val & SCTLR_I_BIT) != 0); 110 /* 111 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 112 * provided platform value 113 */ 114 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 115 /* 116 * If CWG is zero, then no CWG information is available but we can 117 * at least check the platform value is less than the architectural 118 * maximum. 119 */ 120 if (val != 0) 121 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 122 else 123 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 124 #endif /* ENABLE_ASSERTIONS */ 125 126 /* Perform remaining generic architectural setup from EL3 */ 127 bl1_arch_setup(); 128 129 #if TRUSTED_BOARD_BOOT 130 /* Initialize authentication module */ 131 auth_mod_init(); 132 #endif /* TRUSTED_BOARD_BOOT */ 133 134 /* Perform platform setup in BL1. */ 135 bl1_platform_setup(); 136 137 #if ENABLE_PAUTH 138 /* Store APIAKey_EL1 key */ 139 bl1_apiakey[0] = read_apiakeylo_el1(); 140 bl1_apiakey[1] = read_apiakeyhi_el1(); 141 #endif /* ENABLE_PAUTH */ 142 143 /* Get the image id of next image to load and run. */ 144 image_id = bl1_plat_get_next_image_id(); 145 146 /* 147 * We currently interpret any image id other than 148 * BL2_IMAGE_ID as the start of firmware update. 149 */ 150 if (image_id == BL2_IMAGE_ID) 151 bl1_load_bl2(); 152 else 153 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 154 155 bl1_prepare_next_image(image_id); 156 157 console_flush(); 158 } 159 160 /******************************************************************************* 161 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 162 * Called by the primary cpu after a cold boot. 163 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 164 * loader etc. 165 ******************************************************************************/ 166 static void bl1_load_bl2(void) 167 { 168 image_desc_t *desc; 169 image_info_t *info; 170 int err; 171 172 /* Get the image descriptor */ 173 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 174 assert(desc != NULL); 175 176 /* Get the image info */ 177 info = &desc->image_info; 178 INFO("BL1: Loading BL2\n"); 179 180 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 181 if (err != 0) { 182 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 183 plat_error_handler(err); 184 } 185 186 err = load_auth_image(BL2_IMAGE_ID, info); 187 if (err != 0) { 188 ERROR("Failed to load BL2 firmware.\n"); 189 plat_error_handler(err); 190 } 191 192 /* Allow platform to handle image information. */ 193 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 194 if (err != 0) { 195 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 196 plat_error_handler(err); 197 } 198 199 NOTICE("BL1: Booting BL2\n"); 200 } 201 202 /******************************************************************************* 203 * Function called just before handing over to the next BL to inform the user 204 * about the boot progress. In debug mode, also print details about the BL 205 * image's execution context. 206 ******************************************************************************/ 207 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 208 { 209 #ifdef __aarch64__ 210 NOTICE("BL1: Booting BL31\n"); 211 #else 212 NOTICE("BL1: Booting BL32\n"); 213 #endif /* __aarch64__ */ 214 print_entry_point_info(bl_ep_info); 215 } 216 217 #if SPIN_ON_BL1_EXIT 218 void print_debug_loop_message(void) 219 { 220 NOTICE("BL1: Debug loop, spinning forever\n"); 221 NOTICE("BL1: Please connect the debugger to continue\n"); 222 } 223 #endif 224 225 /******************************************************************************* 226 * Top level handler for servicing BL1 SMCs. 227 ******************************************************************************/ 228 u_register_t bl1_smc_handler(unsigned int smc_fid, 229 u_register_t x1, 230 u_register_t x2, 231 u_register_t x3, 232 u_register_t x4, 233 void *cookie, 234 void *handle, 235 unsigned int flags) 236 { 237 238 #if TRUSTED_BOARD_BOOT 239 /* 240 * Dispatch FWU calls to FWU SMC handler and return its return 241 * value 242 */ 243 if (is_fwu_fid(smc_fid)) { 244 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 245 handle, flags); 246 } 247 #endif 248 249 switch (smc_fid) { 250 case BL1_SMC_CALL_COUNT: 251 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 252 253 case BL1_SMC_UID: 254 SMC_UUID_RET(handle, bl1_svc_uid); 255 256 case BL1_SMC_VERSION: 257 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 258 259 default: 260 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid); 261 SMC_RET1(handle, SMC_UNK); 262 } 263 } 264 265 /******************************************************************************* 266 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 267 * compliance when invoking bl1_smc_handler. 268 ******************************************************************************/ 269 u_register_t bl1_smc_wrapper(uint32_t smc_fid, 270 void *cookie, 271 void *handle, 272 unsigned int flags) 273 { 274 u_register_t x1, x2, x3, x4; 275 276 assert(handle != NULL); 277 278 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 279 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 280 } 281