1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 if (security_state == NON_SECURE) 136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 137 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 138 139 /* 140 * Enable MTE support. Support is enabled unilaterally for the normal 141 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 142 * set. 143 */ 144 #if CTX_INCLUDE_MTE_REGS 145 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 146 scr_el3 |= SCR_ATA_BIT; 147 #else 148 unsigned int mte = get_armv8_5_mte_support(); 149 if (mte == MTE_IMPLEMENTED_EL0) { 150 /* 151 * Can enable MTE across both worlds as no MTE registers are 152 * used 153 */ 154 scr_el3 |= SCR_ATA_BIT; 155 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 156 /* 157 * Can only enable MTE in Non-Secure world without register 158 * saving 159 */ 160 scr_el3 |= SCR_ATA_BIT; 161 } 162 #endif 163 164 #ifdef IMAGE_BL31 165 /* 166 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 167 * indicated by the interrupt routing model for BL31. 168 */ 169 scr_el3 |= get_scr_el3_from_routing_model(security_state); 170 #endif 171 172 /* 173 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 174 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 175 * next mode is Hyp. 176 */ 177 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 178 || ((GET_RW(ep->spsr) != MODE_RW_64) 179 && (GET_M32(ep->spsr) == MODE32_hyp))) { 180 scr_el3 |= SCR_HCE_BIT; 181 } 182 183 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 184 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 185 if (GET_RW(ep->spsr) != MODE_RW_64) { 186 ERROR("S-EL2 can not be used in AArch32."); 187 panic(); 188 } 189 190 scr_el3 |= SCR_EEL2_BIT; 191 } 192 193 /* 194 * Initialise SCTLR_EL1 to the reset value corresponding to the target 195 * execution state setting all fields rather than relying of the hw. 196 * Some fields have architecturally UNKNOWN reset values and these are 197 * set to zero. 198 * 199 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 200 * 201 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 202 * required by PSCI specification) 203 */ 204 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 205 if (GET_RW(ep->spsr) == MODE_RW_64) 206 sctlr_elx |= SCTLR_EL1_RES1; 207 else { 208 /* 209 * If the target execution state is AArch32 then the following 210 * fields need to be set. 211 * 212 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 213 * instructions are not trapped to EL1. 214 * 215 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 216 * instructions are not trapped to EL1. 217 * 218 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 219 * CP15DMB, CP15DSB, and CP15ISB instructions. 220 */ 221 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 222 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 223 } 224 225 #if ERRATA_A75_764081 226 /* 227 * If workaround of errata 764081 for Cortex-A75 is used then set 228 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 229 */ 230 sctlr_elx |= SCTLR_IESB_BIT; 231 #endif 232 233 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 234 if (is_armv8_6_twed_present()) { 235 uint32_t delay = plat_arm_set_twedel_scr_el3(); 236 237 if (delay != TWED_DISABLED) { 238 /* Make sure delay value fits */ 239 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 240 241 /* Set delay in SCR_EL3 */ 242 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 243 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 244 << SCR_TWEDEL_SHIFT); 245 246 /* Enable WFE delay */ 247 scr_el3 |= SCR_TWEDEn_BIT; 248 } 249 } 250 251 /* 252 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 253 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 254 * are not part of the stored cpu_context. 255 */ 256 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 257 258 /* 259 * Base the context ACTLR_EL1 on the current value, as it is 260 * implementation defined. The context restore process will write 261 * the value from the context to the actual register and can cause 262 * problems for processor cores that don't expect certain bits to 263 * be zero. 264 */ 265 actlr_elx = read_actlr_el1(); 266 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 267 268 /* 269 * Populate EL3 state so that we've the right context 270 * before doing ERET 271 */ 272 state = get_el3state_ctx(ctx); 273 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 274 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 275 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 276 277 /* 278 * Store the X0-X7 value from the entrypoint into the context 279 * Use memcpy as we are in control of the layout of the structures 280 */ 281 gp_regs = get_gpregs_ctx(ctx); 282 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 283 } 284 285 /******************************************************************************* 286 * Enable architecture extensions on first entry to Non-secure world. 287 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 288 * it is zero. 289 ******************************************************************************/ 290 static void enable_extensions_nonsecure(bool el2_unused) 291 { 292 #if IMAGE_BL31 293 #if ENABLE_SPE_FOR_LOWER_ELS 294 spe_enable(el2_unused); 295 #endif 296 297 #if ENABLE_AMU 298 amu_enable(el2_unused); 299 #endif 300 301 #if ENABLE_SVE_FOR_NS 302 sve_enable(el2_unused); 303 #endif 304 305 #if ENABLE_MPAM_FOR_LOWER_ELS 306 mpam_enable(el2_unused); 307 #endif 308 #endif 309 } 310 311 /******************************************************************************* 312 * The following function initializes the cpu_context for a CPU specified by 313 * its `cpu_idx` for first use, and sets the initial entrypoint state as 314 * specified by the entry_point_info structure. 315 ******************************************************************************/ 316 void cm_init_context_by_index(unsigned int cpu_idx, 317 const entry_point_info_t *ep) 318 { 319 cpu_context_t *ctx; 320 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 321 cm_setup_context(ctx, ep); 322 } 323 324 /******************************************************************************* 325 * The following function initializes the cpu_context for the current CPU 326 * for first use, and sets the initial entrypoint state as specified by the 327 * entry_point_info structure. 328 ******************************************************************************/ 329 void cm_init_my_context(const entry_point_info_t *ep) 330 { 331 cpu_context_t *ctx; 332 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 333 cm_setup_context(ctx, ep); 334 } 335 336 /******************************************************************************* 337 * Prepare the CPU system registers for first entry into secure or normal world 338 * 339 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 340 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 341 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 342 * For all entries, the EL1 registers are initialized from the cpu_context 343 ******************************************************************************/ 344 void cm_prepare_el3_exit(uint32_t security_state) 345 { 346 u_register_t sctlr_elx, scr_el3, mdcr_el2; 347 cpu_context_t *ctx = cm_get_context(security_state); 348 bool el2_unused = false; 349 uint64_t hcr_el2 = 0U; 350 351 assert(ctx != NULL); 352 353 if (security_state == NON_SECURE) { 354 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 355 CTX_SCR_EL3); 356 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 357 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 358 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 359 CTX_SCTLR_EL1); 360 sctlr_elx &= SCTLR_EE_BIT; 361 sctlr_elx |= SCTLR_EL2_RES1; 362 #if ERRATA_A75_764081 363 /* 364 * If workaround of errata 764081 for Cortex-A75 is used 365 * then set SCTLR_EL2.IESB to enable Implicit Error 366 * Synchronization Barrier. 367 */ 368 sctlr_elx |= SCTLR_IESB_BIT; 369 #endif 370 write_sctlr_el2(sctlr_elx); 371 } else if (el_implemented(2) != EL_IMPL_NONE) { 372 el2_unused = true; 373 374 /* 375 * EL2 present but unused, need to disable safely. 376 * SCTLR_EL2 can be ignored in this case. 377 * 378 * Set EL2 register width appropriately: Set HCR_EL2 379 * field to match SCR_EL3.RW. 380 */ 381 if ((scr_el3 & SCR_RW_BIT) != 0U) 382 hcr_el2 |= HCR_RW_BIT; 383 384 /* 385 * For Armv8.3 pointer authentication feature, disable 386 * traps to EL2 when accessing key registers or using 387 * pointer authentication instructions from lower ELs. 388 */ 389 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 390 391 write_hcr_el2(hcr_el2); 392 393 /* 394 * Initialise CPTR_EL2 setting all fields rather than 395 * relying on the hw. All fields have architecturally 396 * UNKNOWN reset values. 397 * 398 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 399 * accesses to the CPACR_EL1 or CPACR from both 400 * Execution states do not trap to EL2. 401 * 402 * CPTR_EL2.TTA: Set to zero so that Non-secure System 403 * register accesses to the trace registers from both 404 * Execution states do not trap to EL2. 405 * 406 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 407 * to SIMD and floating-point functionality from both 408 * Execution states do not trap to EL2. 409 */ 410 write_cptr_el2(CPTR_EL2_RESET_VAL & 411 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 412 | CPTR_EL2_TFP_BIT)); 413 414 /* 415 * Initialise CNTHCTL_EL2. All fields are 416 * architecturally UNKNOWN on reset and are set to zero 417 * except for field(s) listed below. 418 * 419 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 420 * Hyp mode of Non-secure EL0 and EL1 accesses to the 421 * physical timer registers. 422 * 423 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 424 * Hyp mode of Non-secure EL0 and EL1 accesses to the 425 * physical counter registers. 426 */ 427 write_cnthctl_el2(CNTHCTL_RESET_VAL | 428 EL1PCEN_BIT | EL1PCTEN_BIT); 429 430 /* 431 * Initialise CNTVOFF_EL2 to zero as it resets to an 432 * architecturally UNKNOWN value. 433 */ 434 write_cntvoff_el2(0); 435 436 /* 437 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 438 * MPIDR_EL1 respectively. 439 */ 440 write_vpidr_el2(read_midr_el1()); 441 write_vmpidr_el2(read_mpidr_el1()); 442 443 /* 444 * Initialise VTTBR_EL2. All fields are architecturally 445 * UNKNOWN on reset. 446 * 447 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 448 * 2 address translation is disabled, cache maintenance 449 * operations depend on the VMID. 450 * 451 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 452 * translation is disabled. 453 */ 454 write_vttbr_el2(VTTBR_RESET_VAL & 455 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 456 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 457 458 /* 459 * Initialise MDCR_EL2, setting all fields rather than 460 * relying on hw. Some fields are architecturally 461 * UNKNOWN on reset. 462 * 463 * MDCR_EL2.HLP: Set to one so that event counter 464 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 465 * occurs on the increment that changes 466 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 467 * implemented. This bit is RES0 in versions of the 468 * architecture earlier than ARMv8.5, setting it to 1 469 * doesn't have any effect on them. 470 * 471 * MDCR_EL2.TTRF: Set to zero so that access to Trace 472 * Filter Control register TRFCR_EL1 at EL1 is not 473 * trapped to EL2. This bit is RES0 in versions of 474 * the architecture earlier than ARMv8.4. 475 * 476 * MDCR_EL2.HPMD: Set to one so that event counting is 477 * prohibited at EL2. This bit is RES0 in versions of 478 * the architecture earlier than ARMv8.1, setting it 479 * to 1 doesn't have any effect on them. 480 * 481 * MDCR_EL2.TPMS: Set to zero so that accesses to 482 * Statistical Profiling control registers from EL1 483 * do not trap to EL2. This bit is RES0 when SPE is 484 * not implemented. 485 * 486 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 487 * EL1 System register accesses to the Debug ROM 488 * registers are not trapped to EL2. 489 * 490 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 491 * System register accesses to the powerdown debug 492 * registers are not trapped to EL2. 493 * 494 * MDCR_EL2.TDA: Set to zero so that System register 495 * accesses to the debug registers do not trap to EL2. 496 * 497 * MDCR_EL2.TDE: Set to zero so that debug exceptions 498 * are not routed to EL2. 499 * 500 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 501 * Monitors. 502 * 503 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 504 * EL1 accesses to all Performance Monitors registers 505 * are not trapped to EL2. 506 * 507 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 508 * and EL1 accesses to the PMCR_EL0 or PMCR are not 509 * trapped to EL2. 510 * 511 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 512 * architecturally-defined reset value. 513 */ 514 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 515 MDCR_EL2_HPMD) | 516 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 517 >> PMCR_EL0_N_SHIFT)) & 518 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 519 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 520 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 521 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 522 MDCR_EL2_TPMCR_BIT); 523 524 write_mdcr_el2(mdcr_el2); 525 526 /* 527 * Initialise HSTR_EL2. All fields are architecturally 528 * UNKNOWN on reset. 529 * 530 * HSTR_EL2.T<n>: Set all these fields to zero so that 531 * Non-secure EL0 or EL1 accesses to System registers 532 * do not trap to EL2. 533 */ 534 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 535 /* 536 * Initialise CNTHP_CTL_EL2. All fields are 537 * architecturally UNKNOWN on reset. 538 * 539 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 540 * physical timer and prevent timer interrupts. 541 */ 542 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 543 ~(CNTHP_CTL_ENABLE_BIT)); 544 } 545 enable_extensions_nonsecure(el2_unused); 546 } 547 548 cm_el1_sysregs_context_restore(security_state); 549 cm_set_next_eret_context(security_state); 550 } 551 552 #if CTX_INCLUDE_EL2_REGS 553 /******************************************************************************* 554 * Save EL2 sysreg context 555 ******************************************************************************/ 556 void cm_el2_sysregs_context_save(uint32_t security_state) 557 { 558 u_register_t scr_el3 = read_scr(); 559 560 /* 561 * Always save the non-secure EL2 context, only save the 562 * S-EL2 context if S-EL2 is enabled. 563 */ 564 if ((security_state == NON_SECURE) || 565 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 566 cpu_context_t *ctx; 567 568 ctx = cm_get_context(security_state); 569 assert(ctx != NULL); 570 571 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 572 } 573 } 574 575 /******************************************************************************* 576 * Restore EL2 sysreg context 577 ******************************************************************************/ 578 void cm_el2_sysregs_context_restore(uint32_t security_state) 579 { 580 u_register_t scr_el3 = read_scr(); 581 582 /* 583 * Always restore the non-secure EL2 context, only restore the 584 * S-EL2 context if S-EL2 is enabled. 585 */ 586 if ((security_state == NON_SECURE) || 587 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 588 cpu_context_t *ctx; 589 590 ctx = cm_get_context(security_state); 591 assert(ctx != NULL); 592 593 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 594 } 595 } 596 #endif /* CTX_INCLUDE_EL2_REGS */ 597 598 /******************************************************************************* 599 * The next four functions are used by runtime services to save and restore 600 * EL1 context on the 'cpu_context' structure for the specified security 601 * state. 602 ******************************************************************************/ 603 void cm_el1_sysregs_context_save(uint32_t security_state) 604 { 605 cpu_context_t *ctx; 606 607 ctx = cm_get_context(security_state); 608 assert(ctx != NULL); 609 610 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 611 612 #if IMAGE_BL31 613 if (security_state == SECURE) 614 PUBLISH_EVENT(cm_exited_secure_world); 615 else 616 PUBLISH_EVENT(cm_exited_normal_world); 617 #endif 618 } 619 620 void cm_el1_sysregs_context_restore(uint32_t security_state) 621 { 622 cpu_context_t *ctx; 623 624 ctx = cm_get_context(security_state); 625 assert(ctx != NULL); 626 627 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 628 629 #if IMAGE_BL31 630 if (security_state == SECURE) 631 PUBLISH_EVENT(cm_entering_secure_world); 632 else 633 PUBLISH_EVENT(cm_entering_normal_world); 634 #endif 635 } 636 637 /******************************************************************************* 638 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 639 * given security state with the given entrypoint 640 ******************************************************************************/ 641 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 642 { 643 cpu_context_t *ctx; 644 el3_state_t *state; 645 646 ctx = cm_get_context(security_state); 647 assert(ctx != NULL); 648 649 /* Populate EL3 state so that ERET jumps to the correct entry */ 650 state = get_el3state_ctx(ctx); 651 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 652 } 653 654 /******************************************************************************* 655 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 656 * pertaining to the given security state 657 ******************************************************************************/ 658 void cm_set_elr_spsr_el3(uint32_t security_state, 659 uintptr_t entrypoint, uint32_t spsr) 660 { 661 cpu_context_t *ctx; 662 el3_state_t *state; 663 664 ctx = cm_get_context(security_state); 665 assert(ctx != NULL); 666 667 /* Populate EL3 state so that ERET jumps to the correct entry */ 668 state = get_el3state_ctx(ctx); 669 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 670 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 671 } 672 673 /******************************************************************************* 674 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 675 * pertaining to the given security state using the value and bit position 676 * specified in the parameters. It preserves all other bits. 677 ******************************************************************************/ 678 void cm_write_scr_el3_bit(uint32_t security_state, 679 uint32_t bit_pos, 680 uint32_t value) 681 { 682 cpu_context_t *ctx; 683 el3_state_t *state; 684 u_register_t scr_el3; 685 686 ctx = cm_get_context(security_state); 687 assert(ctx != NULL); 688 689 /* Ensure that the bit position is a valid one */ 690 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 691 692 /* Ensure that the 'value' is only a bit wide */ 693 assert(value <= 1U); 694 695 /* 696 * Get the SCR_EL3 value from the cpu context, clear the desired bit 697 * and set it to its new value. 698 */ 699 state = get_el3state_ctx(ctx); 700 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 701 scr_el3 &= ~(1U << bit_pos); 702 scr_el3 |= (u_register_t)value << bit_pos; 703 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 704 } 705 706 /******************************************************************************* 707 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 708 * given security state. 709 ******************************************************************************/ 710 u_register_t cm_get_scr_el3(uint32_t security_state) 711 { 712 cpu_context_t *ctx; 713 el3_state_t *state; 714 715 ctx = cm_get_context(security_state); 716 assert(ctx != NULL); 717 718 /* Populate EL3 state so that ERET jumps to the correct entry */ 719 state = get_el3state_ctx(ctx); 720 return read_ctx_reg(state, CTX_SCR_EL3); 721 } 722 723 /******************************************************************************* 724 * This function is used to program the context that's used for exception 725 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 726 * the required security state 727 ******************************************************************************/ 728 void cm_set_next_eret_context(uint32_t security_state) 729 { 730 cpu_context_t *ctx; 731 732 ctx = cm_get_context(security_state); 733 assert(ctx != NULL); 734 735 cm_set_next_context(ctx); 736 } 737