1# 2# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7override BL2_AT_EL3 := 1 8override COLD_BOOT_SINGLE_CPU := 1 9override PROGRAMMABLE_RESET_ADDRESS := 1 10override USE_COHERENT_MEM := 1 11override ENABLE_SVE_FOR_NS := 0 12 13# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust 14# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses. 15override ENABLE_PIE := 1 16 17ALLOW_RO_XLAT_TABLES := 1 18 19ifeq ($(ALLOW_RO_XLAT_TABLES),1) 20BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 21BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 22endif 23 24# Cortex-A53 revision r0p4-51rel0 25# needed for LD20, unneeded for LD11, PXs3 (no ACE) 26ERRATA_A53_855873 := 1 27 28FIP_ALIGN := 512 29 30ifeq ($(NEED_BL32),yes) 31$(eval $(call add_define,UNIPHIER_LOAD_BL32)) 32endif 33 34# Libraries 35include lib/xlat_tables_v2/xlat_tables.mk 36 37PLAT_PATH := plat/socionext/uniphier 38PLAT_INCLUDES := -I$(PLAT_PATH)/include 39 40# common sources for BL2, BL31 (and BL32 if SPD=tspd) 41PLAT_BL_COMMON_SOURCES += plat/common/aarch64/crash_console_helpers.S \ 42 $(PLAT_PATH)/uniphier_console.S \ 43 $(PLAT_PATH)/uniphier_console_setup.c \ 44 $(PLAT_PATH)/uniphier_helpers.S \ 45 $(PLAT_PATH)/uniphier_soc_info.c \ 46 $(PLAT_PATH)/uniphier_xlat_setup.c \ 47 ${XLAT_TABLES_LIB_SRCS} 48 49BL2_SOURCES += common/desc_image_load.c \ 50 drivers/io/io_block.c \ 51 drivers/io/io_fip.c \ 52 drivers/io/io_memmap.c \ 53 drivers/io/io_storage.c \ 54 lib/cpus/aarch64/cortex_a53.S \ 55 lib/cpus/aarch64/cortex_a72.S \ 56 $(PLAT_PATH)/uniphier_bl2_setup.c \ 57 $(PLAT_PATH)/uniphier_boot_device.c \ 58 $(PLAT_PATH)/uniphier_emmc.c \ 59 $(PLAT_PATH)/uniphier_image_desc.c \ 60 $(PLAT_PATH)/uniphier_io_storage.c \ 61 $(PLAT_PATH)/uniphier_nand.c \ 62 $(PLAT_PATH)/uniphier_scp.c \ 63 $(PLAT_PATH)/uniphier_usb.c 64 65# Include GICv3 driver files 66include drivers/arm/gic/v3/gicv3.mk 67 68BL31_SOURCES += drivers/arm/cci/cci.c \ 69 ${GICV3_SOURCES} \ 70 lib/cpus/aarch64/cortex_a53.S \ 71 lib/cpus/aarch64/cortex_a72.S \ 72 plat/common/plat_gicv3.c \ 73 plat/common/plat_psci_common.c \ 74 $(PLAT_PATH)/uniphier_bl31_setup.c \ 75 $(PLAT_PATH)/uniphier_boot_device.c \ 76 $(PLAT_PATH)/uniphier_cci.c \ 77 $(PLAT_PATH)/uniphier_gicv3.c \ 78 $(PLAT_PATH)/uniphier_psci.c \ 79 $(PLAT_PATH)/uniphier_scp.c \ 80 $(PLAT_PATH)/uniphier_smp.S \ 81 $(PLAT_PATH)/uniphier_syscnt.c \ 82 $(PLAT_PATH)/uniphier_topology.c 83 84ifeq (${TRUSTED_BOARD_BOOT},1) 85 86include drivers/auth/mbedtls/mbedtls_crypto.mk 87include drivers/auth/mbedtls/mbedtls_x509.mk 88 89BL2_SOURCES += drivers/auth/auth_mod.c \ 90 drivers/auth/crypto_mod.c \ 91 drivers/auth/img_parser_mod.c \ 92 drivers/auth/tbbr/tbbr_cot.c \ 93 plat/common/tbbr/plat_tbbr.c \ 94 $(PLAT_PATH)/uniphier_rotpk.S \ 95 $(PLAT_PATH)/uniphier_tbbr.c 96 97ROT_KEY = $(BUILD_PLAT)/rot_key.pem 98ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin 99 100$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) 101$(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH) 102 103certificates: $(ROT_KEY) 104$(ROT_KEY): | $(BUILD_PLAT) 105 @echo " OPENSSL $@" 106 $(Q)openssl genrsa 2048 > $@ 2>/dev/null 107 108$(ROTPK_HASH): $(ROT_KEY) 109 @echo " OPENSSL $@" 110 $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ 111 openssl dgst -sha256 -binary > $@ 2>/dev/null 112 113endif 114 115ifeq (${FIP_GZIP},1) 116 117include lib/zlib/zlib.mk 118 119BL2_SOURCES += common/image_decompress.c \ 120 $(ZLIB_SOURCES) 121 122$(eval $(call add_define,UNIPHIER_DECOMPRESS_GZIP)) 123 124# compress all images loaded by BL2 125SCP_BL2_PRE_TOOL_FILTER := GZIP 126BL31_PRE_TOOL_FILTER := GZIP 127BL32_PRE_TOOL_FILTER := GZIP 128BL33_PRE_TOOL_FILTER := GZIP 129 130endif 131 132.PHONY: bl2_gzip 133bl2_gzip: $(BUILD_PLAT)/bl2.bin.gz 134%.gz: % 135 @echo " GZIP $@" 136 $(Q)gzip -n -f -9 $< --stdout > $@ 137