1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 165 #define ID_AA64PFR0_GIC_SHIFT U(24) 166 #define ID_AA64PFR0_GIC_WIDTH U(4) 167 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 168 #define ID_AA64PFR0_SVE_SHIFT U(32) 169 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 170 #define ID_AA64PFR0_SEL2_SHIFT U(36) 171 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 172 #define ID_AA64PFR0_MPAM_SHIFT U(40) 173 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 174 #define ID_AA64PFR0_DIT_SHIFT U(48) 175 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 176 #define ID_AA64PFR0_DIT_LENGTH U(4) 177 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 178 #define ID_AA64PFR0_CSV2_SHIFT U(56) 179 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 180 #define ID_AA64PFR0_CSV2_LENGTH U(4) 181 182 /* Exception level handling */ 183 #define EL_IMPL_NONE ULL(0) 184 #define EL_IMPL_A64ONLY ULL(1) 185 #define EL_IMPL_A64_A32 ULL(2) 186 187 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 188 #define ID_AA64DFR0_PMS_SHIFT U(32) 189 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 190 191 /* ID_AA64ISAR1_EL1 definitions */ 192 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 193 #define ID_AA64ISAR1_GPI_SHIFT U(28) 194 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 195 #define ID_AA64ISAR1_GPA_SHIFT U(24) 196 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 197 #define ID_AA64ISAR1_API_SHIFT U(8) 198 #define ID_AA64ISAR1_API_MASK ULL(0xf) 199 #define ID_AA64ISAR1_APA_SHIFT U(4) 200 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 201 202 /* ID_AA64MMFR0_EL1 definitions */ 203 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 204 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 205 206 #define PARANGE_0000 U(32) 207 #define PARANGE_0001 U(36) 208 #define PARANGE_0010 U(40) 209 #define PARANGE_0011 U(42) 210 #define PARANGE_0100 U(44) 211 #define PARANGE_0101 U(48) 212 #define PARANGE_0110 U(52) 213 214 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 215 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 216 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 217 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 218 219 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 220 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 221 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 222 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 223 224 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 225 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 226 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 227 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 228 229 /* ID_AA64MMFR1_EL1 definitions */ 230 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 231 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 232 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 233 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 234 235 /* ID_AA64MMFR2_EL1 definitions */ 236 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 237 238 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 239 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 240 241 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 242 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 243 244 /* ID_AA64PFR1_EL1 definitions */ 245 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 246 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 247 248 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 249 250 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 251 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 252 253 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 254 255 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 256 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 257 258 #define MTE_UNIMPLEMENTED ULL(0) 259 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ 260 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ 261 262 /* ID_PFR1_EL1 definitions */ 263 #define ID_PFR1_VIRTEXT_SHIFT U(12) 264 #define ID_PFR1_VIRTEXT_MASK U(0xf) 265 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 266 & ID_PFR1_VIRTEXT_MASK) 267 268 /* SCTLR definitions */ 269 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 270 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 271 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 272 273 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 274 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 275 #define SCTLR_AARCH32_EL1_RES1 \ 276 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 277 (U(1) << 4) | (U(1) << 3)) 278 279 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 280 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 281 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 282 283 #define SCTLR_M_BIT (ULL(1) << 0) 284 #define SCTLR_A_BIT (ULL(1) << 1) 285 #define SCTLR_C_BIT (ULL(1) << 2) 286 #define SCTLR_SA_BIT (ULL(1) << 3) 287 #define SCTLR_SA0_BIT (ULL(1) << 4) 288 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 289 #define SCTLR_ITD_BIT (ULL(1) << 7) 290 #define SCTLR_SED_BIT (ULL(1) << 8) 291 #define SCTLR_UMA_BIT (ULL(1) << 9) 292 #define SCTLR_I_BIT (ULL(1) << 12) 293 #define SCTLR_EnDB_BIT (ULL(1) << 13) 294 #define SCTLR_DZE_BIT (ULL(1) << 14) 295 #define SCTLR_UCT_BIT (ULL(1) << 15) 296 #define SCTLR_NTWI_BIT (ULL(1) << 16) 297 #define SCTLR_NTWE_BIT (ULL(1) << 18) 298 #define SCTLR_WXN_BIT (ULL(1) << 19) 299 #define SCTLR_UWXN_BIT (ULL(1) << 20) 300 #define SCTLR_IESB_BIT (ULL(1) << 21) 301 #define SCTLR_E0E_BIT (ULL(1) << 24) 302 #define SCTLR_EE_BIT (ULL(1) << 25) 303 #define SCTLR_UCI_BIT (ULL(1) << 26) 304 #define SCTLR_EnDA_BIT (ULL(1) << 27) 305 #define SCTLR_EnIB_BIT (ULL(1) << 30) 306 #define SCTLR_EnIA_BIT (ULL(1) << 31) 307 #define SCTLR_BT0_BIT (ULL(1) << 35) 308 #define SCTLR_BT1_BIT (ULL(1) << 36) 309 #define SCTLR_BT_BIT (ULL(1) << 36) 310 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 311 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 312 313 /* CPACR_El1 definitions */ 314 #define CPACR_EL1_FPEN(x) ((x) << 20) 315 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 316 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 317 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 318 319 /* SCR definitions */ 320 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 321 #define SCR_TWEDEL_SHIFT U(30) 322 #define SCR_TWEDEL_MASK ULL(0xf) 323 #define SCR_TWEDEn_BIT (UL(1) << 29) 324 #define SCR_ATA_BIT (U(1) << 26) 325 #define SCR_FIEN_BIT (U(1) << 21) 326 #define SCR_EEL2_BIT (U(1) << 18) 327 #define SCR_API_BIT (U(1) << 17) 328 #define SCR_APK_BIT (U(1) << 16) 329 #define SCR_TWE_BIT (U(1) << 13) 330 #define SCR_TWI_BIT (U(1) << 12) 331 #define SCR_ST_BIT (U(1) << 11) 332 #define SCR_RW_BIT (U(1) << 10) 333 #define SCR_SIF_BIT (U(1) << 9) 334 #define SCR_HCE_BIT (U(1) << 8) 335 #define SCR_SMD_BIT (U(1) << 7) 336 #define SCR_EA_BIT (U(1) << 3) 337 #define SCR_FIQ_BIT (U(1) << 2) 338 #define SCR_IRQ_BIT (U(1) << 1) 339 #define SCR_NS_BIT (U(1) << 0) 340 #define SCR_VALID_BIT_MASK U(0x2f8f) 341 #define SCR_RESET_VAL SCR_RES1_BITS 342 343 /* MDCR_EL3 definitions */ 344 #define MDCR_SCCD_BIT (ULL(1) << 23) 345 #define MDCR_SPME_BIT (ULL(1) << 17) 346 #define MDCR_SDD_BIT (ULL(1) << 16) 347 #define MDCR_SPD32(x) ((x) << 14) 348 #define MDCR_SPD32_LEGACY ULL(0x0) 349 #define MDCR_SPD32_DISABLE ULL(0x2) 350 #define MDCR_SPD32_ENABLE ULL(0x3) 351 #define MDCR_NSPB(x) ((x) << 12) 352 #define MDCR_NSPB_EL1 ULL(0x3) 353 #define MDCR_TDOSA_BIT (ULL(1) << 10) 354 #define MDCR_TDA_BIT (ULL(1) << 9) 355 #define MDCR_TPM_BIT (ULL(1) << 6) 356 #define MDCR_EL3_RESET_VAL ULL(0x0) 357 358 /* MDCR_EL2 definitions */ 359 #define MDCR_EL2_HLP (U(1) << 26) 360 #define MDCR_EL2_HCCD (U(1) << 23) 361 #define MDCR_EL2_TTRF (U(1) << 19) 362 #define MDCR_EL2_HPMD (U(1) << 17) 363 #define MDCR_EL2_TPMS (U(1) << 14) 364 #define MDCR_EL2_E2PB(x) ((x) << 12) 365 #define MDCR_EL2_E2PB_EL1 U(0x3) 366 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 367 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 368 #define MDCR_EL2_TDA_BIT (U(1) << 9) 369 #define MDCR_EL2_TDE_BIT (U(1) << 8) 370 #define MDCR_EL2_HPME_BIT (U(1) << 7) 371 #define MDCR_EL2_TPM_BIT (U(1) << 6) 372 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 373 #define MDCR_EL2_RESET_VAL U(0x0) 374 375 /* HSTR_EL2 definitions */ 376 #define HSTR_EL2_RESET_VAL U(0x0) 377 #define HSTR_EL2_T_MASK U(0xff) 378 379 /* CNTHP_CTL_EL2 definitions */ 380 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 381 #define CNTHP_CTL_RESET_VAL U(0x0) 382 383 /* VTTBR_EL2 definitions */ 384 #define VTTBR_RESET_VAL ULL(0x0) 385 #define VTTBR_VMID_MASK ULL(0xff) 386 #define VTTBR_VMID_SHIFT U(48) 387 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 388 #define VTTBR_BADDR_SHIFT U(0) 389 390 /* HCR definitions */ 391 #define HCR_API_BIT (ULL(1) << 41) 392 #define HCR_APK_BIT (ULL(1) << 40) 393 #define HCR_E2H_BIT (ULL(1) << 34) 394 #define HCR_TGE_BIT (ULL(1) << 27) 395 #define HCR_RW_SHIFT U(31) 396 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 397 #define HCR_AMO_BIT (ULL(1) << 5) 398 #define HCR_IMO_BIT (ULL(1) << 4) 399 #define HCR_FMO_BIT (ULL(1) << 3) 400 401 /* ISR definitions */ 402 #define ISR_A_SHIFT U(8) 403 #define ISR_I_SHIFT U(7) 404 #define ISR_F_SHIFT U(6) 405 406 /* CNTHCTL_EL2 definitions */ 407 #define CNTHCTL_RESET_VAL U(0x0) 408 #define EVNTEN_BIT (U(1) << 2) 409 #define EL1PCEN_BIT (U(1) << 1) 410 #define EL1PCTEN_BIT (U(1) << 0) 411 412 /* CNTKCTL_EL1 definitions */ 413 #define EL0PTEN_BIT (U(1) << 9) 414 #define EL0VTEN_BIT (U(1) << 8) 415 #define EL0PCTEN_BIT (U(1) << 0) 416 #define EL0VCTEN_BIT (U(1) << 1) 417 #define EVNTEN_BIT (U(1) << 2) 418 #define EVNTDIR_BIT (U(1) << 3) 419 #define EVNTI_SHIFT U(4) 420 #define EVNTI_MASK U(0xf) 421 422 /* CPTR_EL3 definitions */ 423 #define TCPAC_BIT (U(1) << 31) 424 #define TAM_BIT (U(1) << 30) 425 #define TTA_BIT (U(1) << 20) 426 #define TFP_BIT (U(1) << 10) 427 #define CPTR_EZ_BIT (U(1) << 8) 428 #define CPTR_EL3_RESET_VAL U(0x0) 429 430 /* CPTR_EL2 definitions */ 431 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 432 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 433 #define CPTR_EL2_TAM_BIT (U(1) << 30) 434 #define CPTR_EL2_TTA_BIT (U(1) << 20) 435 #define CPTR_EL2_TFP_BIT (U(1) << 10) 436 #define CPTR_EL2_TZ_BIT (U(1) << 8) 437 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 438 439 /* CPSR/SPSR definitions */ 440 #define DAIF_FIQ_BIT (U(1) << 0) 441 #define DAIF_IRQ_BIT (U(1) << 1) 442 #define DAIF_ABT_BIT (U(1) << 2) 443 #define DAIF_DBG_BIT (U(1) << 3) 444 #define SPSR_DAIF_SHIFT U(6) 445 #define SPSR_DAIF_MASK U(0xf) 446 447 #define SPSR_AIF_SHIFT U(6) 448 #define SPSR_AIF_MASK U(0x7) 449 450 #define SPSR_E_SHIFT U(9) 451 #define SPSR_E_MASK U(0x1) 452 #define SPSR_E_LITTLE U(0x0) 453 #define SPSR_E_BIG U(0x1) 454 455 #define SPSR_T_SHIFT U(5) 456 #define SPSR_T_MASK U(0x1) 457 #define SPSR_T_ARM U(0x0) 458 #define SPSR_T_THUMB U(0x1) 459 460 #define SPSR_M_SHIFT U(4) 461 #define SPSR_M_MASK U(0x1) 462 #define SPSR_M_AARCH64 U(0x0) 463 #define SPSR_M_AARCH32 U(0x1) 464 465 #define SPSR_EL_SHIFT U(2) 466 #define SPSR_EL_WIDTH U(2) 467 468 #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) 469 #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) 470 471 #define DISABLE_ALL_EXCEPTIONS \ 472 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 473 474 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 475 476 /* 477 * RMR_EL3 definitions 478 */ 479 #define RMR_EL3_RR_BIT (U(1) << 1) 480 #define RMR_EL3_AA64_BIT (U(1) << 0) 481 482 /* 483 * HI-VECTOR address for AArch32 state 484 */ 485 #define HI_VECTOR_BASE U(0xFFFF0000) 486 487 /* 488 * TCR defintions 489 */ 490 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 491 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 492 #define TCR_EL1_IPS_SHIFT U(32) 493 #define TCR_EL2_PS_SHIFT U(16) 494 #define TCR_EL3_PS_SHIFT U(16) 495 496 #define TCR_TxSZ_MIN ULL(16) 497 #define TCR_TxSZ_MAX ULL(39) 498 #define TCR_TxSZ_MAX_TTST ULL(48) 499 500 #define TCR_T0SZ_SHIFT U(0) 501 #define TCR_T1SZ_SHIFT U(16) 502 503 /* (internal) physical address size bits in EL3/EL1 */ 504 #define TCR_PS_BITS_4GB ULL(0x0) 505 #define TCR_PS_BITS_64GB ULL(0x1) 506 #define TCR_PS_BITS_1TB ULL(0x2) 507 #define TCR_PS_BITS_4TB ULL(0x3) 508 #define TCR_PS_BITS_16TB ULL(0x4) 509 #define TCR_PS_BITS_256TB ULL(0x5) 510 511 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 512 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 513 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 514 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 515 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 516 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 517 518 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 519 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 520 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 521 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 522 523 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 524 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 525 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 526 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 527 528 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 529 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 530 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 531 532 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 533 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 534 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 535 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 536 537 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 538 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 539 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 540 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 541 542 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 543 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 544 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 545 546 #define TCR_TG0_SHIFT U(14) 547 #define TCR_TG0_MASK ULL(3) 548 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 549 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 550 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 551 552 #define TCR_TG1_SHIFT U(30) 553 #define TCR_TG1_MASK ULL(3) 554 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 555 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 556 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 557 558 #define TCR_EPD0_BIT (ULL(1) << 7) 559 #define TCR_EPD1_BIT (ULL(1) << 23) 560 561 #define MODE_SP_SHIFT U(0x0) 562 #define MODE_SP_MASK U(0x1) 563 #define MODE_SP_EL0 U(0x0) 564 #define MODE_SP_ELX U(0x1) 565 566 #define MODE_RW_SHIFT U(0x4) 567 #define MODE_RW_MASK U(0x1) 568 #define MODE_RW_64 U(0x0) 569 #define MODE_RW_32 U(0x1) 570 571 #define MODE_EL_SHIFT U(0x2) 572 #define MODE_EL_MASK U(0x3) 573 #define MODE_EL_WIDTH U(0x2) 574 #define MODE_EL3 U(0x3) 575 #define MODE_EL2 U(0x2) 576 #define MODE_EL1 U(0x1) 577 #define MODE_EL0 U(0x0) 578 579 #define MODE32_SHIFT U(0) 580 #define MODE32_MASK U(0xf) 581 #define MODE32_usr U(0x0) 582 #define MODE32_fiq U(0x1) 583 #define MODE32_irq U(0x2) 584 #define MODE32_svc U(0x3) 585 #define MODE32_mon U(0x6) 586 #define MODE32_abt U(0x7) 587 #define MODE32_hyp U(0xa) 588 #define MODE32_und U(0xb) 589 #define MODE32_sys U(0xf) 590 591 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 592 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 593 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 594 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 595 596 #define SPSR_64(el, sp, daif) \ 597 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 598 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 599 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 600 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 601 (~(SPSR_SSBS_BIT_AARCH64))) 602 603 #define SPSR_MODE32(mode, isa, endian, aif) \ 604 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 605 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 606 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 607 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 608 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 609 (~(SPSR_SSBS_BIT_AARCH32))) 610 611 /* 612 * TTBR Definitions 613 */ 614 #define TTBR_CNP_BIT ULL(0x1) 615 616 /* 617 * CTR_EL0 definitions 618 */ 619 #define CTR_CWG_SHIFT U(24) 620 #define CTR_CWG_MASK U(0xf) 621 #define CTR_ERG_SHIFT U(20) 622 #define CTR_ERG_MASK U(0xf) 623 #define CTR_DMINLINE_SHIFT U(16) 624 #define CTR_DMINLINE_MASK U(0xf) 625 #define CTR_L1IP_SHIFT U(14) 626 #define CTR_L1IP_MASK U(0x3) 627 #define CTR_IMINLINE_SHIFT U(0) 628 #define CTR_IMINLINE_MASK U(0xf) 629 630 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 631 632 /* Physical timer control register bit fields shifts and masks */ 633 #define CNTP_CTL_ENABLE_SHIFT U(0) 634 #define CNTP_CTL_IMASK_SHIFT U(1) 635 #define CNTP_CTL_ISTATUS_SHIFT U(2) 636 637 #define CNTP_CTL_ENABLE_MASK U(1) 638 #define CNTP_CTL_IMASK_MASK U(1) 639 #define CNTP_CTL_ISTATUS_MASK U(1) 640 641 /* Physical timer control macros */ 642 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 643 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 644 645 /* Exception Syndrome register bits and bobs */ 646 #define ESR_EC_SHIFT U(26) 647 #define ESR_EC_MASK U(0x3f) 648 #define ESR_EC_LENGTH U(6) 649 #define ESR_ISS_SHIFT U(0) 650 #define ESR_ISS_LENGTH U(25) 651 #define EC_UNKNOWN U(0x0) 652 #define EC_WFE_WFI U(0x1) 653 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 654 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 655 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 656 #define EC_AARCH32_CP14_LDC_STC U(0x6) 657 #define EC_FP_SIMD U(0x7) 658 #define EC_AARCH32_CP10_MRC U(0x8) 659 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 660 #define EC_ILLEGAL U(0xe) 661 #define EC_AARCH32_SVC U(0x11) 662 #define EC_AARCH32_HVC U(0x12) 663 #define EC_AARCH32_SMC U(0x13) 664 #define EC_AARCH64_SVC U(0x15) 665 #define EC_AARCH64_HVC U(0x16) 666 #define EC_AARCH64_SMC U(0x17) 667 #define EC_AARCH64_SYS U(0x18) 668 #define EC_IABORT_LOWER_EL U(0x20) 669 #define EC_IABORT_CUR_EL U(0x21) 670 #define EC_PC_ALIGN U(0x22) 671 #define EC_DABORT_LOWER_EL U(0x24) 672 #define EC_DABORT_CUR_EL U(0x25) 673 #define EC_SP_ALIGN U(0x26) 674 #define EC_AARCH32_FP U(0x28) 675 #define EC_AARCH64_FP U(0x2c) 676 #define EC_SERROR U(0x2f) 677 #define EC_BRK U(0x3c) 678 679 /* 680 * External Abort bit in Instruction and Data Aborts synchronous exception 681 * syndromes. 682 */ 683 #define ESR_ISS_EABORT_EA_BIT U(9) 684 685 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 686 687 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 688 #define RMR_RESET_REQUEST_SHIFT U(0x1) 689 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 690 691 /******************************************************************************* 692 * Definitions of register offsets, fields and macros for CPU system 693 * instructions. 694 ******************************************************************************/ 695 696 #define TLBI_ADDR_SHIFT U(12) 697 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 698 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 699 700 /******************************************************************************* 701 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 702 * system level implementation of the Generic Timer. 703 ******************************************************************************/ 704 #define CNTCTLBASE_CNTFRQ U(0x0) 705 #define CNTNSAR U(0x4) 706 #define CNTNSAR_NS_SHIFT(x) (x) 707 708 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 709 #define CNTACR_RPCT_SHIFT U(0x0) 710 #define CNTACR_RVCT_SHIFT U(0x1) 711 #define CNTACR_RFRQ_SHIFT U(0x2) 712 #define CNTACR_RVOFF_SHIFT U(0x3) 713 #define CNTACR_RWVT_SHIFT U(0x4) 714 #define CNTACR_RWPT_SHIFT U(0x5) 715 716 /******************************************************************************* 717 * Definitions of register offsets and fields in the CNTBaseN Frame of the 718 * system level implementation of the Generic Timer. 719 ******************************************************************************/ 720 /* Physical Count register. */ 721 #define CNTPCT_LO U(0x0) 722 /* Counter Frequency register. */ 723 #define CNTBASEN_CNTFRQ U(0x10) 724 /* Physical Timer CompareValue register. */ 725 #define CNTP_CVAL_LO U(0x20) 726 /* Physical Timer Control register. */ 727 #define CNTP_CTL U(0x2c) 728 729 /* PMCR_EL0 definitions */ 730 #define PMCR_EL0_RESET_VAL U(0x0) 731 #define PMCR_EL0_N_SHIFT U(11) 732 #define PMCR_EL0_N_MASK U(0x1f) 733 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 734 #define PMCR_EL0_LP_BIT (U(1) << 7) 735 #define PMCR_EL0_LC_BIT (U(1) << 6) 736 #define PMCR_EL0_DP_BIT (U(1) << 5) 737 #define PMCR_EL0_X_BIT (U(1) << 4) 738 #define PMCR_EL0_D_BIT (U(1) << 3) 739 #define PMCR_EL0_C_BIT (U(1) << 2) 740 #define PMCR_EL0_P_BIT (U(1) << 1) 741 #define PMCR_EL0_E_BIT (U(1) << 0) 742 743 /******************************************************************************* 744 * Definitions for system register interface to SVE 745 ******************************************************************************/ 746 #define ZCR_EL3 S3_6_C1_C2_0 747 #define ZCR_EL2 S3_4_C1_C2_0 748 749 /* ZCR_EL3 definitions */ 750 #define ZCR_EL3_LEN_MASK U(0xf) 751 752 /* ZCR_EL2 definitions */ 753 #define ZCR_EL2_LEN_MASK U(0xf) 754 755 /******************************************************************************* 756 * Definitions of MAIR encodings for device and normal memory 757 ******************************************************************************/ 758 /* 759 * MAIR encodings for device memory attributes. 760 */ 761 #define MAIR_DEV_nGnRnE ULL(0x0) 762 #define MAIR_DEV_nGnRE ULL(0x4) 763 #define MAIR_DEV_nGRE ULL(0x8) 764 #define MAIR_DEV_GRE ULL(0xc) 765 766 /* 767 * MAIR encodings for normal memory attributes. 768 * 769 * Cache Policy 770 * WT: Write Through 771 * WB: Write Back 772 * NC: Non-Cacheable 773 * 774 * Transient Hint 775 * NTR: Non-Transient 776 * TR: Transient 777 * 778 * Allocation Policy 779 * RA: Read Allocate 780 * WA: Write Allocate 781 * RWA: Read and Write Allocate 782 * NA: No Allocation 783 */ 784 #define MAIR_NORM_WT_TR_WA ULL(0x1) 785 #define MAIR_NORM_WT_TR_RA ULL(0x2) 786 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 787 #define MAIR_NORM_NC ULL(0x4) 788 #define MAIR_NORM_WB_TR_WA ULL(0x5) 789 #define MAIR_NORM_WB_TR_RA ULL(0x6) 790 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 791 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 792 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 793 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 794 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 795 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 796 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 797 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 798 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 799 800 #define MAIR_NORM_OUTER_SHIFT U(4) 801 802 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 803 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 804 805 /* PAR_EL1 fields */ 806 #define PAR_F_SHIFT U(0) 807 #define PAR_F_MASK ULL(0x1) 808 #define PAR_ADDR_SHIFT U(12) 809 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 810 811 /******************************************************************************* 812 * Definitions for system register interface to SPE 813 ******************************************************************************/ 814 #define PMBLIMITR_EL1 S3_0_C9_C10_0 815 816 /******************************************************************************* 817 * Definitions for system register interface to MPAM 818 ******************************************************************************/ 819 #define MPAMIDR_EL1 S3_0_C10_C4_4 820 #define MPAM2_EL2 S3_4_C10_C5_0 821 #define MPAMHCR_EL2 S3_4_C10_C4_0 822 #define MPAM3_EL3 S3_6_C10_C5_0 823 824 /******************************************************************************* 825 * Definitions for system register interface to AMU for ARMv8.4 onwards 826 ******************************************************************************/ 827 #define AMCR_EL0 S3_3_C13_C2_0 828 #define AMCFGR_EL0 S3_3_C13_C2_1 829 #define AMCGCR_EL0 S3_3_C13_C2_2 830 #define AMUSERENR_EL0 S3_3_C13_C2_3 831 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 832 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 833 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 834 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 835 836 /* Activity Monitor Group 0 Event Counter Registers */ 837 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 838 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 839 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 840 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 841 842 /* Activity Monitor Group 0 Event Type Registers */ 843 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 844 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 845 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 846 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 847 848 /* Activity Monitor Group 1 Event Counter Registers */ 849 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 850 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 851 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 852 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 853 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 854 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 855 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 856 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 857 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 858 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 859 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 860 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 861 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 862 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 863 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 864 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 865 866 /* Activity Monitor Group 1 Event Type Registers */ 867 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 868 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 869 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 870 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 871 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 872 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 873 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 874 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 875 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 876 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 877 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 878 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 879 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 880 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 881 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 882 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 883 884 /* AMCGCR_EL0 definitions */ 885 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 886 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 887 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 888 889 /* MPAM register definitions */ 890 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 891 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 892 893 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 894 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 895 896 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 897 898 /******************************************************************************* 899 * RAS system registers 900 ******************************************************************************/ 901 #define DISR_EL1 S3_0_C12_C1_1 902 #define DISR_A_BIT U(31) 903 904 #define ERRIDR_EL1 S3_0_C5_C3_0 905 #define ERRIDR_MASK U(0xffff) 906 907 #define ERRSELR_EL1 S3_0_C5_C3_1 908 909 /* System register access to Standard Error Record registers */ 910 #define ERXFR_EL1 S3_0_C5_C4_0 911 #define ERXCTLR_EL1 S3_0_C5_C4_1 912 #define ERXSTATUS_EL1 S3_0_C5_C4_2 913 #define ERXADDR_EL1 S3_0_C5_C4_3 914 #define ERXPFGF_EL1 S3_0_C5_C4_4 915 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 916 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 917 #define ERXMISC0_EL1 S3_0_C5_C5_0 918 #define ERXMISC1_EL1 S3_0_C5_C5_1 919 920 #define ERXCTLR_ED_BIT (U(1) << 0) 921 #define ERXCTLR_UE_BIT (U(1) << 4) 922 923 #define ERXPFGCTL_UC_BIT (U(1) << 1) 924 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 925 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 926 927 /******************************************************************************* 928 * Armv8.3 Pointer Authentication Registers 929 ******************************************************************************/ 930 #define APIAKeyLo_EL1 S3_0_C2_C1_0 931 #define APIAKeyHi_EL1 S3_0_C2_C1_1 932 #define APIBKeyLo_EL1 S3_0_C2_C1_2 933 #define APIBKeyHi_EL1 S3_0_C2_C1_3 934 #define APDAKeyLo_EL1 S3_0_C2_C2_0 935 #define APDAKeyHi_EL1 S3_0_C2_C2_1 936 #define APDBKeyLo_EL1 S3_0_C2_C2_2 937 #define APDBKeyHi_EL1 S3_0_C2_C2_3 938 #define APGAKeyLo_EL1 S3_0_C2_C3_0 939 #define APGAKeyHi_EL1 S3_0_C2_C3_1 940 941 /******************************************************************************* 942 * Armv8.4 Data Independent Timing Registers 943 ******************************************************************************/ 944 #define DIT S3_3_C4_C2_5 945 #define DIT_BIT BIT(24) 946 947 /******************************************************************************* 948 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 949 ******************************************************************************/ 950 #define SSBS S3_3_C4_C2_6 951 952 /******************************************************************************* 953 * Armv8.5 - Memory Tagging Extension Registers 954 ******************************************************************************/ 955 #define TFSRE0_EL1 S3_0_C5_C6_1 956 #define TFSR_EL1 S3_0_C5_C6_0 957 #define RGSR_EL1 S3_0_C1_C0_5 958 #define GCR_EL1 S3_0_C1_C0_6 959 960 /******************************************************************************* 961 * Definitions for DynamicIQ Shared Unit registers 962 ******************************************************************************/ 963 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 964 965 /* CLUSTERPWRDN_EL1 register definitions */ 966 #define DSU_CLUSTER_PWR_OFF 0 967 #define DSU_CLUSTER_PWR_ON 1 968 #define DSU_CLUSTER_PWR_MASK U(1) 969 970 #endif /* ARCH_H */ 971