1/* 2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <common/bl_common.ld.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12OUTPUT_FORMAT(elf32-littlearm) 13OUTPUT_ARCH(arm) 14ENTRY(sp_min_vector_table) 15 16MEMORY { 17 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 18} 19 20#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 21#include <plat_sp_min.ld.S> 22#endif 23 24SECTIONS 25{ 26 . = BL32_BASE; 27 ASSERT(. == ALIGN(PAGE_SIZE), 28 "BL32_BASE address is not aligned on a page boundary.") 29 30#if SEPARATE_CODE_AND_RODATA 31 .text . : { 32 __TEXT_START__ = .; 33 *entrypoint.o(.text*) 34 *(.text*) 35 *(.vectors) 36 . = ALIGN(PAGE_SIZE); 37 __TEXT_END__ = .; 38 } >RAM 39 40 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 41 .ARM.extab . : { 42 *(.ARM.extab* .gnu.linkonce.armextab.*) 43 } >RAM 44 45 .ARM.exidx . : { 46 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 47 } >RAM 48 49 .rodata . : { 50 __RODATA_START__ = .; 51 *(.rodata*) 52 53 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 54 . = ALIGN(4); 55 __RT_SVC_DESCS_START__ = .; 56 KEEP(*(rt_svc_descs)) 57 __RT_SVC_DESCS_END__ = .; 58 59 . = ALIGN(4); 60 __FCONF_POPULATOR_START__ = .; 61 KEEP(*(.fconf_populator)) 62 __FCONF_POPULATOR_END__ = .; 63 64#if ENABLE_PMF 65 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 66 . = ALIGN(4); 67 __PMF_SVC_DESCS_START__ = .; 68 KEEP(*(pmf_svc_descs)) 69 __PMF_SVC_DESCS_END__ = .; 70#endif /* ENABLE_PMF */ 71 72 /* 73 * Ensure 4-byte alignment for cpu_ops so that its fields are also 74 * aligned. Also ensure cpu_ops inclusion. 75 */ 76 . = ALIGN(4); 77 __CPU_OPS_START__ = .; 78 KEEP(*(cpu_ops)) 79 __CPU_OPS_END__ = .; 80 81 /* Place pubsub sections for events */ 82 . = ALIGN(8); 83#include <lib/el3_runtime/pubsub_events.h> 84 85 . = ALIGN(PAGE_SIZE); 86 __RODATA_END__ = .; 87 } >RAM 88#else 89 ro . : { 90 __RO_START__ = .; 91 *entrypoint.o(.text*) 92 *(.text*) 93 *(.rodata*) 94 95 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 96 . = ALIGN(4); 97 __RT_SVC_DESCS_START__ = .; 98 KEEP(*(rt_svc_descs)) 99 __RT_SVC_DESCS_END__ = .; 100 101 . = ALIGN(4); 102 __FCONF_POPULATOR_START__ = .; 103 KEEP(*(.fconf_populator)) 104 __FCONF_POPULATOR_END__ = .; 105 106 /* 107 * Ensure 4-byte alignment for cpu_ops so that its fields are also 108 * aligned. Also ensure cpu_ops inclusion. 109 */ 110 . = ALIGN(4); 111 __CPU_OPS_START__ = .; 112 KEEP(*(cpu_ops)) 113 __CPU_OPS_END__ = .; 114 115 /* Place pubsub sections for events */ 116 . = ALIGN(8); 117#include <lib/el3_runtime/pubsub_events.h> 118 119 *(.vectors) 120 __RO_END_UNALIGNED__ = .; 121 122 /* 123 * Memory page(s) mapped to this section will be marked as 124 * read-only, executable. No RW data from the next section must 125 * creep in. Ensure the rest of the current memory block is unused. 126 */ 127 . = ALIGN(PAGE_SIZE); 128 __RO_END__ = .; 129 } >RAM 130#endif 131 132 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 133 "cpu_ops not defined for this platform.") 134 /* 135 * Define a linker symbol to mark start of the RW memory area for this 136 * image. 137 */ 138 __RW_START__ = . ; 139 140 .data . : { 141 __DATA_START__ = .; 142 *(.data*) 143 __DATA_END__ = .; 144 } >RAM 145 146#ifdef BL32_PROGBITS_LIMIT 147 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 148#endif 149 150 stacks (NOLOAD) : { 151 __STACKS_START__ = .; 152 *(tzfw_normal_stacks) 153 __STACKS_END__ = .; 154 } >RAM 155 156 /* 157 * The .bss section gets initialised to 0 at runtime. 158 * Its base address should be 8-byte aligned for better performance of the 159 * zero-initialization code. 160 */ 161 .bss (NOLOAD) : ALIGN(8) { 162 __BSS_START__ = .; 163 *(.bss*) 164 *(COMMON) 165#if !USE_COHERENT_MEM 166 /* 167 * Bakery locks are stored in normal .bss memory 168 * 169 * Each lock's data is spread across multiple cache lines, one per CPU, 170 * but multiple locks can share the same cache line. 171 * The compiler will allocate enough memory for one CPU's bakery locks, 172 * the remaining cache lines are allocated by the linker script 173 */ 174 . = ALIGN(CACHE_WRITEBACK_GRANULE); 175 __BAKERY_LOCK_START__ = .; 176 __PERCPU_BAKERY_LOCK_START__ = .; 177 *(bakery_lock) 178 . = ALIGN(CACHE_WRITEBACK_GRANULE); 179 __PERCPU_BAKERY_LOCK_END__ = .; 180 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 181 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 182 __BAKERY_LOCK_END__ = .; 183#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 184 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 185 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 186#endif 187#endif 188 189#if ENABLE_PMF 190 /* 191 * Time-stamps are stored in normal .bss memory 192 * 193 * The compiler will allocate enough memory for one CPU's time-stamps, 194 * the remaining memory for other CPUs is allocated by the 195 * linker script 196 */ 197 . = ALIGN(CACHE_WRITEBACK_GRANULE); 198 __PMF_TIMESTAMP_START__ = .; 199 KEEP(*(pmf_timestamp_array)) 200 . = ALIGN(CACHE_WRITEBACK_GRANULE); 201 __PMF_PERCPU_TIMESTAMP_END__ = .; 202 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 203 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 204 __PMF_TIMESTAMP_END__ = .; 205#endif /* ENABLE_PMF */ 206 207 __BSS_END__ = .; 208 } >RAM 209 210 XLAT_TABLE_SECTION >RAM 211 212 __BSS_SIZE__ = SIZEOF(.bss); 213 214#if USE_COHERENT_MEM 215 /* 216 * The base address of the coherent memory section must be page-aligned (4K) 217 * to guarantee that the coherent data are stored on their own pages and 218 * are not mixed with normal data. This is required to set up the correct 219 * memory attributes for the coherent data page tables. 220 */ 221 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 222 __COHERENT_RAM_START__ = .; 223 /* 224 * Bakery locks are stored in coherent memory 225 * 226 * Each lock's data is contiguous and fully allocated by the compiler 227 */ 228 *(bakery_lock) 229 *(tzfw_coherent_mem) 230 __COHERENT_RAM_END_UNALIGNED__ = .; 231 /* 232 * Memory page(s) mapped to this section will be marked 233 * as device memory. No other unexpected data must creep in. 234 * Ensure the rest of the current memory page is unused. 235 */ 236 . = ALIGN(PAGE_SIZE); 237 __COHERENT_RAM_END__ = .; 238 } >RAM 239 240 __COHERENT_RAM_UNALIGNED_SIZE__ = 241 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 242#endif 243 244 /* 245 * Define a linker symbol to mark end of the RW memory area for this 246 * image. 247 */ 248 __RW_END__ = .; 249 250 __BL32_END__ = .; 251} 252