1 /* 2 * Copyright (c) 2019-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/console.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 #include <plat/common/common_def.h> 12 13 #include <fsx.h> 14 #include <platform_def.h> 15 #include <sr_utils.h> 16 17 #define FS4_IDM_IO_CONTROL_DIRECT__SRAM_CLK_EN 0 18 19 #define FS4_IDM_IO_CONTROL_DIRECT__MEM_POWERON 11 20 #define FS4_IDM_IO_CONTROL_DIRECT__MEM_POWEROK 12 21 #define FS4_IDM_IO_CONTROL_DIRECT__MEM_ARRPOWERON 13 22 #define FS4_IDM_IO_CONTROL_DIRECT__MEM_ARRPOWEROK 14 23 #define FS4_IDM_IO_CONTROL_DIRECT__MEM_ISO 15 24 #define FS4_IDM_IO_CONTROL_DIRECT__CLK_EN 31 25 26 #define FS4_IDM_IO_STATUS__MEM_POWERON 0 27 #define FS4_IDM_IO_STATUS__MEM_POWEROK 1 28 #define FS4_IDM_IO_STATUS__MEM_ARRPOWERON 2 29 #define FS4_IDM_IO_STATUS__MEM_ARRPOWEROK 3 30 #define FS4_IDM_IO_STATUS__MEM_ALLOK 0xf 31 32 #define FS4_IDM_RESET_CONTROL__RESET 0 33 34 #define FSX_RINGx_BASE(__b, __i) \ 35 ((__b) + (__i) * 0x10000) 36 37 #define FSX_RINGx_VERSION_NUMBER(__b, __i) \ 38 (FSX_RINGx_BASE(__b, __i) + 0x0) 39 40 #define FSX_RINGx_MSI_DEV_ID(__b, __i) \ 41 (FSX_RINGx_BASE(__b, __i) + 0x44) 42 43 #define FSX_COMM_RINGx_BASE(__b, __i) \ 44 ((__b) + 0x200000 + (__i) * 0x100) 45 46 #define FSX_COMM_RINGx_CONTROL(__b, __i) \ 47 (FSX_COMM_RINGx_BASE(__b, __i) + 0x0) 48 #define FSX_COMM_RINGx_CONTROL__AXI_ID 8 49 #define FSX_COMM_RINGx_CONTROL__AXI_ID_MASK 0x1f 50 #define FSX_COMM_RINGx_CONTROL__PRIORITY 4 51 #define FSX_COMM_RINGx_CONTROL__PRIORITY_MASK 0x7 52 #define FSX_COMM_RINGx_CONTROL__AE_GROUP 0 53 #define FSX_COMM_RINGx_CONTROL__AE_GROUP_MASK 0x7 54 55 #define FSX_COMM_RINGx_MSI_DEV_ID(__b, __i) \ 56 (FSX_COMM_RINGx_BASE(__b, __i) + 0x4) 57 58 #define FSX_AEx_BASE(__b, __i) \ 59 ((__b) + 0x202000 + (__i) * 0x100) 60 61 #define FSX_AEx_CONTROL_REGISTER(__b, __i) \ 62 (FSX_AEx_BASE(__b, __i) + 0x0) 63 #define FSX_AEx_CONTROL_REGISTER__ACTIVE 4 64 #define FSX_AEx_CONTROL_REGISTER__GROUP_ID 0 65 #define FSX_AEx_CONTROL_REGISTER__GROUP_ID_MASK 0x7 66 67 #define FSX_COMM_RM_RING_SECURITY_SETTING 0x0 68 69 #define FSX_COMM_RM_SSID_CONTROL 0x4 70 #define FSX_COMM_RM_SSID_CONTROL__RING_BITS 5 71 #define FSX_COMM_RM_SSID_CONTROL__MASK 0x3ff 72 73 #define FSX_COMM_RM_CONTROL_REGISTER 0x8 74 #define FSX_COMM_RM_CONTROL_REGISTER__CONFIG_DONE 2 75 #define FSX_COMM_RM_CONTROL_REGISTER__AE_TIMEOUT 5 76 #define FSX_COMM_RM_CONTROL_REGISTER__AE_LOCKING 7 77 78 #define FSX_COMM_RM_TIMER_CONTROL_0 0xc 79 #define FSX_COMM_RM_TIMER_CONTROL_0__FAST 16 80 #define FSX_COMM_RM_TIMER_CONTROL_0__MEDIUM 0 81 82 #define FSX_COMM_RM_TIMER_CONTROL_1 0x10 83 #define FSX_COMM_RM_TIMER_CONTROL_1__SLOW 16 84 #define FSX_COMM_RM_TIMER_CONTROL_1__IDLE 0 85 86 #define FSX_COMM_RM_BURST_BD_THRESHOLD 0x14 87 #define FSX_COMM_RM_BURST_BD_THRESHOLD_LOW 0 88 #define FSX_COMM_RM_BURST_BD_THRESHOLD_HIGH 16 89 90 #define FSX_COMM_RM_BURST_LENGTH 0x18 91 #define FSX_COMM_RM_BURST_LENGTH__FOR_DDR_ADDR_GEN 16 92 #define FSX_COMM_RM_BURST_LENGTH__FOR_DDR_ADDR_GEN_MASK 0x1ff 93 #define FSX_COMM_RM_BURST_LENGTH__FOR_TOGGLE 0 94 #define FSX_COMM_RM_BURST_LENGTH__FOR_TOGGLE_MASK 0x1ff 95 96 #define FSX_COMM_RM_FIFO_THRESHOLD 0x1c 97 #define FSX_COMM_RM_FIFO_THRESHOLD__BD_FIFO_FULL 16 98 #define FSX_COMM_RM_FIFO_THRESHOLD__BD_FIFO_FULL_MASK 0x1ff 99 #define FSX_COMM_RM_FIFO_THRESHOLD__AE_FIFO_FULL 0 100 #define FSX_COMM_RM_FIFO_THRESHOLD__AE_FIFO_FULL_MASK 0x1f 101 102 #define FSX_COMM_RM_AE_TIMEOUT 0x24 103 104 #define FSX_COMM_RM_RING_FLUSH_TIMEOUT 0x2c 105 106 #define FSX_COMM_RM_MEMORY_CONFIGURATION 0x30 107 #define FSX_COMM_RM_MEMORY_CONFIGURATION__ARRPOWERONIN 12 108 #define FSX_COMM_RM_MEMORY_CONFIGURATION__ARRPOWEROKIN 13 109 #define FSX_COMM_RM_MEMORY_CONFIGURATION__POWERONIN 14 110 #define FSX_COMM_RM_MEMORY_CONFIGURATION__POWEROKIN 15 111 112 #define FSX_COMM_RM_AXI_CONTROL 0x34 113 #define FSX_COMM_RM_AXI_CONTROL__WRITE_CHANNEL_EN 28 114 #define FSX_COMM_RM_AXI_CONTROL__READ_CHANNEL_EN 24 115 #define FSX_COMM_RM_AXI_CONTROL__AWQOS 20 116 #define FSX_COMM_RM_AXI_CONTROL__ARQOS 16 117 #define FSX_COMM_RM_AXI_CONTROL__AWPROT 12 118 #define FSX_COMM_RM_AXI_CONTROL__ARPROT 8 119 #define FSX_COMM_RM_AXI_CONTROL__AWCACHE 4 120 #define FSX_COMM_RM_AXI_CONTROL__ARCACHE 0 121 122 #define FSX_COMM_RM_CONFIG_INTERRUPT_STATUS_CLEAR 0x48 123 124 #define FSX_COMM_RM_GROUP_PKT_EXTENSION_SUPPORT 0xc0 125 126 #define FSX_COMM_RM_AXI_READ_BURST_THRESHOLD 0xc8 127 #define FSX_COMM_RM_AXI_READ_BURST_THRESHOLD__MASK 0x1ff 128 #define FSX_COMM_RM_AXI_READ_BURST_THRESHOLD__MAX 16 129 #define FSX_COMM_RM_AXI_READ_BURST_THRESHOLD__MIN 0 130 131 #define FSX_COMM_RM_GROUP_RING_COUNT 0xcc 132 133 #define FSX_COMM_RM_MAIN_HW_INIT_DONE 0x12c 134 #define FSX_COMM_RM_MAIN_HW_INIT_DONE__MASK 0x1 135 136 #define FSX_DMEx_BASE(__b, __i) \ 137 ((__b) + (__i) * 0x1000) 138 139 #define FSX_DMEx_AXI_CONTROL(__b, __i) \ 140 (FSX_DMEx_BASE(__b, __i) + 0x4) 141 #define FSX_DMEx_AXI_CONTROL__WRITE_CHANNEL_EN 28 142 #define FSX_DMEx_AXI_CONTROL__READ_CHANNEL_EN 24 143 #define FSX_DMEx_AXI_CONTROL__AWQOS 20 144 #define FSX_DMEx_AXI_CONTROL__ARQOS 16 145 #define FSX_DMEx_AXI_CONTROL__AWCACHE 4 146 #define FSX_DMEx_AXI_CONTROL__ARCACHE 0 147 148 #define FSX_DMEx_WR_FIFO_THRESHOLD(__b, __i) \ 149 (FSX_DMEx_BASE(__b, __i) + 0xc) 150 #define FSX_DMEx_WR_FIFO_THRESHOLD__MASK 0x3ff 151 #define FSX_DMEx_WR_FIFO_THRESHOLD__MAX 10 152 #define FSX_DMEx_WR_FIFO_THRESHOLD__MIN 0 153 154 #define FSX_DMEx_RD_FIFO_THRESHOLD(__b, __i) \ 155 (FSX_DMEx_BASE(__b, __i) + 0x14) 156 #define FSX_DMEx_RD_FIFO_THRESHOLD__MASK 0x3ff 157 #define FSX_DMEx_RD_FIFO_THRESHOLD__MAX 10 158 #define FSX_DMEx_RD_FIFO_THRESHOLD__MIN 0 159 160 #define FS6_SUB_TOP_BASE 0x66D8F800 161 #define FS6_PKI_DME_RESET 0x4 162 #define PKI_DME_RESET 1 163 164 char *fsx_type_names[] = { 165 "fs4-raid", 166 "fs4-crypto", 167 "fs6-pki", 168 }; 169 170 void fsx_init(eFSX_TYPE fsx_type, 171 unsigned int ring_count, 172 unsigned int dme_count, 173 unsigned int ae_count, 174 unsigned int start_stream_id, 175 unsigned int msi_dev_id, 176 uintptr_t idm_io_control_direct, 177 uintptr_t idm_reset_control, 178 uintptr_t base, 179 uintptr_t dme_base) 180 { 181 int try; 182 unsigned int i, v, data; 183 uintptr_t fs4_idm_io_control_direct = idm_io_control_direct; 184 uintptr_t fs4_idm_reset_control = idm_reset_control; 185 uintptr_t fsx_comm_rm = (base + 0x203000); 186 187 VERBOSE("fsx %s init start\n", fsx_type_names[fsx_type]); 188 189 if (fsx_type == eFS4_RAID || fsx_type == eFS4_CRYPTO) { 190 /* Enable FSx engine clock */ 191 VERBOSE(" - enable fsx clock\n"); 192 mmio_write_32(fs4_idm_io_control_direct, 193 (1U << FS4_IDM_IO_CONTROL_DIRECT__CLK_EN)); 194 udelay(500); 195 196 /* Reset FSx engine */ 197 VERBOSE(" - reset fsx\n"); 198 v = mmio_read_32(fs4_idm_reset_control); 199 v |= (1 << FS4_IDM_RESET_CONTROL__RESET); 200 mmio_write_32(fs4_idm_reset_control, v); 201 udelay(500); 202 v = mmio_read_32(fs4_idm_reset_control); 203 v &= ~(1 << FS4_IDM_RESET_CONTROL__RESET); 204 mmio_write_32(fs4_idm_reset_control, v); 205 } else { 206 /* 207 * Default RM and AE are out of reset, 208 * So only DME Reset added here 209 */ 210 v = mmio_read_32(FS6_SUB_TOP_BASE + FS6_PKI_DME_RESET); 211 v &= ~(PKI_DME_RESET); 212 mmio_write_32(FS6_SUB_TOP_BASE + FS6_PKI_DME_RESET, v); 213 } 214 215 /* Wait for HW-init done */ 216 VERBOSE(" - wait for HW-init done\n"); 217 try = 10000; 218 do { 219 udelay(1); 220 data = mmio_read_32(fsx_comm_rm + 221 FSX_COMM_RM_MAIN_HW_INIT_DONE); 222 try--; 223 } while (!(data & FSX_COMM_RM_MAIN_HW_INIT_DONE__MASK) && (try > 0)); 224 225 if (try <= 0) 226 ERROR("fsx_comm_rm + 0x%x: 0x%x\n", 227 data, FSX_COMM_RM_MAIN_HW_INIT_DONE); 228 229 /* Make all rings non-secured */ 230 VERBOSE(" - make all rings non-secured\n"); 231 v = 0xffffffff; 232 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_RING_SECURITY_SETTING, v); 233 234 /* Set start stream-id for rings to */ 235 VERBOSE(" - set start stream-id for rings to 0x%x\n", 236 start_stream_id); 237 v = start_stream_id >> FSX_COMM_RM_SSID_CONTROL__RING_BITS; 238 v &= FSX_COMM_RM_SSID_CONTROL__MASK; 239 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_SSID_CONTROL, v); 240 241 /* Set timer configuration */ 242 VERBOSE(" - set timer configuration\n"); 243 v = 0x0271 << FSX_COMM_RM_TIMER_CONTROL_0__MEDIUM; 244 v |= (0x0138 << FSX_COMM_RM_TIMER_CONTROL_0__FAST); 245 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_TIMER_CONTROL_0, v); 246 v = 0x09c4 << FSX_COMM_RM_TIMER_CONTROL_1__IDLE; 247 v |= (0x04e2 << FSX_COMM_RM_TIMER_CONTROL_1__SLOW); 248 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_TIMER_CONTROL_1, v); 249 v = 0x0000f424; 250 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_RING_FLUSH_TIMEOUT, v); 251 252 /* Set burst length and fifo threshold */ 253 VERBOSE(" - set burst length, fifo and bd threshold\n"); 254 v = 0x0; 255 v |= (0x8 << FSX_COMM_RM_BURST_LENGTH__FOR_DDR_ADDR_GEN); 256 v |= (0x8 << FSX_COMM_RM_BURST_LENGTH__FOR_TOGGLE); 257 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_BURST_LENGTH, v); 258 v = 0x0; 259 v |= (0x67 << FSX_COMM_RM_FIFO_THRESHOLD__BD_FIFO_FULL); 260 v |= (0x18 << FSX_COMM_RM_FIFO_THRESHOLD__AE_FIFO_FULL); 261 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_FIFO_THRESHOLD, v); 262 v = 0x0; 263 v |= (0x8 << FSX_COMM_RM_BURST_BD_THRESHOLD_LOW); 264 v |= (0x8 << FSX_COMM_RM_BURST_BD_THRESHOLD_HIGH); 265 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_BURST_BD_THRESHOLD, v); 266 267 /* Set memory configuration */ 268 VERBOSE(" - set memory configuration\n"); 269 v = 0x0; 270 v |= (1 << FSX_COMM_RM_MEMORY_CONFIGURATION__POWERONIN); 271 v |= (1 << FSX_COMM_RM_MEMORY_CONFIGURATION__POWEROKIN); 272 v |= (1 << FSX_COMM_RM_MEMORY_CONFIGURATION__ARRPOWERONIN); 273 v |= (1 << FSX_COMM_RM_MEMORY_CONFIGURATION__ARRPOWEROKIN); 274 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_MEMORY_CONFIGURATION, v); 275 276 /* AXI configuration for RM */ 277 v = 0; 278 v |= (0x1 << FSX_COMM_RM_AXI_CONTROL__WRITE_CHANNEL_EN); 279 v |= (0x1 << FSX_COMM_RM_AXI_CONTROL__READ_CHANNEL_EN); 280 v |= (0xe << FSX_COMM_RM_AXI_CONTROL__AWQOS); 281 v |= (0xa << FSX_COMM_RM_AXI_CONTROL__ARQOS); 282 v |= (0x2 << FSX_COMM_RM_AXI_CONTROL__AWPROT); 283 v |= (0x2 << FSX_COMM_RM_AXI_CONTROL__ARPROT); 284 v |= (0xf << FSX_COMM_RM_AXI_CONTROL__AWCACHE); 285 v |= (0xf << FSX_COMM_RM_AXI_CONTROL__ARCACHE); 286 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_AXI_CONTROL, v); 287 VERBOSE(" - set AXI control = 0x%x\n", 288 mmio_read_32(fsx_comm_rm + FSX_COMM_RM_AXI_CONTROL)); 289 v = 0x0; 290 v |= (0x10 << FSX_COMM_RM_AXI_READ_BURST_THRESHOLD__MAX); 291 v |= (0x10 << FSX_COMM_RM_AXI_READ_BURST_THRESHOLD__MIN); 292 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_AXI_READ_BURST_THRESHOLD, v); 293 VERBOSE(" - set AXI read burst threshold = 0x%x\n", 294 mmio_read_32(fsx_comm_rm + FSX_COMM_RM_AXI_READ_BURST_THRESHOLD)); 295 296 /* Configure group ring count for all groups */ 297 /* By default we schedule extended packets 298 * on all AEs/DMEs in a group. 299 */ 300 v = (dme_count & 0xf) << 0; 301 v |= (dme_count & 0xf) << 4; 302 v |= (dme_count & 0xf) << 8; 303 v |= (dme_count & 0xf) << 12; 304 v |= (dme_count & 0xf) << 16; 305 v |= (dme_count & 0xf) << 20; 306 v |= (dme_count & 0xf) << 24; 307 v |= (dme_count & 0xf) << 28; 308 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_GROUP_RING_COUNT, v); 309 310 /* 311 * Due to HW issue spurious interrupts are getting generated. 312 * To fix sw needs to clear the config status interrupts 313 * before setting CONFIG_DONE. 314 */ 315 mmio_write_32(fsx_comm_rm + 316 FSX_COMM_RM_CONFIG_INTERRUPT_STATUS_CLEAR, 317 0xffffffff); 318 319 /* Configure RM control */ 320 VERBOSE(" - configure RM control\n"); 321 v = mmio_read_32(fsx_comm_rm + FSX_COMM_RM_CONTROL_REGISTER); 322 v |= (1 << FSX_COMM_RM_CONTROL_REGISTER__AE_LOCKING); 323 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_CONTROL_REGISTER, v); 324 v |= (1 << FSX_COMM_RM_CONTROL_REGISTER__CONFIG_DONE); 325 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_CONTROL_REGISTER, v); 326 327 /* Configure AE timeout */ 328 VERBOSE(" - configure AE timeout\n"); 329 v = 0x00003fff; 330 mmio_write_32(fsx_comm_rm + FSX_COMM_RM_AE_TIMEOUT, v); 331 332 /* Initialize all AEs */ 333 for (i = 0; i < ae_count; i++) { 334 VERBOSE(" - initialize AE%d\n", i); 335 v = (0x1 << FSX_AEx_CONTROL_REGISTER__ACTIVE); 336 mmio_write_32(FSX_AEx_CONTROL_REGISTER(base, i), v); 337 } 338 339 /* Initialize all DMEs */ 340 for (i = 0; i < dme_count; i++) { 341 VERBOSE(" - initialize DME%d\n", i); 342 v = 0; 343 v |= (0x1 << FSX_DMEx_AXI_CONTROL__WRITE_CHANNEL_EN); 344 v |= (0x1 << FSX_DMEx_AXI_CONTROL__READ_CHANNEL_EN); 345 v |= (0xe << FSX_DMEx_AXI_CONTROL__AWQOS); 346 v |= (0xa << FSX_DMEx_AXI_CONTROL__ARQOS); 347 v |= (0xf << FSX_DMEx_AXI_CONTROL__AWCACHE); 348 v |= (0xf << FSX_DMEx_AXI_CONTROL__ARCACHE); 349 mmio_write_32(FSX_DMEx_AXI_CONTROL(dme_base, i), v); 350 VERBOSE(" -- AXI_CONTROL = 0x%x\n", 351 mmio_read_32(FSX_DMEx_AXI_CONTROL(dme_base, i))); 352 v = 0; 353 v |= (0x4 << FSX_DMEx_WR_FIFO_THRESHOLD__MIN); 354 v |= (0x4 << FSX_DMEx_WR_FIFO_THRESHOLD__MAX); 355 mmio_write_32(FSX_DMEx_WR_FIFO_THRESHOLD(dme_base, i), v); 356 VERBOSE(" -- WR_FIFO_THRESHOLD = 0x%x\n", 357 mmio_read_32(FSX_DMEx_WR_FIFO_THRESHOLD(dme_base, i))); 358 v = 0; 359 v |= (0x4 << FSX_DMEx_RD_FIFO_THRESHOLD__MIN); 360 v |= (0x4 << FSX_DMEx_RD_FIFO_THRESHOLD__MAX); 361 mmio_write_32(FSX_DMEx_RD_FIFO_THRESHOLD(dme_base, i), v); 362 VERBOSE(" -- RD_FIFO_THRESHOLD = 0x%x\n", 363 mmio_read_32(FSX_DMEx_RD_FIFO_THRESHOLD(dme_base, i))); 364 } 365 366 /* Configure ring axi id and msi device id */ 367 for (i = 0; i < ring_count; i++) { 368 VERBOSE(" - ring%d version=0x%x\n", i, 369 mmio_read_32(FSX_RINGx_VERSION_NUMBER(base, i))); 370 mmio_write_32(FSX_COMM_RINGx_MSI_DEV_ID(base, i), 371 msi_dev_id); 372 v = 0; 373 v |= ((i & FSX_COMM_RINGx_CONTROL__AXI_ID_MASK) << 374 FSX_COMM_RINGx_CONTROL__AXI_ID); 375 mmio_write_32(FSX_COMM_RINGx_CONTROL(base, i), v); 376 } 377 378 INFO("fsx %s init done\n", fsx_type_names[fsx_type]); 379 } 380 381 void fsx_meminit(const char *name, 382 uintptr_t idm_io_control_direct, 383 uintptr_t idm_io_status) 384 { 385 int try; 386 unsigned int val; 387 388 VERBOSE("fsx %s meminit start\n", name); 389 390 VERBOSE(" - arrpoweron\n"); 391 mmio_setbits_32(idm_io_control_direct, 392 BIT(FS4_IDM_IO_CONTROL_DIRECT__MEM_ARRPOWERON)); 393 while (!(mmio_read_32(idm_io_status) & 394 BIT(FS4_IDM_IO_STATUS__MEM_ARRPOWERON))) 395 ; 396 397 VERBOSE(" - arrpowerok\n"); 398 mmio_setbits_32(idm_io_control_direct, 399 (1 << FS4_IDM_IO_CONTROL_DIRECT__MEM_ARRPOWEROK)); 400 while (!(mmio_read_32(idm_io_status) & 401 BIT(FS4_IDM_IO_STATUS__MEM_ARRPOWEROK))) 402 ; 403 404 VERBOSE(" - poweron\n"); 405 mmio_setbits_32(idm_io_control_direct, 406 (1 << FS4_IDM_IO_CONTROL_DIRECT__MEM_POWERON)); 407 while (!(mmio_read_32(idm_io_status) & 408 BIT(FS4_IDM_IO_STATUS__MEM_POWERON))) 409 ; 410 411 VERBOSE(" - powerok\n"); 412 mmio_setbits_32(idm_io_control_direct, 413 (1 << FS4_IDM_IO_CONTROL_DIRECT__MEM_POWEROK)); 414 while (!(mmio_read_32(idm_io_status) & 415 BIT(FS4_IDM_IO_STATUS__MEM_POWEROK))) 416 ; 417 418 /* Final check on all power bits */ 419 try = 10; 420 do { 421 val = mmio_read_32(idm_io_status); 422 if (val == FS4_IDM_IO_STATUS__MEM_ALLOK) 423 break; 424 425 /* Wait sometime */ 426 mdelay(1); 427 428 try--; 429 } while (try > 0); 430 431 /* Remove memory isolation if things are fine. */ 432 if (try <= 0) { 433 INFO(" - powerup failed\n"); 434 } else { 435 VERBOSE(" - remove isolation\n"); 436 mmio_clrbits_32(idm_io_control_direct, 437 (1 << FS4_IDM_IO_CONTROL_DIRECT__MEM_ISO)); 438 VERBOSE(" - powerup done\n"); 439 } 440 441 INFO("fsx %s meminit done\n", name); 442 } 443 444 void fs4_disable_clocks(bool disable_sram, 445 bool disable_crypto, 446 bool disable_raid) 447 { 448 VERBOSE("fs4 disable clocks start\n"); 449 450 if (disable_sram) { 451 VERBOSE(" - disable sram clock\n"); 452 mmio_clrbits_32(FS4_SRAM_IDM_IO_CONTROL_DIRECT, 453 (1 << FS4_IDM_IO_CONTROL_DIRECT__SRAM_CLK_EN)); 454 } 455 456 if (disable_crypto) { 457 VERBOSE(" - disable crypto clock\n"); 458 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, 459 CDRU_GENPLL5_CONTROL1__CHNL1_CRYPTO_AE_CLK); 460 } 461 462 if (disable_raid) { 463 VERBOSE(" - disable raid clock\n"); 464 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, 465 CDRU_GENPLL5_CONTROL1__CHNL2_RAID_AE_CLK); 466 } 467 468 if (disable_sram && disable_crypto && disable_raid) { 469 VERBOSE(" - disable root clock\n"); 470 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, 471 CDRU_GENPLL5_CONTROL1__CHNL0_DME_CLK); 472 mmio_setbits_32(CDRU_GENPLL2_CONTROL1, 473 CDRU_GENPLL2_CONTROL1__CHNL6_FS4_CLK); 474 } 475 476 INFO("fs4 disable clocks done\n"); 477 } 478