1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32_console.h> 20 #include <drivers/st/stm32_iwdg.h> 21 #include <drivers/st/stm32mp_pmic.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_pwr.h> 25 #include <drivers/st/stm32mp1_ram.h> 26 #include <lib/mmio.h> 27 #include <lib/optee_utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <stm32mp1_context.h> 32 #include <stm32mp1_dbgmcu.h> 33 34 static console_t console; 35 static struct stm32mp_auth_ops stm32mp1_auth_ops; 36 37 static void print_reset_reason(void) 38 { 39 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 40 41 if (rstsr == 0U) { 42 WARN("Reset reason unknown\n"); 43 return; 44 } 45 46 INFO("Reset reason (0x%x):\n", rstsr); 47 48 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 49 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 50 INFO("System exits from STANDBY\n"); 51 return; 52 } 53 54 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 55 INFO("MPU exits from CSTANDBY\n"); 56 return; 57 } 58 } 59 60 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 61 INFO(" Power-on Reset (rst_por)\n"); 62 return; 63 } 64 65 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 66 INFO(" Brownout Reset (rst_bor)\n"); 67 return; 68 } 69 70 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 71 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 72 INFO(" System reset generated by MCU (MCSYSRST)\n"); 73 } else { 74 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 75 } 76 return; 77 } 78 79 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 80 INFO(" System reset generated by MPU (MPSYSRST)\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 85 INFO(" Reset due to a clock failure on HSE\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 90 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 95 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 100 INFO(" MPU Processor 0 Reset\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 105 INFO(" MPU Processor 1 Reset\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 110 INFO(" Pad Reset from NRST\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 115 INFO(" Reset due to a failure of VDD_CORE\n"); 116 return; 117 } 118 119 ERROR(" Unidentified reset reason\n"); 120 } 121 122 void bl2_el3_early_platform_setup(u_register_t arg0, 123 u_register_t arg1 __unused, 124 u_register_t arg2 __unused, 125 u_register_t arg3 __unused) 126 { 127 stm32mp_save_boot_ctx_address(arg0); 128 } 129 130 void bl2_platform_setup(void) 131 { 132 int ret; 133 uint32_t ddr_ns_size; 134 135 if (dt_pmic_status() > 0) { 136 initialize_pmic(); 137 } 138 139 ret = stm32mp1_ddr_probe(); 140 if (ret < 0) { 141 ERROR("Invalid DDR init: error %d\n", ret); 142 panic(); 143 } 144 145 ddr_ns_size = stm32mp_get_ddr_ns_size(); 146 assert(ddr_ns_size > 0U); 147 148 /* Map non secure DDR for BL33 load, now with cacheable attribute */ 149 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 150 ddr_ns_size, MT_MEMORY | MT_RW | MT_NS); 151 assert(ret == 0); 152 153 #ifdef AARCH32_SP_OPTEE 154 INFO("BL2 runs OP-TEE setup\n"); 155 156 /* Map secure DDR for OP-TEE paged area */ 157 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size, 158 STM32MP_DDR_BASE + ddr_ns_size, 159 STM32MP_DDR_S_SIZE, 160 MT_MEMORY | MT_RW | MT_SECURE); 161 assert(ret == 0); 162 163 /* Initialize tzc400 after DDR initialization */ 164 stm32mp1_security_setup(); 165 #else 166 INFO("BL2 runs SP_MIN setup\n"); 167 #endif 168 } 169 170 void bl2_el3_plat_arch_setup(void) 171 { 172 int32_t result; 173 struct dt_node_info dt_uart_info; 174 const char *board_model; 175 boot_api_context_t *boot_context = 176 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 177 uint32_t clk_rate; 178 uintptr_t pwr_base; 179 uintptr_t rcc_base; 180 181 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 182 BL_CODE_END - BL_CODE_BASE, 183 MT_CODE | MT_SECURE); 184 185 #ifdef AARCH32_SP_OPTEE 186 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 187 STM32MP_OPTEE_SIZE, 188 MT_MEMORY | MT_RW | MT_SECURE); 189 #else 190 /* Prevent corruption of preloaded BL32 */ 191 mmap_add_region(BL32_BASE, BL32_BASE, 192 BL32_LIMIT - BL32_BASE, 193 MT_RO_DATA | MT_SECURE); 194 #endif 195 /* Prevent corruption of preloaded Device Tree */ 196 mmap_add_region(DTB_BASE, DTB_BASE, 197 DTB_LIMIT - DTB_BASE, 198 MT_RO_DATA | MT_SECURE); 199 200 configure_mmu(); 201 202 if (dt_open_and_check() < 0) { 203 panic(); 204 } 205 206 pwr_base = stm32mp_pwr_base(); 207 rcc_base = stm32mp_rcc_base(); 208 209 /* 210 * Disable the backup domain write protection. 211 * The protection is enable at each reset by hardware 212 * and must be disabled by software. 213 */ 214 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 215 216 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 217 ; 218 } 219 220 if (bsec_probe() != 0) { 221 panic(); 222 } 223 224 /* Reset backup domain on cold boot cases */ 225 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 226 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 227 228 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 229 0U) { 230 ; 231 } 232 233 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 234 } 235 236 /* Disable MCKPROT */ 237 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 238 239 generic_delay_timer_init(); 240 241 if (stm32mp1_clk_probe() < 0) { 242 panic(); 243 } 244 245 if (stm32mp1_clk_init() < 0) { 246 panic(); 247 } 248 249 stm32mp1_syscfg_init(); 250 251 result = dt_get_stdout_uart_info(&dt_uart_info); 252 253 if ((result <= 0) || 254 (dt_uart_info.status == 0U) || 255 (dt_uart_info.clock < 0) || 256 (dt_uart_info.reset < 0)) { 257 goto skip_console_init; 258 } 259 260 if (dt_set_stdout_pinctrl() != 0) { 261 goto skip_console_init; 262 } 263 264 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 265 266 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 267 udelay(2); 268 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 269 mdelay(1); 270 271 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 272 273 if (console_stm32_register(dt_uart_info.base, clk_rate, 274 STM32MP_UART_BAUDRATE, &console) == 0) { 275 panic(); 276 } 277 278 console_set_scope(&console, CONSOLE_FLAG_BOOT | 279 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); 280 281 stm32mp_print_cpuinfo(); 282 283 board_model = dt_get_board_model(); 284 if (board_model != NULL) { 285 NOTICE("Model: %s\n", board_model); 286 } 287 288 stm32mp_print_boardinfo(); 289 290 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 291 NOTICE("Bootrom authentication %s\n", 292 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 293 "failed" : "succeeded"); 294 } 295 296 skip_console_init: 297 if (stm32_iwdg_init() < 0) { 298 panic(); 299 } 300 301 stm32_iwdg_refresh(); 302 303 result = stm32mp1_dbgmcu_freeze_iwdg2(); 304 if (result != 0) { 305 INFO("IWDG2 freeze error : %i\n", result); 306 } 307 308 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 309 boot_context->boot_interface_instance) != 310 0) { 311 ERROR("Cannot save boot interface\n"); 312 } 313 314 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 315 stm32mp1_auth_ops.verify_signature = 316 boot_context->bootrom_ecdsa_verify_signature; 317 318 stm32mp_init_auth(&stm32mp1_auth_ops); 319 320 stm32mp1_arch_security_setup(); 321 322 print_reset_reason(); 323 324 stm32mp_io_setup(); 325 } 326 327 #if defined(AARCH32_SP_OPTEE) 328 /******************************************************************************* 329 * This function can be used by the platforms to update/use image 330 * information for given `image_id`. 331 ******************************************************************************/ 332 int bl2_plat_handle_post_image_load(unsigned int image_id) 333 { 334 int err = 0; 335 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 336 bl_mem_params_node_t *bl32_mem_params; 337 bl_mem_params_node_t *pager_mem_params; 338 bl_mem_params_node_t *paged_mem_params; 339 340 assert(bl_mem_params != NULL); 341 342 switch (image_id) { 343 case BL32_IMAGE_ID: 344 bl_mem_params->ep_info.pc = 345 bl_mem_params->image_info.image_base; 346 347 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 348 assert(pager_mem_params != NULL); 349 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 350 pager_mem_params->image_info.image_max_size = 351 STM32MP_OPTEE_SIZE; 352 353 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 354 assert(paged_mem_params != NULL); 355 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 356 stm32mp_get_ddr_ns_size(); 357 paged_mem_params->image_info.image_max_size = 358 STM32MP_DDR_S_SIZE; 359 360 err = parse_optee_header(&bl_mem_params->ep_info, 361 &pager_mem_params->image_info, 362 &paged_mem_params->image_info); 363 if (err) { 364 ERROR("OPTEE header parse error.\n"); 365 panic(); 366 } 367 368 /* Set optee boot info from parsed header data */ 369 bl_mem_params->ep_info.pc = 370 pager_mem_params->image_info.image_base; 371 bl_mem_params->ep_info.args.arg0 = 372 paged_mem_params->image_info.image_base; 373 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 374 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 375 break; 376 377 case BL33_IMAGE_ID: 378 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 379 assert(bl32_mem_params != NULL); 380 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 381 break; 382 383 default: 384 /* Do nothing in default case */ 385 break; 386 } 387 388 return err; 389 } 390 #endif 391