feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
i

feat(s32g274ardb): add DDR clock source support

Introduce support to configure DDR clock
source and safely deasserting the reset
signal for the DDR controller.

These utilities are required before
initializing the DDR subsystem.

Change-Id: I48cc984f73fca5cde1b81e9075488fd5bed420d6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(flexspi): add 128Mbytes flash info

Those 4 nor flash have the same geometry:
Micron MT25QU01GBBB
GigaDevice GD55LB01GF
Macronix MX66U1G45G
Winbond W25Q01NW

Signed-off-by: Vincent Jardi

feat(flexspi): add 128Mbytes flash info

Those 4 nor flash have the same geometry:
Micron MT25QU01GBBB
GigaDevice GD55LB01GF
Macronix MX66U1G45G
Winbond W25Q01NW

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Change-Id: Iff74461ef3b252fc0f07745317d9860bd42c1ba1

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Merge changes Iea4c11de,Icae1fb08 into integration

* changes:
fix(lx2160): add DDRC missing DIMMs
fix(nxp): driver crypto caam

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: V

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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fix(nxp): imx_trdc.h header guard

The header guard define is IMX_XRDC_H where everything
else is IMX_TRDC_H, gcc-15 complains about this so
update the define to what it should be.

Fixes: 293529100

fix(nxp): imx_trdc.h header guard

The header guard define is IMX_XRDC_H where everything
else is IMX_TRDC_H, gcc-15 complains about this so
update the define to what it should be.

Fixes: 293529100 ("feat(imx93): add the trdc driver")
Change-Id: I4767dc4d1c26ebe95d417be724f5cb848f54a524
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

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feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

Change-Id: I23f468a3e5f7daa832c0841b55211a048284a7f0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add mor

feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.

Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add object

Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add objects needed for DDR clock
feat(nxp-clk): setup the DDR PLL
feat(nxp-clk): add MC_ME utilities
feat(nxp-clk): add partition reset utilities
feat(nxp-clk): add partitions objects

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refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e156457

refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A

feat(nxp-clk): add partitions objects

The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A partition is an island that may
contain multiple blocks, each of which corresponds to a peripheral or a
core and can, in most cases, be reset individually. This reset structure
results in better device availability. If a fault is detected in a
software reset domain, that domain can be reset separately without
impacting the operation of the rest of the chip.

Change-Id: Ie60dbe151309209e377aa71356dbbd6a4f376a8c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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