| a60aeae7 | 09-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR post training setup
Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.
The post training setup is now
feat(s32g274ardb): add DDR post training setup
Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.
The post training setup is now integrated into
the DDR initialization flow.
Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| 47f0a591 | 09-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add training for 1D and 2D
Extend the logic for executing the training stage
to include 1D and 2D PHY training.
Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by
feat(s32g274ardb): add training for 1D and 2D
Extend the logic for executing the training stage
to include 1D and 2D PHY training.
Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| a4efd428 | 01-Oct-2025 |
Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com> |
feat(s32g274ardb): add DDR register accessories
Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.
These
feat(s32g274ardb): add DDR register accessories
Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.
These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.
Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
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| cf6d73d4 | 28-Jan-2025 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): add clock modules for uSDHC
One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.
feat(nxp-clk): add clock modules for uSDHC
One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.
Change-Id: I23f468a3e5f7daa832c0841b55211a048284a7f0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| 63d536fe | 23-Jan-2025 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): add clock objects for CGM dividers
The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.
Change-Id: I
feat(nxp-clk): add clock objects for CGM dividers
The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.
Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| 4a2ca718 | 17-Sep-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): add objects needed for DDR clock
The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition
feat(nxp-clk): add objects needed for DDR clock
The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.
Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| e4462dae | 06-Aug-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz
feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| 5692f881 | 05-Aug-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(nxp-clk): add dependencies for the XBAR clock
Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.
Change-Id: Ib9cf82c0e40b76863637
feat(nxp-clk): add dependencies for the XBAR clock
Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.
Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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