xref: /rk3399_ARM-atf/lib/el3_runtime/aarch64/context.S (revision 8653352ad72e0f95dfd44f2ef9d1b2406dd8dca5) 
1/*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <context.h>
11#include <el3_common_macros.S>
12
13#if CTX_INCLUDE_FPREGS
14	.global	fpregs_context_save
15	.global	fpregs_context_restore
16#endif /* CTX_INCLUDE_FPREGS */
17
18#if ERRATA_SPECULATIVE_AT
19	.global save_and_update_ptw_el1_sys_regs
20#endif /* ERRATA_SPECULATIVE_AT */
21
22	.global	prepare_el3_entry
23	.global	restore_gp_pmcr_pauth_regs
24	.global	el3_exit
25
26/* ------------------------------------------------------------------
27 * The following function follows the aapcs_64 strictly to use
28 * x9-x17 (temporary caller-saved registers according to AArch64 PCS)
29 * to save floating point register context. It assumes that 'x0' is
30 * pointing to a 'fp_regs' structure where the register context will
31 * be saved.
32 *
33 * Access to VFP registers will trap if CPTR_EL3.TFP is set.
34 * However currently we don't use VFP registers nor set traps in
35 * Trusted Firmware, and assume it's cleared.
36 *
37 * TODO: Revisit when VFP is used in secure world
38 * ------------------------------------------------------------------
39 */
40#if CTX_INCLUDE_FPREGS
41func fpregs_context_save
42	stp	q0, q1, [x0, #CTX_FP_Q0]
43	stp	q2, q3, [x0, #CTX_FP_Q2]
44	stp	q4, q5, [x0, #CTX_FP_Q4]
45	stp	q6, q7, [x0, #CTX_FP_Q6]
46	stp	q8, q9, [x0, #CTX_FP_Q8]
47	stp	q10, q11, [x0, #CTX_FP_Q10]
48	stp	q12, q13, [x0, #CTX_FP_Q12]
49	stp	q14, q15, [x0, #CTX_FP_Q14]
50	stp	q16, q17, [x0, #CTX_FP_Q16]
51	stp	q18, q19, [x0, #CTX_FP_Q18]
52	stp	q20, q21, [x0, #CTX_FP_Q20]
53	stp	q22, q23, [x0, #CTX_FP_Q22]
54	stp	q24, q25, [x0, #CTX_FP_Q24]
55	stp	q26, q27, [x0, #CTX_FP_Q26]
56	stp	q28, q29, [x0, #CTX_FP_Q28]
57	stp	q30, q31, [x0, #CTX_FP_Q30]
58
59	mrs	x9, fpsr
60	str	x9, [x0, #CTX_FP_FPSR]
61
62	mrs	x10, fpcr
63	str	x10, [x0, #CTX_FP_FPCR]
64
65#if CTX_INCLUDE_AARCH32_REGS
66	mrs	x11, fpexc32_el2
67	str	x11, [x0, #CTX_FP_FPEXC32_EL2]
68#endif /* CTX_INCLUDE_AARCH32_REGS */
69	ret
70endfunc fpregs_context_save
71
72/* ------------------------------------------------------------------
73 * The following function follows the aapcs_64 strictly to use x9-x17
74 * (temporary caller-saved registers according to AArch64 PCS) to
75 * restore floating point register context. It assumes that 'x0' is
76 * pointing to a 'fp_regs' structure from where the register context
77 * will be restored.
78 *
79 * Access to VFP registers will trap if CPTR_EL3.TFP is set.
80 * However currently we don't use VFP registers nor set traps in
81 * Trusted Firmware, and assume it's cleared.
82 *
83 * TODO: Revisit when VFP is used in secure world
84 * ------------------------------------------------------------------
85 */
86func fpregs_context_restore
87	ldp	q0, q1, [x0, #CTX_FP_Q0]
88	ldp	q2, q3, [x0, #CTX_FP_Q2]
89	ldp	q4, q5, [x0, #CTX_FP_Q4]
90	ldp	q6, q7, [x0, #CTX_FP_Q6]
91	ldp	q8, q9, [x0, #CTX_FP_Q8]
92	ldp	q10, q11, [x0, #CTX_FP_Q10]
93	ldp	q12, q13, [x0, #CTX_FP_Q12]
94	ldp	q14, q15, [x0, #CTX_FP_Q14]
95	ldp	q16, q17, [x0, #CTX_FP_Q16]
96	ldp	q18, q19, [x0, #CTX_FP_Q18]
97	ldp	q20, q21, [x0, #CTX_FP_Q20]
98	ldp	q22, q23, [x0, #CTX_FP_Q22]
99	ldp	q24, q25, [x0, #CTX_FP_Q24]
100	ldp	q26, q27, [x0, #CTX_FP_Q26]
101	ldp	q28, q29, [x0, #CTX_FP_Q28]
102	ldp	q30, q31, [x0, #CTX_FP_Q30]
103
104	ldr	x9, [x0, #CTX_FP_FPSR]
105	msr	fpsr, x9
106
107	ldr	x10, [x0, #CTX_FP_FPCR]
108	msr	fpcr, x10
109
110#if CTX_INCLUDE_AARCH32_REGS
111	ldr	x11, [x0, #CTX_FP_FPEXC32_EL2]
112	msr	fpexc32_el2, x11
113#endif /* CTX_INCLUDE_AARCH32_REGS */
114
115	/*
116	 * No explict ISB required here as ERET to
117	 * switch to secure EL1 or non-secure world
118	 * covers it
119	 */
120
121	ret
122endfunc fpregs_context_restore
123#endif /* CTX_INCLUDE_FPREGS */
124
125	/*
126	 * Set SCR_EL3.EA bit to enable SErrors at EL3
127	 */
128	.macro enable_serror_at_el3
129	mrs     x8, scr_el3
130	orr     x8, x8, #SCR_EA_BIT
131	msr     scr_el3, x8
132	.endm
133
134	/*
135	 * Set the PSTATE bits not set when the exception was taken as
136	 * described in the AArch64.TakeException() pseudocode function
137	 * in ARM DDI 0487F.c page J1-7635 to a default value.
138	 */
139	.macro set_unset_pstate_bits
140	/*
141	 * If Data Independent Timing (DIT) functionality is implemented,
142	 * always enable DIT in EL3
143	 */
144#if ENABLE_FEAT_DIT
145#if ENABLE_FEAT_DIT >= 2
146	mrs	x8, id_aa64pfr0_el1
147	and	x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT)
148	cbz	x8, 1f
149#endif
150	mov     x8, #DIT_BIT
151	msr     DIT, x8
1521:
153#endif /* ENABLE_FEAT_DIT */
154	.endm /* set_unset_pstate_bits */
155
156/*-------------------------------------------------------------------------
157 * This macro checks the ENABLE_FEAT_MPAM state, performs ID register
158 * check to see if the platform supports MPAM extension and restores MPAM3
159 * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED.
160 *
161 * This is particularly more complicated because we can't check
162 * if the platform supports MPAM  by looking for status of a particular bit
163 * in the MDCR_EL3 or CPTR_EL3 register like other extensions.
164 * ------------------------------------------------------------------------
165 */
166
167	.macro	restore_mpam3_el3
168#if ENABLE_FEAT_MPAM
169#if ENABLE_FEAT_MPAM >= 2
170	mrs x8, id_aa64pfr0_el1
171	lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT)
172	and x8, x8, #(ID_AA64PFR0_MPAM_MASK)
173	mrs x7, id_aa64pfr1_el1
174	lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT)
175	and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK)
176	orr x7, x7, x8
177	cbz x7, no_mpam
178#endif
179	/* -----------------------------------------------------------
180	 * Restore MPAM3_EL3 register as per context state
181	 * Currently we only enable MPAM for NS world and trap to EL3
182	 * for MPAM access in lower ELs of Secure and Realm world
183	 * x9 holds address of the per_world context
184	 * -----------------------------------------------------------
185	 */
186
187	ldr	x17, [x9, #CTX_MPAM3_EL3]
188	msr	S3_6_C10_C5_0, x17 /* mpam3_el3 */
189
190no_mpam:
191#endif
192	.endm /* restore_mpam3_el3 */
193
194/* ------------------------------------------------------------------
195 * The following macro is used to save and restore all the general
196 * purpose and ARMv8.3-PAuth (if enabled) registers.
197 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0)
198 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0
199 * needs not to be saved/restored during world switch.
200 *
201 * Ideally we would only save and restore the callee saved registers
202 * when a world switch occurs but that type of implementation is more
203 * complex. So currently we will always save and restore these
204 * registers on entry and exit of EL3.
205 * clobbers: x18
206 * ------------------------------------------------------------------
207 */
208	.macro save_gp_pmcr_pauth_regs
209	stp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
210	stp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
211	stp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
212	stp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
213	stp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
214	stp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
215	stp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
216	stp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
217	stp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
218	stp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
219	stp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
220	stp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
221	stp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
222	stp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
223	stp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
224	mrs	x18, sp_el0
225	str	x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
226
227	/* PMUv3 is presumed to be always present */
228	mrs	x9, pmcr_el0
229	str	x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
230	/* Disable cycle counter when event counting is prohibited */
231	orr	x9, x9, #PMCR_EL0_DP_BIT
232	msr	pmcr_el0, x9
233	isb
234#if CTX_INCLUDE_PAUTH_REGS
235	/* ----------------------------------------------------------
236 	 * Save the ARMv8.3-PAuth keys as they are not banked
237 	 * by exception level
238	 * ----------------------------------------------------------
239	 */
240	add	x19, sp, #CTX_PAUTH_REGS_OFFSET
241
242	mrs	x20, APIAKeyLo_EL1	/* x21:x20 = APIAKey */
243	mrs	x21, APIAKeyHi_EL1
244	mrs	x22, APIBKeyLo_EL1	/* x23:x22 = APIBKey */
245	mrs	x23, APIBKeyHi_EL1
246	mrs	x24, APDAKeyLo_EL1	/* x25:x24 = APDAKey */
247	mrs	x25, APDAKeyHi_EL1
248	mrs	x26, APDBKeyLo_EL1	/* x27:x26 = APDBKey */
249	mrs	x27, APDBKeyHi_EL1
250	mrs	x28, APGAKeyLo_EL1	/* x29:x28 = APGAKey */
251	mrs	x29, APGAKeyHi_EL1
252
253	stp	x20, x21, [x19, #CTX_PACIAKEY_LO]
254	stp	x22, x23, [x19, #CTX_PACIBKEY_LO]
255	stp	x24, x25, [x19, #CTX_PACDAKEY_LO]
256	stp	x26, x27, [x19, #CTX_PACDBKEY_LO]
257	stp	x28, x29, [x19, #CTX_PACGAKEY_LO]
258#endif /* CTX_INCLUDE_PAUTH_REGS */
259	.endm /* save_gp_pmcr_pauth_regs */
260
261/* -----------------------------------------------------------------
262 * This function saves the context and sets the PSTATE to a known
263 * state, preparing entry to el3.
264 * Save all the general purpose and ARMv8.3-PAuth (if enabled)
265 * registers.
266 * Then set any of the PSTATE bits that are not set by hardware
267 * according to the Aarch64.TakeException pseudocode in the Arm
268 * Architecture Reference Manual to a default value for EL3.
269 * clobbers: x17
270 * -----------------------------------------------------------------
271 */
272func prepare_el3_entry
273	save_gp_pmcr_pauth_regs
274	enable_serror_at_el3
275	/*
276	 * Set the PSTATE bits not described in the Aarch64.TakeException
277	 * pseudocode to their default values.
278	 */
279	set_unset_pstate_bits
280	ret
281endfunc prepare_el3_entry
282
283/* ------------------------------------------------------------------
284 * This function restores ARMv8.3-PAuth (if enabled) and all general
285 * purpose registers except x30 from the CPU context.
286 * x30 register must be explicitly restored by the caller.
287 * ------------------------------------------------------------------
288 */
289func restore_gp_pmcr_pauth_regs
290#if CTX_INCLUDE_PAUTH_REGS
291 	/* Restore the ARMv8.3 PAuth keys */
292	add	x10, sp, #CTX_PAUTH_REGS_OFFSET
293
294	ldp	x0, x1, [x10, #CTX_PACIAKEY_LO]	/* x1:x0 = APIAKey */
295	ldp	x2, x3, [x10, #CTX_PACIBKEY_LO]	/* x3:x2 = APIBKey */
296	ldp	x4, x5, [x10, #CTX_PACDAKEY_LO]	/* x5:x4 = APDAKey */
297	ldp	x6, x7, [x10, #CTX_PACDBKEY_LO]	/* x7:x6 = APDBKey */
298	ldp	x8, x9, [x10, #CTX_PACGAKEY_LO]	/* x9:x8 = APGAKey */
299
300	msr	APIAKeyLo_EL1, x0
301	msr	APIAKeyHi_EL1, x1
302	msr	APIBKeyLo_EL1, x2
303	msr	APIBKeyHi_EL1, x3
304	msr	APDAKeyLo_EL1, x4
305	msr	APDAKeyHi_EL1, x5
306	msr	APDBKeyLo_EL1, x6
307	msr	APDBKeyHi_EL1, x7
308	msr	APGAKeyLo_EL1, x8
309	msr	APGAKeyHi_EL1, x9
310#endif /* CTX_INCLUDE_PAUTH_REGS */
311
312	/* PMUv3 is presumed to be always present */
313	ldr	x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
314	msr	pmcr_el0, x0
315	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
316	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
317	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
318	ldp	x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
319	ldp	x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
320	ldp	x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
321	ldp	x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
322	ldp	x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
323	ldp	x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
324	ldp	x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
325	ldp	x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
326	ldp	x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
327	ldp	x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
328	ldp	x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
329	ldr	x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
330	msr	sp_el0, x28
331	ldp	x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
332	ret
333endfunc restore_gp_pmcr_pauth_regs
334
335#if ERRATA_SPECULATIVE_AT
336/* --------------------------------------------------------------------
337 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1
338 * registers and update EL1 registers to disable stage1 and stage2
339 * page table walk.
340 * --------------------------------------------------------------------
341 */
342func save_and_update_ptw_el1_sys_regs
343	/* ----------------------------------------------------------
344	 * Save only sctlr_el1 and tcr_el1 registers
345	 * ----------------------------------------------------------
346	 */
347	mrs	x29, sctlr_el1
348	str	x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)]
349	mrs	x29, tcr_el1
350	str	x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)]
351
352	/* ------------------------------------------------------------
353	 * Must follow below order in order to disable page table
354	 * walk for lower ELs (EL1 and EL0). First step ensures that
355	 * page table walk is disabled for stage1 and second step
356	 * ensures that page table walker should use TCR_EL1.EPDx
357	 * bits to perform address translation. ISB ensures that CPU
358	 * does these 2 steps in order.
359	 *
360	 * 1. Update TCR_EL1.EPDx bits to disable page table walk by
361	 *    stage1.
362	 * 2. Enable MMU bit to avoid identity mapping via stage2
363	 *    and force TCR_EL1.EPDx to be used by the page table
364	 *    walker.
365	 * ------------------------------------------------------------
366	 */
367	orr	x29, x29, #(TCR_EPD0_BIT)
368	orr	x29, x29, #(TCR_EPD1_BIT)
369	msr	tcr_el1, x29
370	isb
371	mrs	x29, sctlr_el1
372	orr	x29, x29, #SCTLR_M_BIT
373	msr	sctlr_el1, x29
374	isb
375	ret
376endfunc save_and_update_ptw_el1_sys_regs
377
378#endif /* ERRATA_SPECULATIVE_AT */
379
380/* -----------------------------------------------------------------
381* The below macro returns the address of the per_world context for
382* the security state, retrieved through "get_security_state" macro.
383* The per_world context address is returned in the register argument.
384* Clobbers: x9, x10
385* ------------------------------------------------------------------
386*/
387
388.macro get_per_world_context _reg:req
389	ldr 	x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
390	get_security_state x9, x10
391	mov_imm	x10, (CTX_PERWORLD_EL3STATE_END - CTX_CPTR_EL3)
392	mul	x9, x9, x10
393	adrp	x10, per_world_context
394	add	x10, x10, :lo12:per_world_context
395	add	x9, x9, x10
396	mov 	\_reg, x9
397.endm
398
399/* ------------------------------------------------------------------
400 * This routine assumes that the SP_EL3 is pointing to a valid
401 * context structure from where the gp regs and other special
402 * registers can be retrieved.
403 * ------------------------------------------------------------------
404 */
405func el3_exit
406#if ENABLE_ASSERTIONS
407	/* el3_exit assumes SP_EL0 on entry */
408	mrs	x17, spsel
409	cmp	x17, #MODE_SP_EL0
410	ASM_ASSERT(eq)
411#endif /* ENABLE_ASSERTIONS */
412
413	/* ----------------------------------------------------------
414	 * Save the current SP_EL0 i.e. the EL3 runtime stack which
415	 * will be used for handling the next SMC.
416	 * Then switch to SP_EL3.
417	 * ----------------------------------------------------------
418	 */
419	mov	x17, sp
420	msr	spsel, #MODE_SP_ELX
421	str	x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
422
423	/* ----------------------------------------------------------
424	 * Restore CPTR_EL3.
425	 * ZCR is only restored if SVE is supported and enabled.
426	 * Synchronization is required before zcr_el3 is addressed.
427	 * ----------------------------------------------------------
428	 */
429
430	/* The address of the per_world context is stored in x9 */
431	get_per_world_context x9
432
433	ldp	x19, x20, [x9, #CTX_CPTR_EL3]
434	msr	cptr_el3, x19
435
436#if IMAGE_BL31
437	ands	x19, x19, #CPTR_EZ_BIT
438	beq	sve_not_enabled
439
440	isb
441	msr	S3_6_C1_C2_0, x20 /* zcr_el3 */
442sve_not_enabled:
443
444	restore_mpam3_el3
445
446#endif /* IMAGE_BL31 */
447
448#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
449	/* ----------------------------------------------------------
450	 * Restore mitigation state as it was on entry to EL3
451	 * ----------------------------------------------------------
452	 */
453	ldr	x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
454	cbz	x17, 1f
455	blr	x17
4561:
457#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */
458
459#if IMAGE_BL31
460	synchronize_errors
461#endif /* IMAGE_BL31 */
462
463	/* --------------------------------------------------------------
464	 * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
465	 * --------------------------------------------------------------
466	 */
467	ldp	x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
468	ldr	x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
469	ldr	x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3]
470	msr	spsr_el3, x16
471	msr	elr_el3, x17
472	msr	scr_el3, x18
473	msr	mdcr_el3, x19
474
475	restore_ptw_el1_sys_regs
476
477	/* ----------------------------------------------------------
478	 * Restore general purpose (including x30), PMCR_EL0 and
479	 * ARMv8.3-PAuth registers.
480	 * Exit EL3 via ERET to a lower exception level.
481 	 * ----------------------------------------------------------
482 	 */
483	bl	restore_gp_pmcr_pauth_regs
484	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
485
486#ifdef IMAGE_BL31
487	/* Clear the EL3 flag as we are exiting el3 */
488	str	xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG]
489#endif /* IMAGE_BL31 */
490
491	exception_return
492
493endfunc el3_exit
494