1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <errno.h> 7 #include <common/debug.h> 8 #include <drivers/clk.h> 9 #include <lib/mmio.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <s32cc-clk-ids.h> 12 #include <s32cc-clk-modules.h> 13 #include <s32cc-clk-regs.h> 14 #include <s32cc-clk-utils.h> 15 #include <s32cc-mc-me.h> 16 17 #define MAX_STACK_DEPTH (40U) 18 19 /* This is used for floating-point precision calculations. */ 20 #define FP_PRECISION (100000000UL) 21 22 struct s32cc_clk_drv { 23 uintptr_t fxosc_base; 24 uintptr_t armpll_base; 25 uintptr_t periphpll_base; 26 uintptr_t armdfs_base; 27 uintptr_t periphdfs_base; 28 uintptr_t cgm0_base; 29 uintptr_t cgm1_base; 30 uintptr_t cgm5_base; 31 uintptr_t ddrpll_base; 32 uintptr_t mc_me; 33 uintptr_t mc_rgm; 34 uintptr_t rdc; 35 }; 36 37 static int set_module_rate(const struct s32cc_clk_obj *module, 38 unsigned long rate, unsigned long *orate, 39 unsigned int *depth); 40 static int get_module_rate(const struct s32cc_clk_obj *module, 41 const struct s32cc_clk_drv *drv, 42 unsigned long *rate, 43 unsigned int depth); 44 45 static int update_stack_depth(unsigned int *depth) 46 { 47 if (*depth == 0U) { 48 return -ENOMEM; 49 } 50 51 (*depth)--; 52 return 0; 53 } 54 55 static struct s32cc_clk_drv *get_drv(void) 56 { 57 static struct s32cc_clk_drv driver = { 58 .fxosc_base = FXOSC_BASE_ADDR, 59 .armpll_base = ARMPLL_BASE_ADDR, 60 .periphpll_base = PERIPHPLL_BASE_ADDR, 61 .armdfs_base = ARM_DFS_BASE_ADDR, 62 .periphdfs_base = PERIPH_DFS_BASE_ADDR, 63 .cgm0_base = CGM0_BASE_ADDR, 64 .cgm1_base = CGM1_BASE_ADDR, 65 .cgm5_base = MC_CGM5_BASE_ADDR, 66 .ddrpll_base = DDRPLL_BASE_ADDR, 67 .mc_me = MC_ME_BASE_ADDR, 68 .mc_rgm = MC_RGM_BASE_ADDR, 69 .rdc = RDC_BASE_ADDR, 70 }; 71 72 return &driver; 73 } 74 75 static int enable_module(struct s32cc_clk_obj *module, 76 const struct s32cc_clk_drv *drv, 77 unsigned int depth); 78 79 static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module) 80 { 81 const struct s32cc_clk *clk = s32cc_obj2clk(module); 82 83 if (clk->module != NULL) { 84 return clk->module; 85 } 86 87 if (clk->pclock != NULL) { 88 return &clk->pclock->desc; 89 } 90 91 return NULL; 92 } 93 94 static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv, 95 uintptr_t *base) 96 { 97 int ret = 0; 98 99 switch (id) { 100 case S32CC_FXOSC: 101 *base = drv->fxosc_base; 102 break; 103 case S32CC_ARM_PLL: 104 *base = drv->armpll_base; 105 break; 106 case S32CC_PERIPH_PLL: 107 *base = drv->periphpll_base; 108 break; 109 case S32CC_DDR_PLL: 110 *base = drv->ddrpll_base; 111 break; 112 case S32CC_ARM_DFS: 113 *base = drv->armdfs_base; 114 break; 115 case S32CC_PERIPH_DFS: 116 *base = drv->periphdfs_base; 117 break; 118 case S32CC_CGM0: 119 *base = drv->cgm0_base; 120 break; 121 case S32CC_CGM1: 122 *base = drv->cgm1_base; 123 break; 124 case S32CC_CGM5: 125 *base = drv->cgm5_base; 126 break; 127 case S32CC_FIRC: 128 break; 129 case S32CC_SIRC: 130 break; 131 default: 132 ret = -EINVAL; 133 break; 134 } 135 136 if (ret != 0) { 137 ERROR("Unknown clock source id: %u\n", id); 138 } 139 140 return ret; 141 } 142 143 static void enable_fxosc(const struct s32cc_clk_drv *drv) 144 { 145 uintptr_t fxosc_base = drv->fxosc_base; 146 uint32_t ctrl; 147 148 ctrl = mmio_read_32(FXOSC_CTRL(fxosc_base)); 149 if ((ctrl & FXOSC_CTRL_OSCON) != U(0)) { 150 return; 151 } 152 153 ctrl = FXOSC_CTRL_COMP_EN; 154 ctrl &= ~FXOSC_CTRL_OSC_BYP; 155 ctrl |= FXOSC_CTRL_EOCV(0x1); 156 ctrl |= FXOSC_CTRL_GM_SEL(0x7); 157 mmio_write_32(FXOSC_CTRL(fxosc_base), ctrl); 158 159 /* Switch ON the crystal oscillator. */ 160 mmio_setbits_32(FXOSC_CTRL(fxosc_base), FXOSC_CTRL_OSCON); 161 162 /* Wait until the clock is stable. */ 163 while ((mmio_read_32(FXOSC_STAT(fxosc_base)) & FXOSC_STAT_OSC_STAT) == U(0)) { 164 } 165 } 166 167 static int enable_osc(struct s32cc_clk_obj *module, 168 const struct s32cc_clk_drv *drv, 169 unsigned int depth) 170 { 171 const struct s32cc_osc *osc = s32cc_obj2osc(module); 172 unsigned int ldepth = depth; 173 int ret = 0; 174 175 ret = update_stack_depth(&ldepth); 176 if (ret != 0) { 177 return ret; 178 } 179 180 switch (osc->source) { 181 case S32CC_FXOSC: 182 enable_fxosc(drv); 183 break; 184 /* FIRC and SIRC oscillators are enabled by default */ 185 case S32CC_FIRC: 186 break; 187 case S32CC_SIRC: 188 break; 189 default: 190 ERROR("Invalid oscillator %d\n", osc->source); 191 ret = -EINVAL; 192 break; 193 }; 194 195 return ret; 196 } 197 198 static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module) 199 { 200 const struct s32cc_pll *pll = s32cc_obj2pll(module); 201 202 if (pll->source == NULL) { 203 ERROR("Failed to identify PLL's parent\n"); 204 } 205 206 return pll->source; 207 } 208 209 static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq, 210 uint32_t *mfi, uint32_t *mfn) 211 212 { 213 unsigned long vco; 214 unsigned long mfn64; 215 216 /* FRAC-N mode */ 217 *mfi = (uint32_t)(pll_vco / ref_freq); 218 219 /* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */ 220 mfn64 = pll_vco % ref_freq; 221 mfn64 *= FP_PRECISION; 222 mfn64 /= ref_freq; 223 mfn64 *= 18432UL; 224 mfn64 /= FP_PRECISION; 225 226 if (mfn64 > UINT32_MAX) { 227 return -EINVAL; 228 } 229 230 *mfn = (uint32_t)mfn64; 231 232 vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL; 233 vco += (unsigned long)*mfi * FP_PRECISION; 234 vco *= ref_freq; 235 vco /= FP_PRECISION; 236 237 if (vco != pll_vco) { 238 ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n", 239 pll_vco, vco); 240 return -EINVAL; 241 } 242 243 return 0; 244 } 245 246 static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll) 247 { 248 const struct s32cc_clk_obj *source = pll->source; 249 const struct s32cc_clk *clk; 250 251 if (source == NULL) { 252 ERROR("Failed to identify PLL's parent\n"); 253 return NULL; 254 } 255 256 if (source->type != s32cc_clk_t) { 257 ERROR("The parent of the PLL isn't a clock\n"); 258 return NULL; 259 } 260 261 clk = s32cc_obj2clk(source); 262 263 if (clk->module == NULL) { 264 ERROR("The clock isn't connected to a module\n"); 265 return NULL; 266 } 267 268 source = clk->module; 269 270 if ((source->type != s32cc_clkmux_t) && 271 (source->type != s32cc_shared_clkmux_t)) { 272 ERROR("The parent of the PLL isn't a MUX\n"); 273 return NULL; 274 } 275 276 return s32cc_obj2clkmux(source); 277 } 278 279 static void disable_odiv(uintptr_t pll_addr, uint32_t div_index) 280 { 281 mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 282 } 283 284 static void enable_odiv(uintptr_t pll_addr, uint32_t div_index) 285 { 286 mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 287 } 288 289 static void enable_odivs(uintptr_t pll_addr, uint32_t ndivs, uint32_t mask) 290 { 291 uint32_t i; 292 293 for (i = 0; i < ndivs; i++) { 294 if ((mask & BIT_32(i)) != 0U) { 295 enable_odiv(pll_addr, i); 296 } 297 } 298 } 299 300 static int adjust_odiv_settings(const struct s32cc_pll *pll, uintptr_t pll_addr, 301 uint32_t odivs_mask, unsigned long old_vco) 302 { 303 uint64_t old_odiv_freq, odiv_freq; 304 uint32_t i, pllodiv, pdiv; 305 int ret = 0; 306 307 if (old_vco == 0UL) { 308 return 0; 309 } 310 311 for (i = 0; i < pll->ndividers; i++) { 312 if ((odivs_mask & BIT_32(i)) == 0U) { 313 continue; 314 } 315 316 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, i)); 317 318 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 319 320 old_odiv_freq = ((old_vco * FP_PRECISION) / (pdiv + 1U)) / FP_PRECISION; 321 pdiv = (uint32_t)(pll->vco_freq * FP_PRECISION / old_odiv_freq / FP_PRECISION); 322 323 odiv_freq = pll->vco_freq * FP_PRECISION / pdiv / FP_PRECISION; 324 325 if (old_odiv_freq != odiv_freq) { 326 ERROR("Failed to adjust ODIV %" PRIu32 " to match previous frequency\n", 327 i); 328 } 329 330 pllodiv = PLLDIG_PLLODIV_DIV_SET(pdiv - 1U); 331 mmio_write_32(PLLDIG_PLLODIV(pll_addr, i), pllodiv); 332 } 333 334 return ret; 335 } 336 337 static uint32_t get_enabled_odivs(uintptr_t pll_addr, uint32_t ndivs) 338 { 339 uint32_t mask = 0; 340 uint32_t pllodiv; 341 uint32_t i; 342 343 for (i = 0; i < ndivs; i++) { 344 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, i)); 345 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 346 mask |= BIT_32(i); 347 } 348 } 349 350 return mask; 351 } 352 353 static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs) 354 { 355 uint32_t i; 356 357 for (i = 0; i < ndivs; i++) { 358 disable_odiv(pll_addr, i); 359 } 360 } 361 362 static void enable_pll_hw(uintptr_t pll_addr) 363 { 364 /* Enable the PLL. */ 365 mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0); 366 367 /* Poll until PLL acquires lock. */ 368 while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) { 369 } 370 } 371 372 static void disable_pll_hw(uintptr_t pll_addr) 373 { 374 mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD); 375 } 376 377 static bool is_pll_enabled(uintptr_t pll_base) 378 { 379 uint32_t pllcr, pllsr; 380 381 pllcr = mmio_read_32(PLLDIG_PLLCR(pll_base)); 382 pllsr = mmio_read_32(PLLDIG_PLLSR(pll_base)); 383 384 /* Enabled and locked PLL */ 385 if ((pllcr & PLLDIG_PLLCR_PLLPD) != 0U) { 386 return false; 387 } 388 389 if ((pllsr & PLLDIG_PLLSR_LOCK) == 0U) { 390 return false; 391 } 392 393 return true; 394 } 395 396 static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr, 397 const struct s32cc_clk_drv *drv, uint32_t sclk_id, 398 unsigned long sclk_freq, unsigned int depth) 399 { 400 uint32_t rdiv = 1, mfi, mfn; 401 unsigned long old_vco = 0UL; 402 unsigned int ldepth = depth; 403 uint32_t odivs_mask; 404 int ret; 405 406 ret = update_stack_depth(&ldepth); 407 if (ret != 0) { 408 return ret; 409 } 410 411 ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn); 412 if (ret != 0) { 413 return -EINVAL; 414 } 415 416 odivs_mask = get_enabled_odivs(pll_addr, pll->ndividers); 417 418 if (is_pll_enabled(pll_addr)) { 419 ret = get_module_rate(&pll->desc, drv, &old_vco, ldepth); 420 if (ret != 0) { 421 return ret; 422 } 423 } 424 425 /* Disable ODIVs*/ 426 disable_odivs(pll_addr, pll->ndividers); 427 428 /* Disable PLL */ 429 disable_pll_hw(pll_addr); 430 431 /* Program PLLCLKMUX */ 432 mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id); 433 434 /* Program VCO */ 435 mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr), 436 PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK, 437 PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi)); 438 439 mmio_write_32(PLLDIG_PLLFD(pll_addr), 440 PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN); 441 442 ret = adjust_odiv_settings(pll, pll_addr, odivs_mask, old_vco); 443 if (ret != 0) { 444 return ret; 445 } 446 447 enable_pll_hw(pll_addr); 448 449 /* Enable out dividers */ 450 enable_odivs(pll_addr, pll->ndividers, odivs_mask); 451 452 return ret; 453 } 454 455 static int enable_pll(struct s32cc_clk_obj *module, 456 const struct s32cc_clk_drv *drv, 457 unsigned int depth) 458 { 459 const struct s32cc_pll *pll = s32cc_obj2pll(module); 460 unsigned int clk_src, ldepth = depth; 461 unsigned long sclk_freq, pll_vco; 462 const struct s32cc_clkmux *mux; 463 uintptr_t pll_addr = UL(0x0); 464 bool pll_enabled; 465 uint32_t sclk_id; 466 int ret; 467 468 ret = update_stack_depth(&ldepth); 469 if (ret != 0) { 470 return ret; 471 } 472 473 mux = get_pll_mux(pll); 474 if (mux == NULL) { 475 return -EINVAL; 476 } 477 478 if (pll->instance != mux->module) { 479 ERROR("MUX type is not in sync with PLL ID\n"); 480 return -EINVAL; 481 } 482 483 ret = get_base_addr(pll->instance, drv, &pll_addr); 484 if (ret != 0) { 485 ERROR("Failed to detect PLL instance\n"); 486 return ret; 487 } 488 489 switch (mux->source_id) { 490 case S32CC_CLK_FIRC: 491 sclk_freq = 48U * MHZ; 492 sclk_id = 0; 493 break; 494 case S32CC_CLK_FXOSC: 495 sclk_freq = 40U * MHZ; 496 sclk_id = 1; 497 break; 498 default: 499 ERROR("Invalid source selection for PLL 0x%lx\n", 500 pll_addr); 501 return -EINVAL; 502 }; 503 504 ret = get_module_rate(&pll->desc, drv, &pll_vco, depth); 505 if (ret != 0) { 506 return ret; 507 } 508 509 pll_enabled = is_pll_enabled(pll_addr); 510 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 511 512 if ((clk_src == sclk_id) && pll_enabled && 513 (pll_vco == pll->vco_freq)) { 514 return 0; 515 } 516 517 return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq, ldepth); 518 } 519 520 static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv) 521 { 522 const struct s32cc_clk_obj *parent; 523 524 parent = pdiv->parent; 525 if (parent == NULL) { 526 ERROR("Failed to identify PLL divider's parent\n"); 527 return NULL; 528 } 529 530 if (parent->type != s32cc_pll_t) { 531 ERROR("The parent of the divider is not a PLL instance\n"); 532 return NULL; 533 } 534 535 return s32cc_obj2pll(parent); 536 } 537 538 static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc) 539 { 540 uint32_t pllodiv; 541 uint32_t pdiv; 542 543 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index)); 544 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 545 546 if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) { 547 return; 548 } 549 550 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 551 disable_odiv(pll_addr, div_index); 552 } 553 554 pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U); 555 mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv); 556 557 enable_odiv(pll_addr, div_index); 558 } 559 560 static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module) 561 { 562 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 563 564 if (pdiv->parent == NULL) { 565 ERROR("Failed to identify PLL DIV's parent\n"); 566 } 567 568 return pdiv->parent; 569 } 570 571 static int enable_pll_div(struct s32cc_clk_obj *module, 572 const struct s32cc_clk_drv *drv, 573 unsigned int depth) 574 { 575 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 576 uintptr_t pll_addr = 0x0ULL; 577 unsigned int ldepth = depth; 578 const struct s32cc_pll *pll; 579 unsigned long pll_vco; 580 uint32_t dc; 581 int ret; 582 583 ret = update_stack_depth(&ldepth); 584 if (ret != 0) { 585 return ret; 586 } 587 588 pll = get_div_pll(pdiv); 589 if (pll == NULL) { 590 ERROR("The parent of the PLL DIV is invalid\n"); 591 return 0; 592 } 593 594 ret = get_base_addr(pll->instance, drv, &pll_addr); 595 if (ret != 0) { 596 ERROR("Failed to detect PLL instance\n"); 597 return -EINVAL; 598 } 599 600 ret = get_module_rate(&pll->desc, drv, &pll_vco, ldepth); 601 if (ret != 0) { 602 ERROR("Failed to enable the PLL due to unknown rate for 0x%" PRIxPTR "\n", 603 pll_addr); 604 return ret; 605 } 606 607 dc = (uint32_t)(pll_vco / pdiv->freq); 608 609 config_pll_out_div(pll_addr, pdiv->index, dc); 610 611 return 0; 612 } 613 614 static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source, 615 bool safe_clk) 616 { 617 uint32_t css, csc; 618 619 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 620 621 /* Already configured */ 622 if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) && 623 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 624 ((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) { 625 return 0; 626 } 627 628 /* Ongoing clock switch? */ 629 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 630 MC_CGM_MUXn_CSS_SWIP) != 0U) { 631 } 632 633 csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)); 634 635 /* Clear previous source. */ 636 csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK); 637 638 if (!safe_clk) { 639 /* Select the clock source and trigger the clock switch. */ 640 csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW; 641 } else { 642 /* Switch to safe clock */ 643 csc |= MC_CGM_MUXn_CSC_SAFE_SW; 644 } 645 646 mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc); 647 648 /* Wait for configuration bit to auto-clear. */ 649 while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) & 650 MC_CGM_MUXn_CSC_CLK_SW) != 0U) { 651 } 652 653 /* Is the clock switch completed? */ 654 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 655 MC_CGM_MUXn_CSS_SWIP) != 0U) { 656 } 657 658 /* 659 * Check if the switch succeeded. 660 * Check switch trigger cause and the source. 661 */ 662 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 663 if (!safe_clk) { 664 if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 665 (MC_CGM_MUXn_CSS_SELSTAT(css) == source)) { 666 return 0; 667 } 668 669 ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n", 670 mux, source, cgm_addr); 671 } else { 672 if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) || 673 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) && 674 ((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) { 675 return 0; 676 } 677 678 ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n", 679 mux, cgm_addr); 680 } 681 682 return -EINVAL; 683 } 684 685 static int enable_cgm_mux(const struct s32cc_clkmux *mux, 686 const struct s32cc_clk_drv *drv) 687 { 688 uintptr_t cgm_addr = UL(0x0); 689 uint32_t mux_hw_clk; 690 int ret; 691 692 ret = get_base_addr(mux->module, drv, &cgm_addr); 693 if (ret != 0) { 694 return ret; 695 } 696 697 mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id); 698 699 return cgm_mux_clk_config(cgm_addr, mux->index, 700 mux_hw_clk, false); 701 } 702 703 static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module) 704 { 705 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 706 struct s32cc_clk *clk; 707 708 if (mux == NULL) { 709 return NULL; 710 } 711 712 clk = s32cc_get_arch_clk(mux->source_id); 713 if (clk == NULL) { 714 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 715 mux->source_id, mux->index); 716 return NULL; 717 } 718 719 return &clk->desc; 720 } 721 722 static int enable_mux(struct s32cc_clk_obj *module, 723 const struct s32cc_clk_drv *drv, 724 unsigned int depth) 725 { 726 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 727 unsigned int ldepth = depth; 728 const struct s32cc_clk *clk; 729 int ret = 0; 730 731 ret = update_stack_depth(&ldepth); 732 if (ret != 0) { 733 return ret; 734 } 735 736 if (mux == NULL) { 737 return -EINVAL; 738 } 739 740 clk = s32cc_get_arch_clk(mux->source_id); 741 if (clk == NULL) { 742 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 743 mux->source_id, mux->index); 744 return -EINVAL; 745 } 746 747 switch (mux->module) { 748 /* PLL mux will be enabled by PLL setup */ 749 case S32CC_ARM_PLL: 750 case S32CC_PERIPH_PLL: 751 case S32CC_DDR_PLL: 752 break; 753 case S32CC_CGM1: 754 ret = enable_cgm_mux(mux, drv); 755 break; 756 case S32CC_CGM0: 757 ret = enable_cgm_mux(mux, drv); 758 break; 759 case S32CC_CGM5: 760 ret = enable_cgm_mux(mux, drv); 761 break; 762 default: 763 ERROR("Unknown mux parent type: %d\n", mux->module); 764 ret = -EINVAL; 765 break; 766 }; 767 768 return ret; 769 } 770 771 static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module) 772 { 773 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 774 775 if (dfs->parent == NULL) { 776 ERROR("Failed to identify DFS's parent\n"); 777 } 778 779 return dfs->parent; 780 } 781 782 static int enable_dfs(struct s32cc_clk_obj *module, 783 const struct s32cc_clk_drv *drv, 784 unsigned int depth) 785 { 786 unsigned int ldepth = depth; 787 int ret = 0; 788 789 ret = update_stack_depth(&ldepth); 790 if (ret != 0) { 791 return ret; 792 } 793 794 return 0; 795 } 796 797 static int get_dfs_freq(const struct s32cc_clk_obj *module, 798 const struct s32cc_clk_drv *drv, 799 unsigned long *rate, unsigned int depth) 800 { 801 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 802 unsigned int ldepth = depth; 803 uintptr_t dfs_addr; 804 int ret; 805 806 ret = update_stack_depth(&ldepth); 807 if (ret != 0) { 808 return ret; 809 } 810 811 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 812 if (ret != 0) { 813 ERROR("Failed to detect the DFS instance\n"); 814 return ret; 815 } 816 817 return get_module_rate(dfs->parent, drv, rate, ldepth); 818 } 819 820 static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div) 821 { 822 const struct s32cc_clk_obj *parent = dfs_div->parent; 823 824 if (parent->type != s32cc_dfs_t) { 825 ERROR("DFS DIV doesn't have a DFS as parent\n"); 826 return NULL; 827 } 828 829 return s32cc_obj2dfs(parent); 830 } 831 832 static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div, 833 uint32_t *mfi, uint32_t *mfn) 834 { 835 uint64_t factor64, tmp64, ofreq; 836 uint32_t factor32; 837 838 unsigned long in = dfs_freq; 839 unsigned long out = dfs_div->freq; 840 841 /** 842 * factor = (IN / OUT) / 2 843 * MFI = integer(factor) 844 * MFN = (factor - MFI) * 36 845 */ 846 factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL; 847 tmp64 = factor64 / FP_PRECISION; 848 if (tmp64 > UINT32_MAX) { 849 return -EINVAL; 850 } 851 852 factor32 = (uint32_t)tmp64; 853 *mfi = factor32; 854 855 tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION; 856 if (tmp64 > UINT32_MAX) { 857 return -EINVAL; 858 } 859 860 *mfn = (uint32_t)tmp64; 861 862 /* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */ 863 factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL; 864 factor64 += ((uint64_t)*mfi) * FP_PRECISION; 865 factor64 *= 2ULL; 866 ofreq = (((uint64_t)in) * FP_PRECISION) / factor64; 867 868 if (ofreq != dfs_div->freq) { 869 ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n", 870 dfs_div->freq); 871 ERROR("Nearest freq = %" PRIx64 "\n", ofreq); 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static int init_dfs_port(uintptr_t dfs_addr, uint32_t port, 879 uint32_t mfi, uint32_t mfn) 880 { 881 uint32_t portsr, portolsr; 882 uint32_t mask, old_mfi, old_mfn; 883 uint32_t dvport; 884 bool init_dfs; 885 886 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port)); 887 888 old_mfi = DFS_DVPORTn_MFI(dvport); 889 old_mfn = DFS_DVPORTn_MFN(dvport); 890 891 portsr = mmio_read_32(DFS_PORTSR(dfs_addr)); 892 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 893 894 /* Skip configuration if it's not needed */ 895 if (((portsr & BIT_32(port)) != 0U) && 896 ((portolsr & BIT_32(port)) == 0U) && 897 (mfi == old_mfi) && (mfn == old_mfn)) { 898 return 0; 899 } 900 901 init_dfs = (portsr == 0U); 902 903 if (init_dfs) { 904 mask = DFS_PORTRESET_MASK; 905 } else { 906 mask = DFS_PORTRESET_SET(BIT_32(port)); 907 } 908 909 mmio_write_32(DFS_PORTOLSR(dfs_addr), mask); 910 mmio_write_32(DFS_PORTRESET(dfs_addr), mask); 911 912 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) { 913 } 914 915 if (init_dfs) { 916 mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 917 } 918 919 mmio_write_32(DFS_DVPORTn(dfs_addr, port), 920 DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn)); 921 922 if (init_dfs) { 923 /* DFS clk enable programming */ 924 mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 925 } 926 927 mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port)); 928 929 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) { 930 } 931 932 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 933 if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) { 934 ERROR("Failed to lock DFS divider\n"); 935 return -EINVAL; 936 } 937 938 return 0; 939 } 940 941 static struct s32cc_clk_obj * 942 get_dfs_div_parent(const struct s32cc_clk_obj *module) 943 { 944 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 945 946 if (dfs_div->parent == NULL) { 947 ERROR("Failed to identify DFS divider's parent\n"); 948 } 949 950 return dfs_div->parent; 951 } 952 953 static int enable_dfs_div(struct s32cc_clk_obj *module, 954 const struct s32cc_clk_drv *drv, 955 unsigned int depth) 956 { 957 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 958 unsigned int ldepth = depth; 959 const struct s32cc_dfs *dfs; 960 uintptr_t dfs_addr = 0UL; 961 unsigned long dfs_freq; 962 uint32_t mfi, mfn; 963 int ret = 0; 964 965 ret = update_stack_depth(&ldepth); 966 if (ret != 0) { 967 return ret; 968 } 969 970 dfs = get_div_dfs(dfs_div); 971 if (dfs == NULL) { 972 return -EINVAL; 973 } 974 975 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 976 if ((ret != 0) || (dfs_addr == 0UL)) { 977 return -EINVAL; 978 } 979 980 ret = get_module_rate(&dfs->desc, drv, &dfs_freq, depth); 981 if (ret != 0) { 982 return ret; 983 } 984 985 ret = get_dfs_mfi_mfn(dfs_freq, dfs_div, &mfi, &mfn); 986 if (ret != 0) { 987 return -EINVAL; 988 } 989 990 return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn); 991 } 992 993 typedef int (*enable_clk_t)(struct s32cc_clk_obj *module, 994 const struct s32cc_clk_drv *drv, 995 unsigned int depth); 996 997 static int enable_part(struct s32cc_clk_obj *module, 998 const struct s32cc_clk_drv *drv, 999 unsigned int depth) 1000 { 1001 const struct s32cc_part *part = s32cc_obj2part(module); 1002 uint32_t part_no = part->partition_id; 1003 1004 if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) { 1005 return -EINVAL; 1006 } 1007 1008 return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no); 1009 } 1010 1011 static int enable_part_block(struct s32cc_clk_obj *module, 1012 const struct s32cc_clk_drv *drv, 1013 unsigned int depth) 1014 { 1015 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 1016 const struct s32cc_part *part = block->part; 1017 uint32_t part_no = part->partition_id; 1018 unsigned int ldepth = depth; 1019 uint32_t cofb; 1020 int ret; 1021 1022 ret = update_stack_depth(&ldepth); 1023 if (ret != 0) { 1024 return ret; 1025 } 1026 1027 if ((block->block >= s32cc_part_block0) && 1028 (block->block <= s32cc_part_block15)) { 1029 cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0; 1030 mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status); 1031 } else { 1032 ERROR("Unknown partition block type: %d\n", block->block); 1033 return -EINVAL; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static struct s32cc_clk_obj * 1040 get_part_block_parent(const struct s32cc_clk_obj *module) 1041 { 1042 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 1043 1044 return &block->part->desc; 1045 } 1046 1047 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1048 const struct s32cc_clk_drv *drv, 1049 unsigned int depth); 1050 1051 static int enable_part_block_link(struct s32cc_clk_obj *module, 1052 const struct s32cc_clk_drv *drv, 1053 unsigned int depth) 1054 { 1055 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 1056 struct s32cc_part_block *block = link->block; 1057 unsigned int ldepth = depth; 1058 int ret; 1059 1060 ret = update_stack_depth(&ldepth); 1061 if (ret != 0) { 1062 return ret; 1063 } 1064 1065 /* Move the enablement algorithm to partition tree */ 1066 return enable_module_with_refcount(&block->desc, drv, ldepth); 1067 } 1068 1069 static struct s32cc_clk_obj * 1070 get_part_block_link_parent(const struct s32cc_clk_obj *module) 1071 { 1072 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 1073 1074 return link->parent; 1075 } 1076 1077 static int get_part_block_link_freq(const struct s32cc_clk_obj *module, 1078 const struct s32cc_clk_drv *drv, 1079 unsigned long *rate, unsigned int depth) 1080 { 1081 const struct s32cc_part_block_link *block = s32cc_obj2partblocklink(module); 1082 unsigned int ldepth = depth; 1083 int ret; 1084 1085 ret = update_stack_depth(&ldepth); 1086 if (ret != 0) { 1087 return ret; 1088 } 1089 1090 return get_module_rate(block->parent, drv, rate, ldepth); 1091 } 1092 1093 static int no_enable(struct s32cc_clk_obj *module, 1094 const struct s32cc_clk_drv *drv, 1095 unsigned int depth) 1096 { 1097 return 0; 1098 } 1099 1100 static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod, 1101 const struct s32cc_clk_drv *drv, bool leaf_node, 1102 unsigned int depth) 1103 { 1104 unsigned int ldepth = depth; 1105 int ret = 0; 1106 1107 if (mod == NULL) { 1108 return 0; 1109 } 1110 1111 ret = update_stack_depth(&ldepth); 1112 if (ret != 0) { 1113 return ret; 1114 } 1115 1116 /* Refcount will be updated as part of the recursivity */ 1117 if (leaf_node) { 1118 return en_cb(mod, drv, ldepth); 1119 } 1120 1121 if (mod->refcount == 0U) { 1122 ret = en_cb(mod, drv, ldepth); 1123 } 1124 1125 if (ret == 0) { 1126 mod->refcount++; 1127 } 1128 1129 return ret; 1130 } 1131 1132 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module); 1133 1134 static int enable_module(struct s32cc_clk_obj *module, 1135 const struct s32cc_clk_drv *drv, 1136 unsigned int depth) 1137 { 1138 struct s32cc_clk_obj *parent = get_module_parent(module); 1139 static const enable_clk_t enable_clbs[12] = { 1140 [s32cc_clk_t] = no_enable, 1141 [s32cc_osc_t] = enable_osc, 1142 [s32cc_pll_t] = enable_pll, 1143 [s32cc_pll_out_div_t] = enable_pll_div, 1144 [s32cc_clkmux_t] = enable_mux, 1145 [s32cc_shared_clkmux_t] = enable_mux, 1146 [s32cc_dfs_t] = enable_dfs, 1147 [s32cc_dfs_div_t] = enable_dfs_div, 1148 [s32cc_part_t] = enable_part, 1149 [s32cc_part_block_t] = enable_part_block, 1150 [s32cc_part_block_link_t] = enable_part_block_link, 1151 }; 1152 unsigned int ldepth = depth; 1153 uint32_t index; 1154 int ret = 0; 1155 1156 ret = update_stack_depth(&ldepth); 1157 if (ret != 0) { 1158 return ret; 1159 } 1160 1161 if (drv == NULL) { 1162 return -EINVAL; 1163 } 1164 1165 index = (uint32_t)module->type; 1166 1167 if (index >= ARRAY_SIZE(enable_clbs)) { 1168 ERROR("Undefined module type: %d\n", module->type); 1169 return -EINVAL; 1170 } 1171 1172 if (enable_clbs[index] == NULL) { 1173 ERROR("Undefined callback for the clock type: %d\n", 1174 module->type); 1175 return -EINVAL; 1176 } 1177 1178 parent = get_module_parent(module); 1179 1180 ret = exec_cb_with_refcount(enable_module, parent, drv, 1181 false, ldepth); 1182 if (ret != 0) { 1183 return ret; 1184 } 1185 1186 ret = exec_cb_with_refcount(enable_clbs[index], module, drv, 1187 true, ldepth); 1188 if (ret != 0) { 1189 return ret; 1190 } 1191 1192 return ret; 1193 } 1194 1195 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1196 const struct s32cc_clk_drv *drv, 1197 unsigned int depth) 1198 { 1199 return exec_cb_with_refcount(enable_module, module, drv, false, depth); 1200 } 1201 1202 static int s32cc_clk_enable(unsigned long id) 1203 { 1204 const struct s32cc_clk_drv *drv = get_drv(); 1205 unsigned int depth = MAX_STACK_DEPTH; 1206 struct s32cc_clk *clk; 1207 1208 clk = s32cc_get_arch_clk(id); 1209 if (clk == NULL) { 1210 return -EINVAL; 1211 } 1212 1213 return enable_module_with_refcount(&clk->desc, drv, depth); 1214 } 1215 1216 static void s32cc_clk_disable(unsigned long id) 1217 { 1218 } 1219 1220 static bool s32cc_clk_is_enabled(unsigned long id) 1221 { 1222 return false; 1223 } 1224 1225 static int set_osc_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1226 unsigned long *orate, unsigned int *depth) 1227 { 1228 struct s32cc_osc *osc = s32cc_obj2osc(module); 1229 int ret; 1230 1231 ret = update_stack_depth(depth); 1232 if (ret != 0) { 1233 return ret; 1234 } 1235 1236 if ((osc->freq != 0UL) && (rate != osc->freq)) { 1237 ERROR("Already initialized oscillator. freq = %lu\n", 1238 osc->freq); 1239 return -EINVAL; 1240 } 1241 1242 osc->freq = rate; 1243 *orate = osc->freq; 1244 1245 return 0; 1246 } 1247 1248 static int get_osc_freq(const struct s32cc_clk_obj *module, 1249 const struct s32cc_clk_drv *drv, 1250 unsigned long *rate, unsigned int depth) 1251 { 1252 const struct s32cc_osc *osc = s32cc_obj2osc(module); 1253 unsigned int ldepth = depth; 1254 int ret; 1255 1256 ret = update_stack_depth(&ldepth); 1257 if (ret != 0) { 1258 return ret; 1259 } 1260 1261 if (osc->freq == 0UL) { 1262 ERROR("Uninitialized oscillator\n"); 1263 return -EINVAL; 1264 } 1265 1266 *rate = osc->freq; 1267 1268 return 0; 1269 } 1270 1271 static int set_clk_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1272 unsigned long *orate, unsigned int *depth) 1273 { 1274 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1275 int ret; 1276 1277 ret = update_stack_depth(depth); 1278 if (ret != 0) { 1279 return ret; 1280 } 1281 1282 if ((clk->min_freq != 0UL) && (clk->max_freq != 0UL) && 1283 ((rate < clk->min_freq) || (rate > clk->max_freq))) { 1284 ERROR("%lu frequency is out of the allowed range: [%lu:%lu]\n", 1285 rate, clk->min_freq, clk->max_freq); 1286 return -EINVAL; 1287 } 1288 1289 if (clk->module != NULL) { 1290 return set_module_rate(clk->module, rate, orate, depth); 1291 } 1292 1293 if (clk->pclock != NULL) { 1294 return set_clk_freq(&clk->pclock->desc, rate, orate, depth); 1295 } 1296 1297 return -EINVAL; 1298 } 1299 1300 static int get_clk_freq(const struct s32cc_clk_obj *module, 1301 const struct s32cc_clk_drv *drv, unsigned long *rate, 1302 unsigned int depth) 1303 { 1304 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1305 unsigned int ldepth = depth; 1306 int ret; 1307 1308 ret = update_stack_depth(&ldepth); 1309 if (ret != 0) { 1310 return ret; 1311 } 1312 1313 if (clk == NULL) { 1314 ERROR("Invalid clock\n"); 1315 return -EINVAL; 1316 } 1317 1318 if (clk->module != NULL) { 1319 return get_module_rate(clk->module, drv, rate, ldepth); 1320 } 1321 1322 if (clk->pclock == NULL) { 1323 ERROR("Invalid clock parent\n"); 1324 return -EINVAL; 1325 } 1326 1327 return get_clk_freq(&clk->pclock->desc, drv, rate, ldepth); 1328 } 1329 1330 static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1331 unsigned long *orate, unsigned int *depth) 1332 { 1333 struct s32cc_pll *pll = s32cc_obj2pll(module); 1334 int ret; 1335 1336 ret = update_stack_depth(depth); 1337 if (ret != 0) { 1338 return ret; 1339 } 1340 1341 if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) { 1342 ERROR("PLL frequency was already set\n"); 1343 return -EINVAL; 1344 } 1345 1346 pll->vco_freq = rate; 1347 *orate = pll->vco_freq; 1348 1349 return 0; 1350 } 1351 1352 static int get_pll_freq(const struct s32cc_clk_obj *module, 1353 const struct s32cc_clk_drv *drv, 1354 unsigned long *rate, unsigned int depth) 1355 { 1356 const struct s32cc_pll *pll = s32cc_obj2pll(module); 1357 const struct s32cc_clk *source; 1358 uint32_t mfi, mfn, rdiv, plldv; 1359 unsigned long prate, clk_src; 1360 unsigned int ldepth = depth; 1361 uintptr_t pll_addr = 0UL; 1362 uint64_t t1, t2; 1363 int ret; 1364 1365 ret = update_stack_depth(&ldepth); 1366 if (ret != 0) { 1367 return ret; 1368 } 1369 1370 ret = get_base_addr(pll->instance, drv, &pll_addr); 1371 if (ret != 0) { 1372 ERROR("Failed to detect PLL instance\n"); 1373 return ret; 1374 } 1375 1376 /* Disabled PLL */ 1377 if (!is_pll_enabled(pll_addr)) { 1378 *rate = pll->vco_freq; 1379 return 0; 1380 } 1381 1382 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 1383 switch (clk_src) { 1384 case 0: 1385 clk_src = S32CC_CLK_FIRC; 1386 break; 1387 case 1: 1388 clk_src = S32CC_CLK_FXOSC; 1389 break; 1390 default: 1391 ERROR("Failed to identify PLL source id %" PRIu64 "\n", clk_src); 1392 return -EINVAL; 1393 }; 1394 1395 source = s32cc_get_arch_clk(clk_src); 1396 if (source == NULL) { 1397 ERROR("Failed to get PLL source clock\n"); 1398 return -EINVAL; 1399 } 1400 1401 ret = get_module_rate(&source->desc, drv, &prate, ldepth); 1402 if (ret != 0) { 1403 ERROR("Failed to get PLL's parent frequency\n"); 1404 return ret; 1405 } 1406 1407 plldv = mmio_read_32(PLLDIG_PLLDV(pll_addr)); 1408 mfi = PLLDIG_PLLDV_MFI(plldv); 1409 rdiv = PLLDIG_PLLDV_RDIV(plldv); 1410 if (rdiv == 0U) { 1411 rdiv = 1; 1412 } 1413 1414 /* Frac-N mode */ 1415 mfn = PLLDIG_PLLFD_MFN_SET(mmio_read_32(PLLDIG_PLLFD(pll_addr))); 1416 1417 /* PLL VCO frequency in Fractional mode when PLLDV[RDIV] is not 0 */ 1418 t1 = prate / rdiv; 1419 t2 = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 18432U); 1420 1421 *rate = t1 * t2 / FP_PRECISION; 1422 1423 return 0; 1424 } 1425 1426 static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1427 unsigned long *orate, unsigned int *depth) 1428 { 1429 struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1430 const struct s32cc_pll *pll; 1431 unsigned long prate, dc; 1432 int ret; 1433 1434 ret = update_stack_depth(depth); 1435 if (ret != 0) { 1436 return ret; 1437 } 1438 1439 if (pdiv->parent == NULL) { 1440 ERROR("Failed to identify PLL divider's parent\n"); 1441 return -EINVAL; 1442 } 1443 1444 pll = s32cc_obj2pll(pdiv->parent); 1445 if (pll == NULL) { 1446 ERROR("The parent of the PLL DIV is invalid\n"); 1447 return -EINVAL; 1448 } 1449 1450 prate = pll->vco_freq; 1451 1452 /** 1453 * The PLL is not initialized yet, so let's take a risk 1454 * and accept the proposed rate. 1455 */ 1456 if (prate == 0UL) { 1457 pdiv->freq = rate; 1458 *orate = rate; 1459 return 0; 1460 } 1461 1462 /* Decline in case the rate cannot fit PLL's requirements. */ 1463 dc = prate / rate; 1464 if ((prate / dc) != rate) { 1465 return -EINVAL; 1466 } 1467 1468 pdiv->freq = rate; 1469 *orate = pdiv->freq; 1470 1471 return 0; 1472 } 1473 1474 static int get_pll_div_freq(const struct s32cc_clk_obj *module, 1475 const struct s32cc_clk_drv *drv, 1476 unsigned long *rate, unsigned int depth) 1477 { 1478 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1479 const struct s32cc_pll *pll; 1480 unsigned int ldepth = depth; 1481 uintptr_t pll_addr = 0UL; 1482 unsigned long pfreq; 1483 uint32_t pllodiv; 1484 uint32_t dc; 1485 int ret; 1486 1487 ret = update_stack_depth(&ldepth); 1488 if (ret != 0) { 1489 return ret; 1490 } 1491 1492 pll = get_div_pll(pdiv); 1493 if (pll == NULL) { 1494 ERROR("The parent of the PLL DIV is invalid\n"); 1495 return -EINVAL; 1496 } 1497 1498 ret = get_base_addr(pll->instance, drv, &pll_addr); 1499 if (ret != 0) { 1500 ERROR("Failed to detect PLL instance\n"); 1501 return -EINVAL; 1502 } 1503 1504 ret = get_module_rate(pdiv->parent, drv, &pfreq, ldepth); 1505 if (ret != 0) { 1506 ERROR("Failed to get the frequency of PLL %" PRIxPTR "\n", 1507 pll_addr); 1508 return ret; 1509 } 1510 1511 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index)); 1512 1513 /* Disabled module */ 1514 if ((pllodiv & PLLDIG_PLLODIV_DE) == 0U) { 1515 *rate = pdiv->freq; 1516 return 0; 1517 } 1518 1519 dc = PLLDIG_PLLODIV_DIV(pllodiv); 1520 *rate = (pfreq * FP_PRECISION) / (dc + 1U) / FP_PRECISION; 1521 1522 return 0; 1523 } 1524 1525 static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1526 unsigned long *orate, unsigned int *depth) 1527 { 1528 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1529 int ret; 1530 1531 ret = update_stack_depth(depth); 1532 if (ret != 0) { 1533 return ret; 1534 } 1535 1536 if (fdiv->parent == NULL) { 1537 ERROR("The divider doesn't have a valid parent\b"); 1538 return -EINVAL; 1539 } 1540 1541 ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth); 1542 1543 /* Update the output rate based on the parent's rate */ 1544 *orate /= fdiv->rate_div; 1545 1546 return ret; 1547 } 1548 1549 static int get_fixed_div_freq(const struct s32cc_clk_obj *module, 1550 const struct s32cc_clk_drv *drv, 1551 unsigned long *rate, unsigned int depth) 1552 { 1553 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1554 unsigned long pfreq; 1555 int ret; 1556 1557 ret = get_module_rate(fdiv->parent, drv, &pfreq, depth); 1558 if (ret != 0) { 1559 return ret; 1560 } 1561 1562 *rate = (pfreq * FP_PRECISION / fdiv->rate_div) / FP_PRECISION; 1563 return 0; 1564 } 1565 1566 static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1567 unsigned long *orate, unsigned int *depth) 1568 { 1569 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1570 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1571 int ret; 1572 1573 ret = update_stack_depth(depth); 1574 if (ret != 0) { 1575 return ret; 1576 } 1577 1578 if (clk == NULL) { 1579 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1580 mux->index, mux->source_id); 1581 return -EINVAL; 1582 } 1583 1584 return set_module_rate(&clk->desc, rate, orate, depth); 1585 } 1586 1587 static int get_mux_freq(const struct s32cc_clk_obj *module, 1588 const struct s32cc_clk_drv *drv, 1589 unsigned long *rate, unsigned int depth) 1590 { 1591 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1592 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1593 unsigned int ldepth = depth; 1594 int ret; 1595 1596 ret = update_stack_depth(&ldepth); 1597 if (ret != 0) { 1598 return ret; 1599 } 1600 1601 if (clk == NULL) { 1602 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1603 mux->index, mux->source_id); 1604 return -EINVAL; 1605 } 1606 1607 return get_clk_freq(&clk->desc, drv, rate, ldepth); 1608 } 1609 1610 static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1611 unsigned long *orate, unsigned int *depth) 1612 { 1613 struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1614 const struct s32cc_dfs *dfs; 1615 int ret; 1616 1617 ret = update_stack_depth(depth); 1618 if (ret != 0) { 1619 return ret; 1620 } 1621 1622 if (dfs_div->parent == NULL) { 1623 ERROR("Failed to identify DFS divider's parent\n"); 1624 return -EINVAL; 1625 } 1626 1627 /* Sanity check */ 1628 dfs = s32cc_obj2dfs(dfs_div->parent); 1629 if (dfs->parent == NULL) { 1630 ERROR("Failed to identify DFS's parent\n"); 1631 return -EINVAL; 1632 } 1633 1634 if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) { 1635 ERROR("DFS DIV frequency was already set to %lu\n", 1636 dfs_div->freq); 1637 return -EINVAL; 1638 } 1639 1640 dfs_div->freq = rate; 1641 *orate = rate; 1642 1643 return ret; 1644 } 1645 1646 static unsigned long compute_dfs_div_freq(unsigned long pfreq, uint32_t mfi, uint32_t mfn) 1647 { 1648 unsigned long freq; 1649 1650 /** 1651 * Formula for input and output clocks of each port divider. 1652 * See 'Digital Frequency Synthesizer' chapter from Reference Manual. 1653 * 1654 * freq = pfreq / (2 * (mfi + mfn / 36.0)); 1655 */ 1656 freq = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 36UL); 1657 freq *= 2UL; 1658 freq = pfreq * FP_PRECISION / freq; 1659 1660 return freq; 1661 } 1662 1663 static int get_dfs_div_freq(const struct s32cc_clk_obj *module, 1664 const struct s32cc_clk_drv *drv, 1665 unsigned long *rate, unsigned int depth) 1666 { 1667 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1668 unsigned int ldepth = depth; 1669 const struct s32cc_dfs *dfs; 1670 uint32_t dvport, mfi, mfn; 1671 uintptr_t dfs_addr = 0UL; 1672 unsigned long pfreq; 1673 int ret; 1674 1675 ret = update_stack_depth(&ldepth); 1676 if (ret != 0) { 1677 return ret; 1678 } 1679 1680 dfs = get_div_dfs(dfs_div); 1681 if (dfs == NULL) { 1682 return -EINVAL; 1683 } 1684 1685 ret = get_module_rate(dfs_div->parent, drv, &pfreq, ldepth); 1686 if (ret != 0) { 1687 return ret; 1688 } 1689 1690 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 1691 if (ret != 0) { 1692 ERROR("Failed to detect the DFS instance\n"); 1693 return ret; 1694 } 1695 1696 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, dfs_div->index)); 1697 1698 mfi = DFS_DVPORTn_MFI(dvport); 1699 mfn = DFS_DVPORTn_MFN(dvport); 1700 1701 /* Disabled port */ 1702 if ((mfi == 0U) && (mfn == 0U)) { 1703 *rate = dfs_div->freq; 1704 return 0; 1705 } 1706 1707 *rate = compute_dfs_div_freq(pfreq, mfi, mfn); 1708 return 0; 1709 } 1710 1711 static int set_module_rate(const struct s32cc_clk_obj *module, 1712 unsigned long rate, unsigned long *orate, 1713 unsigned int *depth) 1714 { 1715 int ret = 0; 1716 1717 ret = update_stack_depth(depth); 1718 if (ret != 0) { 1719 return ret; 1720 } 1721 1722 ret = -EINVAL; 1723 1724 switch (module->type) { 1725 case s32cc_clk_t: 1726 ret = set_clk_freq(module, rate, orate, depth); 1727 break; 1728 case s32cc_osc_t: 1729 ret = set_osc_freq(module, rate, orate, depth); 1730 break; 1731 case s32cc_pll_t: 1732 ret = set_pll_freq(module, rate, orate, depth); 1733 break; 1734 case s32cc_pll_out_div_t: 1735 ret = set_pll_div_freq(module, rate, orate, depth); 1736 break; 1737 case s32cc_fixed_div_t: 1738 ret = set_fixed_div_freq(module, rate, orate, depth); 1739 break; 1740 case s32cc_clkmux_t: 1741 ret = set_mux_freq(module, rate, orate, depth); 1742 break; 1743 case s32cc_shared_clkmux_t: 1744 ret = set_mux_freq(module, rate, orate, depth); 1745 break; 1746 case s32cc_dfs_t: 1747 ERROR("Setting the frequency of a DFS is not allowed!"); 1748 break; 1749 case s32cc_dfs_div_t: 1750 ret = set_dfs_div_freq(module, rate, orate, depth); 1751 break; 1752 default: 1753 break; 1754 } 1755 1756 return ret; 1757 } 1758 1759 static int get_module_rate(const struct s32cc_clk_obj *module, 1760 const struct s32cc_clk_drv *drv, 1761 unsigned long *rate, 1762 unsigned int depth) 1763 { 1764 unsigned int ldepth = depth; 1765 int ret = 0; 1766 1767 ret = update_stack_depth(&ldepth); 1768 if (ret != 0) { 1769 return ret; 1770 } 1771 1772 switch (module->type) { 1773 case s32cc_osc_t: 1774 ret = get_osc_freq(module, drv, rate, ldepth); 1775 break; 1776 case s32cc_clk_t: 1777 ret = get_clk_freq(module, drv, rate, ldepth); 1778 break; 1779 case s32cc_pll_t: 1780 ret = get_pll_freq(module, drv, rate, ldepth); 1781 break; 1782 case s32cc_dfs_t: 1783 ret = get_dfs_freq(module, drv, rate, ldepth); 1784 break; 1785 case s32cc_dfs_div_t: 1786 ret = get_dfs_div_freq(module, drv, rate, ldepth); 1787 break; 1788 case s32cc_fixed_div_t: 1789 ret = get_fixed_div_freq(module, drv, rate, ldepth); 1790 break; 1791 case s32cc_pll_out_div_t: 1792 ret = get_pll_div_freq(module, drv, rate, ldepth); 1793 break; 1794 case s32cc_clkmux_t: 1795 ret = get_mux_freq(module, drv, rate, ldepth); 1796 break; 1797 case s32cc_shared_clkmux_t: 1798 ret = get_mux_freq(module, drv, rate, ldepth); 1799 break; 1800 case s32cc_part_t: 1801 ERROR("s32cc_part_t cannot be used to get rate\n"); 1802 break; 1803 case s32cc_part_block_t: 1804 ERROR("s32cc_part_block_t cannot be used to get rate\n"); 1805 break; 1806 case s32cc_part_block_link_t: 1807 ret = get_part_block_link_freq(module, drv, rate, ldepth); 1808 break; 1809 default: 1810 ret = -EINVAL; 1811 break; 1812 } 1813 1814 return ret; 1815 } 1816 1817 static int s32cc_clk_set_rate(unsigned long id, unsigned long rate, 1818 unsigned long *orate) 1819 { 1820 unsigned int depth = MAX_STACK_DEPTH; 1821 const struct s32cc_clk *clk; 1822 int ret; 1823 1824 clk = s32cc_get_arch_clk(id); 1825 if (clk == NULL) { 1826 return -EINVAL; 1827 } 1828 1829 ret = set_module_rate(&clk->desc, rate, orate, &depth); 1830 if (ret != 0) { 1831 ERROR("Failed to set frequency (%lu MHz) for clock %lu\n", 1832 rate, id); 1833 } 1834 1835 return ret; 1836 } 1837 1838 static unsigned long s32cc_clk_get_rate(unsigned long id) 1839 { 1840 const struct s32cc_clk_drv *drv = get_drv(); 1841 unsigned int depth = MAX_STACK_DEPTH; 1842 const struct s32cc_clk *clk; 1843 unsigned long rate = 0UL; 1844 int ret; 1845 1846 clk = s32cc_get_arch_clk(id); 1847 if (clk == NULL) { 1848 return 0; 1849 } 1850 1851 ret = get_module_rate(&clk->desc, drv, &rate, depth); 1852 if (ret != 0) { 1853 ERROR("Failed to get frequency (%lu MHz) for clock %lu\n", 1854 rate, id); 1855 return 0; 1856 } 1857 1858 return rate; 1859 } 1860 1861 static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module) 1862 { 1863 return NULL; 1864 } 1865 1866 typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj); 1867 1868 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module) 1869 { 1870 static const get_parent_clb_t parents_clbs[12] = { 1871 [s32cc_clk_t] = get_clk_parent, 1872 [s32cc_osc_t] = get_no_parent, 1873 [s32cc_pll_t] = get_pll_parent, 1874 [s32cc_pll_out_div_t] = get_pll_div_parent, 1875 [s32cc_clkmux_t] = get_mux_parent, 1876 [s32cc_shared_clkmux_t] = get_mux_parent, 1877 [s32cc_dfs_t] = get_dfs_parent, 1878 [s32cc_dfs_div_t] = get_dfs_div_parent, 1879 [s32cc_part_t] = get_no_parent, 1880 [s32cc_part_block_t] = get_part_block_parent, 1881 [s32cc_part_block_link_t] = get_part_block_link_parent, 1882 }; 1883 uint32_t index; 1884 1885 if (module == NULL) { 1886 return NULL; 1887 } 1888 1889 index = (uint32_t)module->type; 1890 1891 if (index >= ARRAY_SIZE(parents_clbs)) { 1892 ERROR("Undefined module type: %d\n", module->type); 1893 return NULL; 1894 } 1895 1896 if (parents_clbs[index] == NULL) { 1897 ERROR("Undefined parent getter for type: %d\n", module->type); 1898 return NULL; 1899 } 1900 1901 return parents_clbs[index](module); 1902 } 1903 1904 static int s32cc_clk_get_parent(unsigned long id) 1905 { 1906 struct s32cc_clk *parent_clk; 1907 const struct s32cc_clk_obj *parent; 1908 const struct s32cc_clk *clk; 1909 unsigned long parent_id; 1910 int ret; 1911 1912 clk = s32cc_get_arch_clk(id); 1913 if (clk == NULL) { 1914 return -EINVAL; 1915 } 1916 1917 parent = get_module_parent(clk->module); 1918 if (parent == NULL) { 1919 return -EINVAL; 1920 } 1921 1922 parent_clk = s32cc_obj2clk(parent); 1923 if (parent_clk == NULL) { 1924 return -EINVAL; 1925 } 1926 1927 ret = s32cc_get_clk_id(parent_clk, &parent_id); 1928 if (ret != 0) { 1929 return ret; 1930 } 1931 1932 if (parent_id > (unsigned long)INT_MAX) { 1933 return -E2BIG; 1934 } 1935 1936 return (int)parent_id; 1937 } 1938 1939 static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id) 1940 { 1941 const struct s32cc_clk *parent; 1942 const struct s32cc_clk *clk; 1943 bool valid_source = false; 1944 struct s32cc_clkmux *mux; 1945 uint8_t i; 1946 1947 clk = s32cc_get_arch_clk(id); 1948 if (clk == NULL) { 1949 return -EINVAL; 1950 } 1951 1952 parent = s32cc_get_arch_clk(parent_id); 1953 if (parent == NULL) { 1954 return -EINVAL; 1955 } 1956 1957 if (!is_s32cc_clk_mux(clk)) { 1958 ERROR("Clock %lu is not a mux\n", id); 1959 return -EINVAL; 1960 } 1961 1962 mux = s32cc_clk2mux(clk); 1963 if (mux == NULL) { 1964 ERROR("Failed to cast clock %lu to clock mux\n", id); 1965 return -EINVAL; 1966 } 1967 1968 for (i = 0; i < mux->nclks; i++) { 1969 if (mux->clkids[i] == parent_id) { 1970 valid_source = true; 1971 break; 1972 } 1973 } 1974 1975 if (!valid_source) { 1976 ERROR("Clock %lu is not a valid clock for mux %lu\n", 1977 parent_id, id); 1978 return -EINVAL; 1979 } 1980 1981 mux->source_id = parent_id; 1982 1983 return 0; 1984 } 1985 1986 static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) 1987 { 1988 const uintptr_t base_addrs[12] = { 1989 drv->fxosc_base, 1990 drv->armpll_base, 1991 drv->periphpll_base, 1992 drv->armdfs_base, 1993 drv->periphdfs_base, 1994 drv->cgm0_base, 1995 drv->cgm1_base, 1996 drv->cgm5_base, 1997 drv->ddrpll_base, 1998 drv->mc_me, 1999 drv->mc_rgm, 2000 drv->rdc, 2001 }; 2002 size_t i; 2003 int ret; 2004 2005 for (i = 0U; i < ARRAY_SIZE(base_addrs); i++) { 2006 ret = mmap_add_dynamic_region(base_addrs[i], base_addrs[i], 2007 PAGE_SIZE, 2008 MT_DEVICE | MT_RW | MT_SECURE); 2009 if (ret != 0) { 2010 ERROR("Failed to map clock module 0x%" PRIuPTR "\n", 2011 base_addrs[i]); 2012 return ret; 2013 } 2014 } 2015 2016 return 0; 2017 } 2018 2019 int s32cc_clk_register_drv(bool mmap_regs) 2020 { 2021 static const struct clk_ops s32cc_clk_ops = { 2022 .enable = s32cc_clk_enable, 2023 .disable = s32cc_clk_disable, 2024 .is_enabled = s32cc_clk_is_enabled, 2025 .get_rate = s32cc_clk_get_rate, 2026 .set_rate = s32cc_clk_set_rate, 2027 .get_parent = s32cc_clk_get_parent, 2028 .set_parent = s32cc_clk_set_parent, 2029 }; 2030 const struct s32cc_clk_drv *drv; 2031 2032 clk_register(&s32cc_clk_ops); 2033 2034 drv = get_drv(); 2035 if (drv == NULL) { 2036 return -EINVAL; 2037 } 2038 2039 if (mmap_regs) { 2040 return s32cc_clk_mmap_regs(drv); 2041 } 2042 2043 return 0; 2044 } 2045 2046