1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* .global erratum_cortex_a520_2938996_wa */ 15.global check_erratum_cortex_a520_2938996 16 17/* Hardware handled coherency */ 18#if HW_ASSISTED_COHERENCY == 0 19#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 20#endif 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 28 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 29workaround_reset_end cortex_a520, ERRATUM(2630792) 30 31check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 32 33workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 34 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 35workaround_reset_end cortex_a520, ERRATUM(2858100) 36 37check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 38 39workaround_runtime_start cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996, CORTEX_A520_MIDR 40workaround_runtime_end cortex_a520, ERRATUM(2938996) 41 42check_erratum_custom_start cortex_a520, ERRATUM(2938996) 43 44 /* This erratum needs to be enabled for r0p0 and r0p1. 45 * Check if revision is less than or equal to r0p1. 46 */ 47 48#if ERRATA_A520_2938996 49 mov x1, #1 50 b cpu_rev_var_ls 51#else 52 mov x0, #ERRATA_MISSING 53#endif 54 ret 55check_erratum_custom_end cortex_a520, ERRATUM(2938996) 56 57 /* ---------------------------------------------------- 58 * HW will do the cache maintenance while powering down 59 * ---------------------------------------------------- 60 */ 61func cortex_a520_core_pwr_dwn 62 /* --------------------------------------------------- 63 * Enable CPU power down bit in power control register 64 * --------------------------------------------------- 65 */ 66 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 67 isb 68 ret 69endfunc cortex_a520_core_pwr_dwn 70 71errata_report_shim cortex_a520 72 73cpu_reset_func_start cortex_a520 74 /* Disable speculative loads */ 75 msr SSBS, xzr 76cpu_reset_func_end cortex_a520 77 78 /* --------------------------------------------- 79 * This function provides Cortex A520 specific 80 * register information for crash reporting. 81 * It needs to return with x6 pointing to 82 * a list of register names in ascii and 83 * x8 - x15 having values of registers to be 84 * reported. 85 * --------------------------------------------- 86 */ 87.section .rodata.cortex_a520_regs, "aS" 88cortex_a520_regs: /* The ascii list of register names to be reported */ 89 .asciz "cpuectlr_el1", "" 90 91func cortex_a520_cpu_reg_dump 92 adr x6, cortex_a520_regs 93 mrs x8, CORTEX_A520_CPUECTLR_EL1 94 ret 95endfunc cortex_a520_cpu_reg_dump 96 97declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 98 cortex_a520_reset_func, \ 99 cortex_a520_core_pwr_dwn 100