1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59 ENABLE_FEAT_D128 := 2 60 ENABLE_FEAT_FPMR := 2 61 ENABLE_FEAT_MOPS := 2 62endif 63 64ENABLE_SYS_REG_TRACE_FOR_NS := 2 65ENABLE_FEAT_CSV2_2 := 2 66ENABLE_FEAT_CSV2_3 := 2 67ENABLE_FEAT_DEBUGV8P9 := 2 68ENABLE_FEAT_DIT := 2 69ENABLE_FEAT_PAN := 2 70ENABLE_FEAT_VHE := 2 71CTX_INCLUDE_NEVE_REGS := 2 72ENABLE_FEAT_SEL2 := 2 73ENABLE_TRF_FOR_NS := 2 74ENABLE_FEAT_ECV := 2 75ENABLE_FEAT_FGT := 2 76ENABLE_FEAT_FGT2 := 2 77ENABLE_FEAT_THE := 2 78ENABLE_FEAT_TCR2 := 2 79ENABLE_FEAT_S2PIE := 2 80ENABLE_FEAT_S1PIE := 2 81ENABLE_FEAT_S2POE := 2 82ENABLE_FEAT_S1POE := 2 83ENABLE_FEAT_SCTLR2 := 2 84ENABLE_FEAT_MTE2 := 2 85ENABLE_FEAT_LS64_ACCDATA := 2 86 87# The FVP platform depends on this macro to build with correct GIC driver. 88$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 89 90# Pass FVP_CLUSTER_COUNT to the build system. 91$(eval $(call add_define,FVP_CLUSTER_COUNT)) 92 93# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 94$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 95 96# Pass FVP_MAX_PE_PER_CPU to the build system. 97$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 98 99# Pass FVP_GICR_REGION_PROTECTION to the build system. 100$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 101 102# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 103$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 104 105# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 106# choose the CCI driver , else the CCN driver 107ifeq ($(FVP_CLUSTER_COUNT), 0) 108$(error "Incorrect cluster count specified for FVP port") 109else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 110FVP_INTERCONNECT_DRIVER := FVP_CCI 111else 112FVP_INTERCONNECT_DRIVER := FVP_CCN 113endif 114 115$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 116 117# Choose the GIC sources depending upon the how the FVP will be invoked 118ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 119 120# The GIC model (GIC-600 or GIC-500) will be detected at runtime 121GICV3_SUPPORT_GIC600 := 1 122GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 123 124# Include GICv3 driver files 125include drivers/arm/gic/v3/gicv3.mk 126 127FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 128 plat/common/plat_gicv3.c \ 129 plat/arm/common/arm_gicv3.c 130 131 ifeq ($(filter 1,${RESET_TO_BL2} \ 132 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 133 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 134 endif 135 136else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 137 138# No GICv4 extension 139GIC_ENABLE_V4_EXTN := 0 140$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 141 142# Include GICv2 driver files 143include drivers/arm/gic/v2/gicv2.mk 144 145FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 146 plat/common/plat_gicv2.c \ 147 plat/arm/common/arm_gicv2.c 148 149FVP_DT_PREFIX := fvp-base-gicv2-psci 150else 151$(error "Incorrect GIC driver chosen on FVP port") 152endif 153 154ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 155FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 156else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 157FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 158 plat/arm/common/arm_ccn.c 159else 160$(error "Incorrect CCN driver chosen on FVP port") 161endif 162 163FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 164 plat/arm/board/fvp/fvp_security.c \ 165 plat/arm/common/arm_tzc400.c 166 167 168PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 169 -Iinclude/lib/psa 170 171 172PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 173 174FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 175 176ifeq (${ARCH}, aarch64) 177 178# select a different set of CPU files, depending on whether we compile for 179# hardware assisted coherency cores or not 180ifeq (${HW_ASSISTED_COHERENCY}, 0) 181# Cores used without DSU 182 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 183 lib/cpus/aarch64/cortex_a53.S \ 184 lib/cpus/aarch64/cortex_a57.S \ 185 lib/cpus/aarch64/cortex_a72.S \ 186 lib/cpus/aarch64/cortex_a73.S 187else 188# Cores used with DSU only 189 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 190 # AArch64-only cores 191 # TODO: add all cores to the appropriate lists 192 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 193 lib/cpus/aarch64/cortex_a65ae.S \ 194 lib/cpus/aarch64/cortex_a76.S \ 195 lib/cpus/aarch64/cortex_a76ae.S \ 196 lib/cpus/aarch64/cortex_a77.S \ 197 lib/cpus/aarch64/cortex_a78.S \ 198 lib/cpus/aarch64/cortex_a78_ae.S \ 199 lib/cpus/aarch64/cortex_a78c.S \ 200 lib/cpus/aarch64/cortex_a710.S \ 201 lib/cpus/aarch64/cortex_a715.S \ 202 lib/cpus/aarch64/cortex_a720.S \ 203 lib/cpus/aarch64/cortex_a720_ae.S \ 204 lib/cpus/aarch64/neoverse_n_common.S \ 205 lib/cpus/aarch64/neoverse_n1.S \ 206 lib/cpus/aarch64/neoverse_n2.S \ 207 lib/cpus/aarch64/neoverse_v1.S \ 208 lib/cpus/aarch64/neoverse_e1.S \ 209 lib/cpus/aarch64/cortex_x2.S \ 210 lib/cpus/aarch64/cortex_x4.S 211 endif 212 # AArch64/AArch32 cores 213 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 214 lib/cpus/aarch64/cortex_a75.S 215endif 216 217#Build AArch64-only CPUs with no FVP model yet. 218ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 219 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 220 lib/cpus/aarch64/cortex_gelas.S \ 221 lib/cpus/aarch64/nevis.S \ 222 lib/cpus/aarch64/travis.S \ 223 lib/cpus/aarch64/cortex_arcadia.S \ 224 lib/cpus/aarch64/cortex_alto.S 225endif 226 227else 228FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 229 lib/cpus/aarch32/cortex_a57.S \ 230 lib/cpus/aarch32/cortex_a53.S 231endif 232 233BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 234 drivers/arm/sp805/sp805.c \ 235 drivers/delay_timer/delay_timer.c \ 236 drivers/io/io_semihosting.c \ 237 lib/semihosting/semihosting.c \ 238 lib/semihosting/${ARCH}/semihosting_call.S \ 239 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 240 plat/arm/board/fvp/fvp_bl1_setup.c \ 241 plat/arm/board/fvp/fvp_cpu_pwr.c \ 242 plat/arm/board/fvp/fvp_err.c \ 243 plat/arm/board/fvp/fvp_io_storage.c \ 244 plat/arm/board/fvp/fvp_topology.c \ 245 ${FVP_CPU_LIBS} \ 246 ${FVP_INTERCONNECT_SOURCES} 247 248ifeq (${USE_SP804_TIMER},1) 249BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 250else 251BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 252endif 253 254 255BL2_SOURCES += drivers/arm/sp805/sp805.c \ 256 drivers/io/io_semihosting.c \ 257 lib/utils/mem_region.c \ 258 lib/semihosting/semihosting.c \ 259 lib/semihosting/${ARCH}/semihosting_call.S \ 260 plat/arm/board/fvp/fvp_bl2_setup.c \ 261 plat/arm/board/fvp/fvp_err.c \ 262 plat/arm/board/fvp/fvp_io_storage.c \ 263 plat/arm/common/arm_nor_psci_mem_protect.c \ 264 ${FVP_SECURITY_SOURCES} 265 266 267ifeq (${COT_DESC_IN_DTB},1) 268BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 269endif 270 271ifeq (${ENABLE_RME},1) 272BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 273 plat/arm/board/fvp/fvp_cpu_pwr.c 274 275BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 276 plat/arm/board/fvp/fvp_realm_attest_key.c \ 277 plat/arm/board/fvp/fvp_el3_token_sign.c 278endif 279 280ifeq (${ENABLE_FEAT_RNG_TRAP},1) 281BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 282endif 283 284ifeq (${RESET_TO_BL2},1) 285BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 286 plat/arm/board/fvp/fvp_cpu_pwr.c \ 287 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 288 ${FVP_CPU_LIBS} \ 289 ${FVP_INTERCONNECT_SOURCES} 290endif 291 292ifeq (${USE_SP804_TIMER},1) 293BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 294endif 295 296BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 297 ${FVP_SECURITY_SOURCES} 298 299ifeq (${USE_SP804_TIMER},1) 300BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 301endif 302 303BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 304 drivers/arm/smmu/smmu_v3.c \ 305 drivers/delay_timer/delay_timer.c \ 306 drivers/cfi/v2m/v2m_flash.c \ 307 lib/utils/mem_region.c \ 308 plat/arm/board/fvp/fvp_bl31_setup.c \ 309 plat/arm/board/fvp/fvp_console.c \ 310 plat/arm/board/fvp/fvp_pm.c \ 311 plat/arm/board/fvp/fvp_topology.c \ 312 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 313 plat/arm/board/fvp/fvp_cpu_pwr.c \ 314 plat/arm/common/arm_nor_psci_mem_protect.c \ 315 ${FVP_CPU_LIBS} \ 316 ${FVP_GIC_SOURCES} \ 317 ${FVP_INTERCONNECT_SOURCES} \ 318 ${FVP_SECURITY_SOURCES} 319 320# Support for fconf in BL31 321# Added separately from the above list for better readability 322ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 323BL31_SOURCES += lib/fconf/fconf.c \ 324 lib/fconf/fconf_dyn_cfg_getter.c \ 325 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 326 327BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 328 329ifeq (${SEC_INT_DESC_IN_FCONF},1) 330BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 331endif 332 333endif 334 335ifeq (${USE_SP804_TIMER},1) 336BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 337else 338BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 339endif 340 341# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 342FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 343 344FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 345$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 346 347ifeq (${TRANSFER_LIST}, 0) 348FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 349 ${PLAT}_fw_config.dts \ 350 ${PLAT}_tb_fw_config.dts \ 351 ${PLAT}_soc_fw_config.dts \ 352 ${PLAT}_nt_fw_config.dts \ 353 ) 354 355FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 356FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 357FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 358FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 359 360ifeq (${SPD},tspd) 361FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 362FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 363 364# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 366endif 367 368ifeq (${SPD},spmd) 369 370ifeq ($(ARM_SPMC_MANIFEST_DTS),) 371ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 372endif 373 374FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 375FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 376 377# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 379endif 380 381# Add the FW_CONFIG to FIP and specify the same to certtool 382$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 383# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 385# Add the NT_FW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 387# Add the TB_FW_CONFIG to FIP and specify the same to certtool 388$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 389endif 390 391# Add the HW_CONFIG to FIP and specify the same to certtool 392$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 393 394ifeq (${TRANSFER_LIST}, 1) 395include lib/transfer_list/transfer_list.mk 396 397ifeq ($(RESET_TO_BL31), 1) 398HW_CONFIG := ${FVP_HW_CONFIG} 399FW_HANDOFF_SIZE := 20000 400 401TRANSFER_LIST_DTB_OFFSET := 0x20 402$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 403endif 404endif 405 406ifeq (${HOB_LIST}, 1) 407include lib/hob/hob.mk 408endif 409 410# Enable dynamic mitigation support by default 411DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 412 413ifneq (${ENABLE_FEAT_AMU},0) 414BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 415 lib/cpus/aarch64/cpuamu_helpers.S 416 417ifeq (${HW_ASSISTED_COHERENCY}, 1) 418BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 419 lib/cpus/aarch64/neoverse_n1_pubsub.c 420endif 421endif 422 423ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 424 ifeq (${ENABLE_FEAT_RAS},1) 425 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 426 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 427 else 428 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 429 endif 430 else 431 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 432 endif 433endif 434 435ifneq (${ENABLE_STACK_PROTECTOR},0) 436PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 437endif 438 439# Enable the dynamic translation tables library. 440ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 441 ifeq (${ARCH},aarch32) 442 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 443 else # AArch64 444 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 445 endif 446endif 447 448ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 449 ifeq (${ARCH},aarch32) 450 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 451 else # AArch64 452 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 453 ifeq (${SPD},tspd) 454 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 455 endif 456 endif 457endif 458 459ifeq (${USE_DEBUGFS},1) 460 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 461endif 462 463# Add support for platform supplied linker script for BL31 build 464$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 465 466ifneq (${RESET_TO_BL2}, 0) 467 override BL1_SOURCES = 468endif 469 470include plat/arm/board/common/board_common.mk 471include plat/arm/common/arm_common.mk 472 473ifeq (${MEASURED_BOOT},1) 474BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 475 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 476 lib/psa/measured_boot.c 477 478BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 479 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 480 lib/psa/measured_boot.c 481endif 482 483ifeq (${DRTM_SUPPORT}, 1) 484BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 485 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 486 plat/arm/board/fvp/fvp_drtm_err.c \ 487 plat/arm/board/fvp/fvp_drtm_measurement.c \ 488 plat/arm/board/fvp/fvp_drtm_stub.c \ 489 plat/arm/common/arm_dyn_cfg.c \ 490 plat/arm/board/fvp/fvp_err.c 491endif 492 493ifeq (${TRUSTED_BOARD_BOOT}, 1) 494BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 495BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 496 497# FVP being a development platform, enable capability to disable Authentication 498# dynamically if TRUSTED_BOARD_BOOT is set. 499DYN_DISABLE_AUTH := 1 500endif 501 502ifeq (${SPMC_AT_EL3}, 1) 503PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 504endif 505 506PSCI_OS_INIT_MODE := 1 507 508ifeq (${SPD},spmd) 509BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 510endif 511 512# Test specific macros, keep them at bottom of this file 513$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 514ifeq (${PLATFORM_TEST_EA_FFH}, 1) 515 ifeq (${FFH_SUPPORT}, 0) 516 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 517 endif 518 519endif 520 521$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 522ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 523 ifeq (${ENABLE_FEAT_RAS}, 0) 524 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 525 endif 526 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 527 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 528 endif 529endif 530 531$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 532ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 533 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 534 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 535 endif 536 ifeq (${ENABLE_SPMD_LP}, 0) 537 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 538 endif 539 ifeq (${ENABLE_FEAT_RAS}, 0) 540 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 541 endif 542 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 543 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 544 endif 545endif 546 547ifeq (${ERRATA_ABI_SUPPORT}, 1) 548include plat/arm/board/fvp/fvp_cpu_errata.mk 549endif 550 551# Build macro necessary for running SPM tests on FVP platform 552$(eval $(call add_define,PLAT_TEST_SPM)) 553