1/* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x4_2726228 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR 32workaround_runtime_end cortex_x4, ERRATUM(2726228) 33 34check_erratum_custom_start cortex_x4, ERRATUM(2726228) 35 36 /* This erratum needs to be enabled for r0p0 and r0p1. 37 * Check if revision is less than or equal to r0p1. 38 */ 39 40#if ERRATA_X4_2726228 41 mov x1, #1 42 b cpu_rev_var_ls 43#else 44 mov x0, #ERRATA_MISSING 45#endif 46 ret 47check_erratum_custom_end cortex_x4, ERRATUM(2726228) 48 49workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 50 /* dsb before isb of power down sequence */ 51 dsb sy 52workaround_runtime_end cortex_x4, ERRATUM(2740089) 53 54check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 55 56workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 57 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 58workaround_reset_end cortex_x4, ERRATUM(2763018) 59 60check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 61 62workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 63 mrs x1, id_aa64pfr1_el1 64 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 65 cbz x2, #1f 66 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 671: 68workaround_reset_end cortex_x4, ERRATUM(2816013) 69 70check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 71 72workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 73#if IMAGE_BL31 74 /* 75 * The Cortex X4 generic vectors are overridden to apply errata 76 * mitigation on exception entry from lower ELs. 77 */ 78 override_vector_table wa_cve_vbar_cortex_x4 79#endif /* IMAGE_BL31 */ 80workaround_reset_end cortex_x4, CVE(2022, 23960) 81 82check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 83 84cpu_reset_func_start cortex_x4 85 /* Disable speculative loads */ 86 msr SSBS, xzr 87cpu_reset_func_end cortex_x4 88 89 /* ---------------------------------------------------- 90 * HW will do the cache maintenance while powering down 91 * ---------------------------------------------------- 92 */ 93func cortex_x4_core_pwr_dwn 94 /* --------------------------------------------------- 95 * Enable CPU power down bit in power control register 96 * --------------------------------------------------- 97 */ 98 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 99 100 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 101 102 isb 103 ret 104endfunc cortex_x4_core_pwr_dwn 105 106errata_report_shim cortex_x4 107 108 /* --------------------------------------------- 109 * This function provides Cortex X4-specific 110 * register information for crash reporting. 111 * It needs to return with x6 pointing to 112 * a list of register names in ascii and 113 * x8 - x15 having values of registers to be 114 * reported. 115 * --------------------------------------------- 116 */ 117.section .rodata.cortex_x4_regs, "aS" 118cortex_x4_regs: /* The ascii list of register names to be reported */ 119 .asciz "cpuectlr_el1", "" 120 121func cortex_x4_cpu_reg_dump 122 adr x6, cortex_x4_regs 123 mrs x8, CORTEX_X4_CPUECTLR_EL1 124 ret 125endfunc cortex_x4_cpu_reg_dump 126 127declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 128 cortex_x4_reset_func, \ 129 cortex_x4_core_pwr_dwn 130