1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <drivers/clk.h> 7 #include <s32cc-clk-drv.h> 8 #include <s32cc-clk-ids.h> 9 #include <s32cc-clk-utils.h> 10 11 #define S32CC_FXOSC_FREQ (40U * MHZ) 12 #define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ) 13 #define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ) 14 #define S32CC_A53_FREQ (1U * GHZ) 15 #define S32CC_XBAR_2X_FREQ (800U * MHZ) 16 #define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ) 17 #define S32CC_PERIPH_PLL_PHI3_FREQ (125U * MHZ) 18 19 static int enable_fxosc_clk(void) 20 { 21 int ret; 22 23 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); 24 if (ret != 0) { 25 return ret; 26 } 27 28 ret = clk_enable(S32CC_CLK_FXOSC); 29 if (ret != 0) { 30 return ret; 31 } 32 33 return ret; 34 } 35 36 static int enable_arm_pll(void) 37 { 38 int ret; 39 40 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC); 41 if (ret != 0) { 42 return ret; 43 } 44 45 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); 46 if (ret != 0) { 47 return ret; 48 } 49 50 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); 51 if (ret != 0) { 52 return ret; 53 } 54 55 ret = clk_enable(S32CC_CLK_ARM_PLL_VCO); 56 if (ret != 0) { 57 return ret; 58 } 59 60 ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0); 61 if (ret != 0) { 62 return ret; 63 } 64 65 return ret; 66 } 67 68 static int enable_periph_pll(void) 69 { 70 int ret; 71 72 ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC); 73 if (ret != 0) { 74 return ret; 75 } 76 77 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); 78 if (ret != 0) { 79 return ret; 80 } 81 82 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); 83 if (ret != 0) { 84 return ret; 85 } 86 87 ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO); 88 if (ret != 0) { 89 return ret; 90 } 91 92 ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3); 93 if (ret != 0) { 94 return ret; 95 } 96 97 return ret; 98 } 99 100 static int enable_a53_clk(void) 101 { 102 int ret; 103 104 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); 105 if (ret != 0) { 106 return ret; 107 } 108 109 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); 110 if (ret != 0) { 111 return ret; 112 } 113 114 ret = clk_enable(S32CC_CLK_A53_CORE); 115 if (ret != 0) { 116 return ret; 117 } 118 119 return ret; 120 } 121 122 static int enable_xbar_clk(void) 123 { 124 int ret; 125 126 ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1); 127 if (ret != 0) { 128 return ret; 129 } 130 131 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); 132 if (ret != 0) { 133 return ret; 134 } 135 136 ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1); 137 if (ret != 0) { 138 return ret; 139 } 140 141 ret = clk_enable(S32CC_CLK_XBAR_2X); 142 if (ret != 0) { 143 return ret; 144 } 145 146 return ret; 147 } 148 149 int s32cc_init_early_clks(void) 150 { 151 int ret; 152 153 s32cc_clk_register_drv(); 154 155 ret = enable_fxosc_clk(); 156 if (ret != 0) { 157 return ret; 158 } 159 160 ret = enable_arm_pll(); 161 if (ret != 0) { 162 return ret; 163 } 164 165 ret = enable_periph_pll(); 166 if (ret != 0) { 167 return ret; 168 } 169 170 ret = enable_a53_clk(); 171 if (ret != 0) { 172 return ret; 173 } 174 175 ret = enable_xbar_clk(); 176 if (ret != 0) { 177 return ret; 178 } 179 180 return ret; 181 } 182