1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv3.h> 14 #include <drivers/console.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/mmio.h> 18 #include <plat/common/platform.h> 19 #include <platform_def.h> 20 #include <pmu.h> 21 22 #include <cpus_on_fixed_addr.h> 23 #include <plat_pm_helpers.h> 24 #include <plat_private.h> 25 #include <pm_pd_regs.h> 26 #include <rk3588_clk.h> 27 #include <rockchip_sip_svc.h> 28 #include <secure.h> 29 #include <soc.h> 30 31 #define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf) 32 #define NONBOOT_CPUS_OFF_LOOP (500000) 33 34 #define DSUGRF_REG_CNT (0x78 / 4 + 1) 35 #define BCORE_GRF_REG_CNT (0x30 / 4 + 1) 36 #define LCORE_GRF_REG_CNT (0x30 / 4 + 1) 37 38 #define CENTER_GRF_REG_CNT (0x20 / 4 + 1) 39 40 static struct psram_data_t *psram_sleep_cfg = 41 (struct psram_data_t *)&sys_sleep_flag_sram; 42 43 static int8_t pd_repair_map[] = { 44 [PD_GPU] = PD_RPR_GPU, 45 [PD_NPU] = -1, 46 [PD_VCODEC] = -1, 47 [PD_NPUTOP] = PD_RPR_NPUTOP, 48 [PD_NPU1] = PD_RPR_NPU1, 49 [PD_NPU2] = PD_RPR_NPU2, 50 [PD_VENC0] = PD_RPR_VENC0, 51 [PD_VENC1] = PD_RPR_VENC1, 52 [PD_RKVDEC0] = PD_RPR_RKVDEC0, 53 [PD_RKVDEC1] = PD_RPR_RKVDEC1, 54 [PD_VDPU] = PD_RPR_VDPU, 55 [PD_RGA30] = PD_RPR_RGA30, 56 [PD_AV1] = PD_RPR_AV1, 57 [PD_VI] = PD_RPR_VI, 58 [PD_FEC] = PD_RPR_FEC, 59 [PD_ISP1] = PD_RPR_ISP1, 60 [PD_RGA31] = PD_RPR_RGA31, 61 [PD_VOP] = PD_RPR_VOP, 62 [PD_VO0] = PD_RPR_VO0, 63 [PD_VO1] = PD_RPR_VO1, 64 [PD_AUDIO] = PD_RPR_AUDIO, 65 [PD_PHP] = PD_RPR_PHP, 66 [PD_GMAC] = PD_RPR_GMAC, 67 [PD_PCIE] = PD_RPR_PCIE, 68 [PD_NVM] = -1, 69 [PD_NVM0] = PD_RPR_NVM0, 70 [PD_SDIO] = PD_RPR_SDIO, 71 [PD_USB] = PD_RPR_USB, 72 [PD_SECURE] = -1, 73 [PD_SDMMC] = PD_RPR_SDMMC, 74 [PD_CRYPTO] = PD_RPR_CRYPTO, 75 [PD_CENTER] = PD_RPR_CENTER, 76 [PD_DDR01] = PD_RPR_DDR01, 77 [PD_DDR23] = PD_RPR_DDR23, 78 }; 79 80 struct rk3588_sleep_ddr_data { 81 uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l; 82 uint32_t pmu_pd_st0, bus_idle_st0, qch_pwr_st; 83 uint32_t pmu2_vol_gate_con[3], pmu2_submem_gate_sft_con0; 84 uint32_t pmu2_bisr_con0; 85 uint32_t cpll_con0; 86 uint32_t cru_mode_con, busscru_mode_con; 87 uint32_t bussgrf_soc_con7; 88 uint32_t pmu0grf_soc_con0, pmu0grf_soc_con1, pmu0grf_soc_con3; 89 uint32_t pmu1grf_soc_con2, pmu1grf_soc_con7, pmu1grf_soc_con8, pmu1grf_soc_con9; 90 uint32_t pmu0sgrf_soc_con1; 91 uint32_t pmu1sgrf_soc_con14; 92 uint32_t ddrgrf_chn_con0[4], ddrgrf_chn_con1[4], 93 ddrgrf_chn_con2[4], pmu1_ddr_pwr_sft_con[4]; 94 uint32_t pmu1cru_clksel_con1; 95 }; 96 97 static struct rk3588_sleep_ddr_data ddr_data; 98 99 struct rk3588_sleep_pmusram_data { 100 uint32_t dsusgrf_soc_con[DSUSGRF_SOC_CON_CNT], 101 dsusgrf_ddr_hash_con[DSUSGRF_DDR_HASH_CON_CNT]; 102 uint32_t dsu_ddr_fw_rgn_reg[FIREWALL_DSU_RGN_CNT], 103 dsu_ddr_fw_mst_reg[FIREWALL_DSU_MST_CNT], 104 dsu_ddr_fw_con_reg[FIREWALL_DSU_CON_CNT]; 105 uint32_t busioc_gpio0b_iomux_h; 106 }; 107 108 static __pmusramdata struct rk3588_sleep_pmusram_data pmusram_data; 109 110 static __pmusramfunc void dsu_restore_early(void) 111 { 112 int i; 113 114 /* dsusgrf */ 115 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 116 mmio_write_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i), 117 WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); 118 119 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 120 mmio_write_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i), 121 pmusram_data.dsusgrf_ddr_hash_con[i]); 122 123 /* dsu ddr firewall */ 124 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 125 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i), 126 pmusram_data.dsu_ddr_fw_rgn_reg[i]); 127 128 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 129 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i), 130 pmusram_data.dsu_ddr_fw_mst_reg[i]); 131 132 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 133 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), 134 pmusram_data.dsu_ddr_fw_con_reg[i]); 135 } 136 137 static __pmusramfunc void ddr_resume(void) 138 { 139 dsu_restore_early(); 140 } 141 142 static void dsu_core_save(void) 143 { 144 int i; 145 146 /* dsusgrf */ 147 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) 148 pmusram_data.dsusgrf_soc_con[i] = 149 mmio_read_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i)); 150 151 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) 152 pmusram_data.dsusgrf_ddr_hash_con[i] = 153 mmio_read_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i)); 154 155 /* dsu ddr firewall */ 156 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) 157 pmusram_data.dsu_ddr_fw_rgn_reg[i] = 158 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i)); 159 160 for (i = 0; i < FIREWALL_DSU_MST_CNT; i++) 161 pmusram_data.dsu_ddr_fw_mst_reg[i] = 162 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(i)); 163 164 for (i = 0; i < FIREWALL_DSU_CON_CNT; i++) 165 pmusram_data.dsu_ddr_fw_con_reg[i] = 166 mmio_read_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i)); 167 168 pvtplls_suspend(); 169 pd_dsu_core_save(); 170 } 171 172 static void dsu_core_restore(void) 173 { 174 pd_dsu_core_restore(); 175 pvtplls_resume(); 176 } 177 178 static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PHPCRU_CLKGATE_CON_CNT + 179 SECURECRU_CLKGATE_CON_CNT + PMU1CRU_CLKGATE_CON_CNT]; 180 181 void clk_gate_con_save(void) 182 { 183 int i, j = 0; 184 185 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 186 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); 187 188 clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON); 189 190 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 191 clk_save[j] = mmio_read_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i)); 192 193 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 194 clk_save[j] = mmio_read_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i)); 195 } 196 197 void clk_gate_con_disable(void) 198 { 199 int i; 200 201 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) 202 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 203 204 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 0xffff0000); 205 206 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++) 207 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 0xffff0000); 208 209 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) 210 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); 211 } 212 213 void clk_gate_con_restore(void) 214 { 215 int i, j = 0; 216 217 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 218 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 219 WITH_16BITS_WMSK(clk_save[j])); 220 221 mmio_write_32(PHP_CRU_BASE + PHPCRU_CLKGATE_CON, 222 WITH_16BITS_WMSK(clk_save[j])); 223 224 for (i = 0; i < SECURECRU_CLKGATE_CON_CNT; i++, j++) 225 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 226 WITH_16BITS_WMSK(clk_save[j])); 227 228 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 229 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 230 WITH_16BITS_WMSK(clk_save[j])); 231 } 232 233 static void pmu_bus_idle_req(uint32_t bus, uint32_t state) 234 { 235 uint32_t wait_cnt = 0; 236 237 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), 238 BITS_WITH_WMASK(state, 0x1, bus % 16)); 239 240 while (pmu_bus_idle_st(bus) != state || 241 pmu_bus_idle_ack(bus) != state) { 242 if (++wait_cnt > BUS_IDLE_LOOP) 243 break; 244 udelay(1); 245 } 246 247 if (wait_cnt > BUS_IDLE_LOOP) 248 WARN("%s: can't wait state %d for bus %d (0x%x)\n", 249 __func__, state, bus, 250 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); 251 } 252 253 static void pmu_qch_pwr_ctlr(uint32_t msk, uint32_t state) 254 { 255 uint32_t wait_cnt = 0; 256 257 if (state != 0) 258 state = msk; 259 260 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, 261 BITS_WITH_WMASK(state, msk, 0)); 262 263 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { 264 if (++wait_cnt > QCH_PWR_LOOP) 265 break; 266 udelay(1); 267 } 268 269 if (wait_cnt > BUS_IDLE_LOOP) 270 WARN("%s: can't wait qch:0x%x to state:0x%x (0x%x)\n", 271 __func__, msk, state, 272 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); 273 } 274 275 static inline uint32_t pmu_power_domain_chain_st(uint32_t pd) 276 { 277 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? 278 pmu_pd_on : 279 pmu_pd_off; 280 } 281 282 static inline uint32_t pmu_power_domain_mem_st(uint32_t pd) 283 { 284 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? 285 pmu_pd_off : 286 pmu_pd_on; 287 } 288 289 static inline uint32_t pmu_power_domain_st(uint32_t pd) 290 { 291 int8_t pd_repair = pd_repair_map[pd]; 292 293 if (pd_repair >= 0) 294 return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? 295 pmu_pd_on : 296 pmu_pd_off; 297 else 298 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? 299 pmu_pd_off : 300 pmu_pd_on; 301 } 302 303 static int pmu_power_domain_pd_to_mem_st(uint32_t pd, uint32_t *pd_mem_st) 304 { 305 uint32_t mem_st; 306 307 switch (pd) { 308 case PD_NPUTOP: 309 mem_st = PD_NPU_TOP_MEM_ST; 310 break; 311 case PD_NPU1: 312 mem_st = PD_NPU1_MEM_ST; 313 break; 314 case PD_NPU2: 315 mem_st = PD_NPU2_MEM_ST; 316 break; 317 case PD_VENC0: 318 mem_st = PD_VENC0_MEM_ST; 319 break; 320 case PD_VENC1: 321 mem_st = PD_VENC1_MEM_ST; 322 break; 323 case PD_RKVDEC0: 324 mem_st = PD_RKVDEC0_MEM_ST; 325 break; 326 case PD_RKVDEC1: 327 mem_st = PD_RKVDEC1_MEM_ST; 328 break; 329 case PD_RGA30: 330 mem_st = PD_RGA30_MEM_ST; 331 break; 332 case PD_AV1: 333 mem_st = PD_AV1_MEM_ST; 334 break; 335 case PD_VI: 336 mem_st = PD_VI_MEM_ST; 337 break; 338 case PD_FEC: 339 mem_st = PD_FEC_MEM_ST; 340 break; 341 case PD_ISP1: 342 mem_st = PD_ISP1_MEM_ST; 343 break; 344 case PD_RGA31: 345 mem_st = PD_RGA31_MEM_ST; 346 break; 347 case PD_VOP: 348 mem_st = PD_VOP_MEM_ST; 349 break; 350 case PD_VO0: 351 mem_st = PD_VO0_MEM_ST; 352 break; 353 case PD_VO1: 354 mem_st = PD_VO1_MEM_ST; 355 break; 356 case PD_AUDIO: 357 mem_st = PD_AUDIO_MEM_ST; 358 break; 359 case PD_PHP: 360 mem_st = PD_PHP_MEM_ST; 361 break; 362 case PD_GMAC: 363 mem_st = PD_GMAC_MEM_ST; 364 break; 365 case PD_PCIE: 366 mem_st = PD_PCIE_MEM_ST; 367 break; 368 case PD_NVM0: 369 mem_st = PD_NVM0_MEM_ST; 370 break; 371 case PD_SDIO: 372 mem_st = PD_SDIO_MEM_ST; 373 break; 374 case PD_USB: 375 mem_st = PD_USB_MEM_ST; 376 break; 377 case PD_SDMMC: 378 mem_st = PD_SDMMC_MEM_ST; 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 *pd_mem_st = mem_st; 385 386 return 0; 387 } 388 389 static int pmu_power_domain_reset_mem(uint32_t pd, uint32_t pd_mem_st) 390 { 391 uint32_t loop = 0; 392 int ret = 0; 393 394 while (pmu_power_domain_chain_st(pd_mem_st) != pmu_pd_on) { 395 udelay(1); 396 loop++; 397 if (loop >= PD_CTR_LOOP) { 398 WARN("%s: %d chain up time out\n", __func__, pd); 399 ret = -EINVAL; 400 goto error; 401 } 402 } 403 404 udelay(60); 405 406 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 407 BITS_WITH_WMASK(pmu_pd_off, 0x1, pd % 16)); 408 dsb(); 409 410 loop = 0; 411 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_off) { 412 udelay(1); 413 loop++; 414 if (loop >= PD_CTR_LOOP) { 415 WARN("%s: %d mem down time out\n", __func__, pd); 416 ret = -EINVAL; 417 goto error; 418 } 419 } 420 421 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), 422 BITS_WITH_WMASK(pmu_pd_on, 0x1, pd % 16)); 423 dsb(); 424 425 loop = 0; 426 while (pmu_power_domain_mem_st(pd_mem_st) != pmu_pd_on) { 427 udelay(1); 428 loop++; 429 if (loop >= PD_CTR_LOOP) { 430 WARN("%s: %d mem up time out\n", __func__, pd); 431 ret = -EINVAL; 432 goto error; 433 } 434 } 435 436 return 0; 437 438 error: 439 return ret; 440 } 441 442 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 443 { 444 uint32_t loop = 0; 445 uint32_t is_mem_on = pmu_pd_off; 446 uint32_t pd_mem_st; 447 int ret = 0; 448 449 if (pd_state == pmu_pd_on) { 450 ret = pmu_power_domain_pd_to_mem_st(pd, &pd_mem_st); 451 if (ret == 0) { 452 is_mem_on = pmu_power_domain_mem_st(pd_mem_st); 453 if (is_mem_on == pmu_pd_on) 454 WARN("%s: %d mem is up\n", __func__, pd); 455 } 456 } 457 458 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), 459 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); 460 dsb(); 461 462 if (is_mem_on == pmu_pd_on) { 463 ret = pmu_power_domain_reset_mem(pd, pd_mem_st); 464 if (ret != 0) 465 goto out; 466 WARN("%s: %d mem reset ok\n", __func__, pd); 467 } 468 469 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 470 udelay(1); 471 loop++; 472 } 473 474 if (pmu_power_domain_st(pd) != pd_state) { 475 WARN("%s: %d, %d, (0x%x, 0x%x) error!\n", __func__, pd, pd_state, 476 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)), 477 mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4))); 478 ret = -EINVAL; 479 } 480 481 out: 482 return ret; 483 } 484 485 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 486 { 487 uint32_t state; 488 489 if (pmu_power_domain_st(pd_id) == pd_state) 490 goto out; 491 492 if (pd_state == pmu_pd_on) 493 pmu_power_domain_ctr(pd_id, pd_state); 494 495 state = (pd_state == pmu_pd_off) ? bus_idle : bus_active; 496 497 switch (pd_id) { 498 case PD_GPU: 499 pmu_bus_idle_req(BUS_ID_GPU, state); 500 break; 501 case PD_NPUTOP: 502 pmu_bus_idle_req(BUS_ID_NPUTOP, state); 503 break; 504 case PD_NPU1: 505 pmu_bus_idle_req(BUS_ID_NPU1, state); 506 break; 507 case PD_NPU2: 508 pmu_bus_idle_req(BUS_ID_NPU2, state); 509 break; 510 case PD_VENC0: 511 pmu_bus_idle_req(BUS_ID_RKVENC0, state); 512 break; 513 case PD_VENC1: 514 pmu_bus_idle_req(BUS_ID_RKVENC1, state); 515 break; 516 case PD_RKVDEC0: 517 pmu_bus_idle_req(BUS_ID_RKVDEC0, state); 518 break; 519 case PD_RKVDEC1: 520 pmu_bus_idle_req(BUS_ID_RKVDEC1, state); 521 break; 522 case PD_VDPU: 523 pmu_bus_idle_req(BUS_ID_VDPU, state); 524 break; 525 case PD_AV1: 526 pmu_bus_idle_req(BUS_ID_AV1, state); 527 break; 528 case PD_VI: 529 pmu_bus_idle_req(BUS_ID_VI, state); 530 break; 531 case PD_ISP1: 532 pmu_bus_idle_req(BUS_ID_ISP, state); 533 break; 534 case PD_RGA31: 535 pmu_bus_idle_req(BUS_ID_RGA31, state); 536 break; 537 case PD_VOP: 538 pmu_bus_idle_req(BUS_ID_VOP_CHANNEL, state); 539 pmu_bus_idle_req(BUS_ID_VOP, state); 540 break; 541 case PD_VO0: 542 pmu_bus_idle_req(BUS_ID_VO0, state); 543 break; 544 case PD_VO1: 545 pmu_bus_idle_req(BUS_ID_VO1, state); 546 break; 547 case PD_AUDIO: 548 pmu_bus_idle_req(BUS_ID_AUDIO, state); 549 break; 550 case PD_PHP: 551 pmu_bus_idle_req(BUS_ID_PHP, state); 552 break; 553 case PD_NVM: 554 pmu_bus_idle_req(BUS_ID_NVM, state); 555 break; 556 case PD_SDIO: 557 pmu_bus_idle_req(BUS_ID_SDIO, state); 558 break; 559 case PD_USB: 560 pmu_bus_idle_req(BUS_ID_USB, state); 561 break; 562 case PD_SECURE: 563 pmu_bus_idle_req(BUS_ID_SECURE, state); 564 break; 565 default: 566 break; 567 } 568 569 if (pd_state == pmu_pd_off) 570 pmu_power_domain_ctr(pd_id, pd_state); 571 572 out: 573 return 0; 574 } 575 576 static void pmu_power_domains_suspend(void) 577 { 578 ddr_data.qch_pwr_st = 579 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & PMU2_QCH_PWR_MSK; 580 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); 581 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); 582 583 qos_save(); 584 585 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 586 pd_php_save(); 587 588 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 589 pd_crypto_save(); 590 591 pmu_qch_pwr_ctlr(0x20, 1); 592 pmu_qch_pwr_ctlr(0x40, 1); 593 pmu_qch_pwr_ctlr(0x1, 1); 594 pmu_qch_pwr_ctlr(0x2, 1); 595 pmu_qch_pwr_ctlr(0x4, 1); 596 pmu_qch_pwr_ctlr(0x8, 1); 597 pmu_qch_pwr_ctlr(0x10, 1); 598 599 pmu_bus_idle_req(BUS_ID_VO1USBTOP, bus_idle); 600 pmu_bus_idle_req(BUS_ID_SECURE_VO1USB_CHANNEL, bus_idle); 601 602 pmu_bus_idle_req(BUS_ID_USB, bus_idle); 603 604 pmu_set_power_domain(PD_GPU, pmu_pd_off); 605 606 pmu_set_power_domain(PD_NPU1, pmu_pd_off); 607 pmu_set_power_domain(PD_NPU2, pmu_pd_off); 608 pmu_set_power_domain(PD_NPUTOP, pmu_pd_off); 609 pmu_set_power_domain(PD_NPU, pmu_pd_off); 610 611 pmu_set_power_domain(PD_RKVDEC1, pmu_pd_off); 612 pmu_set_power_domain(PD_RKVDEC0, pmu_pd_off); 613 pmu_set_power_domain(PD_VENC1, pmu_pd_off); 614 pmu_set_power_domain(PD_VENC0, pmu_pd_off); 615 pmu_set_power_domain(PD_VCODEC, pmu_pd_off); 616 617 pmu_set_power_domain(PD_RGA30, pmu_pd_off); 618 pmu_set_power_domain(PD_AV1, pmu_pd_off); 619 pmu_set_power_domain(PD_VDPU, pmu_pd_off); 620 621 pmu_set_power_domain(PD_VO0, pmu_pd_off); 622 pmu_set_power_domain(PD_VO1, pmu_pd_off); 623 pmu_set_power_domain(PD_VOP, pmu_pd_off); 624 625 pmu_set_power_domain(PD_FEC, pmu_pd_off); 626 pmu_set_power_domain(PD_ISP1, pmu_pd_off); 627 pmu_set_power_domain(PD_VI, pmu_pd_off); 628 629 pmu_set_power_domain(PD_RGA31, pmu_pd_off); 630 631 pmu_set_power_domain(PD_AUDIO, pmu_pd_off); 632 633 pmu_set_power_domain(PD_GMAC, pmu_pd_off); 634 pmu_set_power_domain(PD_PCIE, pmu_pd_off); 635 pmu_set_power_domain(PD_PHP, pmu_pd_off); 636 637 pmu_set_power_domain(PD_SDIO, pmu_pd_off); 638 639 pmu_set_power_domain(PD_NVM0, pmu_pd_off); 640 pmu_set_power_domain(PD_NVM, pmu_pd_off); 641 642 pmu_set_power_domain(PD_SDMMC, pmu_pd_off); 643 pmu_set_power_domain(PD_CRYPTO, pmu_pd_off); 644 } 645 646 static void pmu_power_domains_resume(void) 647 { 648 int i; 649 650 pmu_set_power_domain(PD_CRYPTO, !!(ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO))); 651 pmu_set_power_domain(PD_SDMMC, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDMMC))); 652 653 pmu_set_power_domain(PD_NVM, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM))); 654 pmu_set_power_domain(PD_NVM0, !!(ddr_data.pmu_pd_st0 & BIT(PD_NVM0))); 655 656 pmu_set_power_domain(PD_SDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_SDIO))); 657 658 pmu_set_power_domain(PD_PHP, !!(ddr_data.pmu_pd_st0 & BIT(PD_PHP))); 659 pmu_set_power_domain(PD_PCIE, !!(ddr_data.pmu_pd_st0 & BIT(PD_PCIE))); 660 pmu_set_power_domain(PD_GMAC, !!(ddr_data.pmu_pd_st0 & BIT(PD_GMAC))); 661 662 pmu_set_power_domain(PD_AUDIO, !!(ddr_data.pmu_pd_st0 & BIT(PD_AUDIO))); 663 664 pmu_set_power_domain(PD_USB, !!(ddr_data.pmu_pd_st0 & BIT(PD_USB))); 665 666 pmu_set_power_domain(PD_RGA31, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA31))); 667 668 pmu_set_power_domain(PD_VI, !!(ddr_data.pmu_pd_st0 & BIT(PD_VI))); 669 pmu_set_power_domain(PD_ISP1, !!(ddr_data.pmu_pd_st0 & BIT(PD_ISP1))); 670 pmu_set_power_domain(PD_FEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_FEC))); 671 672 pmu_set_power_domain(PD_VOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_VOP))); 673 674 pmu_set_power_domain(PD_VO1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO1))); 675 676 pmu_set_power_domain(PD_VO0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VO0))); 677 678 pmu_set_power_domain(PD_VDPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_VDPU))); 679 pmu_set_power_domain(PD_AV1, !!(ddr_data.pmu_pd_st0 & BIT(PD_AV1))); 680 pmu_set_power_domain(PD_RGA30, !!(ddr_data.pmu_pd_st0 & BIT(PD_RGA30))); 681 682 pmu_set_power_domain(PD_VCODEC, !!(ddr_data.pmu_pd_st0 & BIT(PD_VCODEC))); 683 pmu_set_power_domain(PD_VENC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC0))); 684 pmu_set_power_domain(PD_VENC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_VENC1))); 685 pmu_set_power_domain(PD_RKVDEC0, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC0))); 686 pmu_set_power_domain(PD_RKVDEC1, !!(ddr_data.pmu_pd_st0 & BIT(PD_RKVDEC1))); 687 688 pmu_set_power_domain(PD_NPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU))); 689 pmu_set_power_domain(PD_NPUTOP, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPUTOP))); 690 pmu_set_power_domain(PD_NPU2, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU2))); 691 pmu_set_power_domain(PD_NPU1, !!(ddr_data.pmu_pd_st0 & BIT(PD_NPU1))); 692 693 pmu_set_power_domain(PD_GPU, !!(ddr_data.pmu_pd_st0 & BIT(PD_GPU))); 694 695 for (i = 0; i < 32; i++) 696 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st0 & BIT(i))); 697 698 pmu_qch_pwr_ctlr(0x10, !!(ddr_data.qch_pwr_st & 0x10)); 699 pmu_qch_pwr_ctlr(0x8, !!(ddr_data.qch_pwr_st & 0x8)); 700 pmu_qch_pwr_ctlr(0x4, !!(ddr_data.qch_pwr_st & 0x4)); 701 pmu_qch_pwr_ctlr(0x2, !!(ddr_data.qch_pwr_st & 0x2)); 702 pmu_qch_pwr_ctlr(0x1, !!(ddr_data.qch_pwr_st & 0x1)); 703 pmu_qch_pwr_ctlr(0x40, !!(ddr_data.qch_pwr_st & 0x40)); 704 pmu_qch_pwr_ctlr(0x20, !!(ddr_data.qch_pwr_st & 0x20)); 705 706 if ((ddr_data.pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) 707 pd_crypto_restore(); 708 709 if ((ddr_data.pmu_pd_st0 & BIT(PD_PHP)) == 0) 710 pd_php_restore(); 711 712 qos_restore(); 713 } 714 715 static int cpus_power_domain_on(uint32_t cpu_id) 716 { 717 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 718 BITS_WITH_WMASK(0, 0x1, core_pm_en)); 719 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 720 BITS_WITH_WMASK(1, 0x1, core_pm_sft_wakeup_en)); 721 dsb(); 722 723 return 0; 724 } 725 726 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 727 { 728 uint32_t apm_value = BIT(core_pm_en); 729 730 if (pd_cfg == core_pwr_wfi_int) 731 apm_value |= BIT(core_pm_int_wakeup_en); 732 733 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 734 BITS_WITH_WMASK(apm_value, 0x3, 0)); 735 dsb(); 736 737 return 0; 738 } 739 740 static inline void cpus_pd_req_enter_wfi(void) 741 { 742 /* CORTEX_A55_CPUACTLR_EL1 */ 743 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 744 "mrs x0, S3_0_C15_C2_7\n" 745 "orr x0, x0, #0x1\n" 746 "msr S3_0_C15_C2_7, x0\n" 747 "wfi_loop:\n" 748 "isb\n" 749 "wfi\n" 750 "b wfi_loop\n"); 751 } 752 753 static void nonboot_cpus_off(void) 754 { 755 uint32_t boot_cpu, cpu, tmp; 756 uint32_t exp_st; 757 uint32_t bcore0_rst_msk = 0, bcore1_rst_msk = 0; 758 int wait_cnt; 759 760 bcore0_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 761 bcore1_rst_msk = CRU_BIGCPU02_RST_MSK | CRU_BIGCPU13_RST_MSK; 762 763 mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); 764 mmio_write_32(BIGCORE1CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore1_rst_msk, 0)); 765 766 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 767 exp_st = SYS_GRF_BIG_CPUS_WFE; 768 do { 769 wait_cnt--; 770 tmp = mmio_read_32(SYSGRF_BASE + SYS_GRF_SOC_STATUS(3)); 771 tmp &= SYS_GRF_BIG_CPUS_WFE; 772 } while (tmp != exp_st && wait_cnt); 773 774 boot_cpu = plat_my_core_pos(); 775 776 /* turn off noboot cpus */ 777 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 778 if (cpu == boot_cpu) 779 continue; 780 cpus_power_domain_off(cpu, core_pwr_wfi); 781 } 782 783 mmio_write_32(SRAM_BASE + 0x08, (uintptr_t)&cpus_pd_req_enter_wfi); 784 mmio_write_32(SRAM_BASE + 0x04, 0xdeadbeaf); 785 786 dsb(); 787 isb(); 788 789 sev(); 790 791 wait_cnt = NONBOOT_CPUS_OFF_LOOP; 792 do { 793 wait_cnt--; 794 tmp = mmio_read_32(PMU_BASE + PMU2_CLUSTER_ST); 795 tmp &= CLUSTER_STS_NONBOOT_CPUS_DWN; 796 } while (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN && wait_cnt); 797 798 if (tmp != CLUSTER_STS_NONBOOT_CPUS_DWN) 799 ERROR("nonboot cpus status(%x) error!\n", tmp); 800 } 801 802 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, 803 uint64_t entrypoint) 804 { 805 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 806 807 assert(cpu_id < PLATFORM_CORE_COUNT); 808 assert(cpuson_flags[cpu_id] == 0); 809 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 810 cpuson_entry_point[cpu_id] = entrypoint; 811 dsb(); 812 813 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 814 flush_dcache_range((uintptr_t)cpuson_entry_point, 815 sizeof(cpuson_entry_point)); 816 dsb(); 817 isb(); 818 819 cpus_power_domain_on(cpu_id); 820 821 return PSCI_E_SUCCESS; 822 } 823 824 int rockchip_soc_cores_pwr_dm_on_finish(void) 825 { 826 uint32_t cpu_id = plat_my_core_pos(); 827 828 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 829 BITS_WITH_WMASK(0, 0xf, 0)); 830 831 return PSCI_E_SUCCESS; 832 } 833 834 int rockchip_soc_cores_pwr_dm_off(void) 835 { 836 uint32_t cpu_id = plat_my_core_pos(); 837 838 cpus_power_domain_off(cpu_id, core_pwr_wfi); 839 840 return PSCI_E_SUCCESS; 841 } 842 843 int rockchip_soc_cores_pwr_dm_suspend(void) 844 { 845 uint32_t cpu_id = plat_my_core_pos(); 846 847 assert(cpu_id < PLATFORM_CORE_COUNT); 848 849 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 850 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 851 dsb(); 852 flush_dcache_range((uintptr_t)cpuson_flags, sizeof(cpuson_flags)); 853 flush_dcache_range((uintptr_t)cpuson_entry_point, 854 sizeof(cpuson_entry_point)); 855 dsb(); 856 isb(); 857 858 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 859 860 __asm__ volatile ("msr DBGPRCR_EL1, xzr\n" 861 "mrs x0, S3_0_C15_C2_7\n" 862 "orr x0, x0, #0x1\n" 863 "msr S3_0_C15_C2_7, x0\n"); 864 865 return PSCI_E_SUCCESS; 866 } 867 868 int rockchip_soc_cores_pwr_dm_resume(void) 869 { 870 uint32_t cpu_id = plat_my_core_pos(); 871 872 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 873 BITS_WITH_WMASK(0, 0x3, 0)); 874 875 dsb(); 876 877 return PSCI_E_SUCCESS; 878 } 879 880 static void ddr_sleep_config(void) 881 { 882 int i; 883 884 if (pmu_power_domain_st(PD_DDR01) == 0) { 885 ddr_data.ddrgrf_chn_con0[0] = 886 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0)); 887 ddr_data.ddrgrf_chn_con0[1] = 888 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0)); 889 ddr_data.ddrgrf_chn_con1[0] = 890 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1)); 891 ddr_data.ddrgrf_chn_con1[1] = 892 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1)); 893 ddr_data.ddrgrf_chn_con2[0] = 894 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2)); 895 ddr_data.ddrgrf_chn_con2[1] = 896 mmio_read_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2)); 897 898 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 899 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 900 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 901 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 902 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 903 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 904 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 905 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 906 } 907 908 if (pmu_power_domain_st(PD_DDR23) == 0) { 909 ddr_data.ddrgrf_chn_con0[2] = 910 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0)); 911 ddr_data.ddrgrf_chn_con0[3] = 912 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0)); 913 ddr_data.ddrgrf_chn_con1[2] = 914 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1)); 915 ddr_data.ddrgrf_chn_con1[3] = 916 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1)); 917 ddr_data.ddrgrf_chn_con2[2] = 918 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2)); 919 ddr_data.ddrgrf_chn_con2[3] = 920 mmio_read_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2)); 921 922 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x20002000); 923 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x20002000); 924 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 0x08000000); 925 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 0x08000000); 926 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 0x00200020); 927 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 0x00200020); 928 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 0x00400040); 929 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 0x00400040); 930 } 931 932 for (i = 0; i < DDR_CHN_CNT; i++) { 933 ddr_data.pmu1_ddr_pwr_sft_con[i] = 934 mmio_read_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i)); 935 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 0x0fff0900); 936 } 937 } 938 939 static void ddr_sleep_config_restore(void) 940 { 941 int i; 942 943 for (i = 0; i < DDR_CHN_CNT; i++) { 944 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 945 0x0fff0000 | ddr_data.pmu1_ddr_pwr_sft_con[i]); 946 } 947 948 if (pmu_power_domain_st(PD_DDR01) == 0) { 949 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(1), 950 0x00400000 | ddr_data.ddrgrf_chn_con1[0]); 951 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(1), 952 0x00400000 | ddr_data.ddrgrf_chn_con1[1]); 953 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(0), 954 0x00200000 | ddr_data.ddrgrf_chn_con0[0]); 955 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(0), 956 0x00200000 | ddr_data.ddrgrf_chn_con0[1]); 957 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHA_CON(2), 958 0x28000000 | ddr_data.ddrgrf_chn_con2[0]); 959 mmio_write_32(DDR01GRF_BASE + DDRGRF_CHB_CON(2), 960 0x28000000 | ddr_data.ddrgrf_chn_con2[1]); 961 } 962 963 if (pmu_power_domain_st(PD_DDR23) == 0) { 964 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(1), 965 0x00400000 | ddr_data.ddrgrf_chn_con1[2]); 966 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(1), 967 0x00400000 | ddr_data.ddrgrf_chn_con1[3]); 968 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(0), 969 0x00200000 | ddr_data.ddrgrf_chn_con0[2]); 970 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(0), 971 0x00200000 | ddr_data.ddrgrf_chn_con0[3]); 972 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHA_CON(2), 973 0x28000000 | ddr_data.ddrgrf_chn_con2[2]); 974 mmio_write_32(DDR23GRF_BASE + DDRGRF_CHB_CON(2), 975 0x28000000 | ddr_data.ddrgrf_chn_con2[3]); 976 } 977 } 978 979 static void pmu_sleep_config(void) 980 { 981 uint32_t pmu1_pwr_con, pmu1_wkup_int_con, pmu1_cru_pwr_con; 982 uint32_t pmu1_ddr_pwr_con, pmu1_pll_pd_con[2] = {0}; 983 uint32_t pmu2_dsu_pwr_con, pmu2_core_pwr_con, pmu2_clst_idle_con; 984 uint32_t pmu2_bus_idle_con[3] = {0}, pmu2_pwr_gate_con[3] = {0}; 985 uint32_t pmu2_vol_gate_con[3] = {0}, pmu2_qch_pwr_con = 0; 986 int i; 987 988 ddr_data.pmu1grf_soc_con7 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7)); 989 ddr_data.pmu1grf_soc_con8 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8)); 990 ddr_data.pmu1grf_soc_con9 = mmio_read_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9)); 991 ddr_data.pmu1sgrf_soc_con14 = mmio_read_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14)); 992 ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); 993 ddr_data.pmu0grf_soc_con1 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1)); 994 995 ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); 996 ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); 997 ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); 998 999 ddr_data.pmu2_submem_gate_sft_con0 = 1000 mmio_read_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0)); 1001 1002 /* save pmic_sleep iomux gpio0_a4 */ 1003 ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); 1004 ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); 1005 ddr_data.pmu0grf_soc_con3 = mmio_read_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3)); 1006 1007 /* PMU1 repair disable */ 1008 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(0), 0x00010000); 1009 1010 /* set pmic_sleep iomux */ 1011 mmio_write_32(PMU0IOC_BASE + 0, 1012 BITS_WITH_WMASK(1, 0xf, 8) | 1013 BITS_WITH_WMASK(1, 0xfu, 12)); 1014 1015 /* set tsadc_shut_m0 pin iomux to gpio */ 1016 mmio_write_32(PMU0IOC_BASE + 0, 1017 BITS_WITH_WMASK(0, 0xf, 4)); 1018 1019 /* set spi2_cs0/1 pin iomux to gpio */ 1020 mmio_write_32(PMU0IOC_BASE + 8, 1021 BITS_WITH_WMASK(0, 0xff, 0)); 1022 1023 /* sleep 1~2 src select */ 1024 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1025 BITS_WITH_WMASK(0x8, 0xf, 0) | 1026 BITS_WITH_WMASK(0x8, 0xf, 4) | 1027 BITS_WITH_WMASK(0x0, 0x3, 8)); 1028 1029 pmu1_wkup_int_con = BIT(WAKEUP_GPIO0_INT_EN) | 1030 BIT(WAKEUP_CPU0_INT_EN); 1031 1032 pmu1_pwr_con = BIT(powermode_en); 1033 1034 pmu1_cru_pwr_con = 1035 BIT(alive_osc_mode_en) | 1036 BIT(power_off_en) | 1037 BIT(pd_clk_src_gate_en); 1038 1039 pmu1_ddr_pwr_con = 0; 1040 1041 pmu2_dsu_pwr_con = 1042 BIT(DSU_PWRDN_EN) | 1043 BIT(DSU_PWROFF_EN); 1044 1045 pmu2_core_pwr_con = BIT(CORE_PWRDN_EN); 1046 1047 pmu2_clst_idle_con = 1048 BIT(IDLE_REQ_BIGCORE0_EN) | 1049 BIT(IDLE_REQ_BIGCORE1_EN) | 1050 BIT(IDLE_REQ_DSU_EN) | 1051 BIT(IDLE_REQ_LITDSU_EN) | 1052 BIT(IDLE_REQ_ADB400_CORE_QCH_EN); 1053 1054 pmu1_pll_pd_con[0] = 1055 BIT(B0PLL_PD_EN) | 1056 BIT(B1PLL_PD_EN) | 1057 BIT(LPLL_PD_EN) | 1058 BIT(V0PLL_PD_EN) | 1059 BIT(AUPLL_PD_EN) | 1060 BIT(GPLL_PD_EN) | 1061 BIT(CPLL_PD_EN) | 1062 BIT(NPLL_PD_EN); 1063 1064 pmu1_pll_pd_con[1] = 1065 BIT(PPLL_PD_EN) | 1066 BIT(SPLL_PD_EN); 1067 1068 pmu2_bus_idle_con[0] = 0; 1069 1070 pmu2_bus_idle_con[1] = 1071 BIT(BUS_ID_SECURE - 16) | 1072 BIT(BUS_ID_SECURE_CENTER_CHANNEL - 16) | 1073 BIT(BUS_ID_CENTER_CHANNEL - 16); 1074 1075 pmu2_bus_idle_con[2] = 1076 BIT(BUS_ID_MSCH - 32) | 1077 BIT(BUS_ID_BUS - 32) | 1078 BIT(BUS_ID_TOP - 32); 1079 1080 pmu2_pwr_gate_con[0] = 0; 1081 pmu2_pwr_gate_con[1] = BIT(PD_SECURE - 16); 1082 pmu2_pwr_gate_con[2] = 0; 1083 1084 pmu2_qch_pwr_con = 0; 1085 1086 pmu2_vol_gate_con[0] = 0x7; 1087 pmu2_vol_gate_con[2] = 0; 1088 1089 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(0), 0x00030000); 1090 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(1), 0x00030000); 1091 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 1092 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1093 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 1094 WITH_16BITS_WMSK(pmu2_core_pwr_con)); 1095 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 1096 WITH_16BITS_WMSK(pmu2_clst_idle_con)); 1097 mmio_write_32(PMU_BASE + PMU2_DSU_AUTO_PWR_CON, 0x00030000); 1098 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 1099 WITH_16BITS_WMSK(pmu2_dsu_pwr_con)); 1100 1101 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000); 1102 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000); 1103 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 24000); 1104 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 24000); 1105 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 24000); 1106 mmio_write_32(PMU_BASE + PMU2_CORE0_STABLE_CNT_THRESH, 24000); 1107 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRUP_CNT_THRESH, 24000); 1108 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRDN_CNT_THRESH, 24000); 1109 mmio_write_32(PMU_BASE + PMU2_CORE1_STABLE_CNT_THRESH, 24000); 1110 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRUP_CNT_THRESH, 24000); 1111 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRDN_CNT_THRESH, 24000); 1112 mmio_write_32(PMU_BASE + PMU2_DSU_STABLE_CNT_THRESH, 24000); 1113 mmio_write_32(PMU_BASE + PMU2_DSU_PWRUP_CNT_THRESH, 24000); 1114 mmio_write_32(PMU_BASE + PMU2_DSU_PWRDN_CNT_THRESH, 24000); 1115 1116 /* Config pmu power mode and pmu wakeup source */ 1117 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 1118 BITS_WITH_WMASK(1, 0x1, 0)); 1119 1120 /* pmu1_pwr_con */ 1121 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 1122 WITH_16BITS_WMSK(pmu1_pwr_con)); 1123 1124 /* cru_pwr_con */ 1125 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON, 1126 WITH_16BITS_WMSK(pmu1_cru_pwr_con)); 1127 1128 /* wakeup source */ 1129 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); 1130 1131 /* ddr pwr con */ 1132 for (i = 0; i < DDR_CHN_CNT; i++) { 1133 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(i), 1134 WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); 1135 pmu2_bus_idle_con[1] |= 1136 BIT(BUS_ID_MSCH0 - 16 + i); 1137 } 1138 1139 /* pll_pd */ 1140 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 1141 WITH_16BITS_WMSK(pmu1_pll_pd_con[0])); 1142 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(1), 1143 WITH_16BITS_WMSK(pmu1_pll_pd_con[1])); 1144 1145 /* bypass cpu1~7*/ 1146 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0x00ff00fe); 1147 1148 /* bus idle */ 1149 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 1150 WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); 1151 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 1152 WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); 1153 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1154 WITH_16BITS_WMSK(pmu2_bus_idle_con[2])); 1155 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), 1156 0xf000f000); 1157 /* power gate */ 1158 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 1159 WITH_16BITS_WMSK(pmu2_pwr_gate_con[0])); 1160 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 1161 WITH_16BITS_WMSK(pmu2_pwr_gate_con[1])); 1162 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(2), 1163 WITH_16BITS_WMSK(pmu2_pwr_gate_con[2])); 1164 /* vol gate */ 1165 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1166 BITS_WITH_WMASK(pmu2_vol_gate_con[0], 0x7, 0)); 1167 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 0); 1168 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1169 BITS_WITH_WMASK(pmu2_vol_gate_con[2], 0x3, 0)); 1170 /* qch */ 1171 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_CON, 1172 BITS_WITH_WMASK(pmu2_qch_pwr_con, 0x7f, 0)); 1173 1174 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1175 0x000f000f); 1176 } 1177 1178 static void pmu_sleep_restore(void) 1179 { 1180 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(7), 1181 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con7)); 1182 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(8), 1183 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con8)); 1184 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(9), 1185 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con9)); 1186 mmio_write_32(PMU1SGRF_BASE + PMU1_SGRF_SOC_CON(14), 1187 WITH_16BITS_WMSK(ddr_data.pmu1sgrf_soc_con14)); 1188 1189 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1), 1190 WITH_16BITS_WMSK(ddr_data.pmu0sgrf_soc_con1)); 1191 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(1), 1192 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); 1193 1194 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 0xffff0000); 1195 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 0xffff0000); 1196 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); 1197 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 0xffff0000); 1198 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0xffff0000); 1199 1200 /* Must clear PMU1_WAKEUP_INT_CON because the wakeup source 1201 * in PMU1_WAKEUP_INT_CON will wakeup cpus in cpu_auto_pd state. 1202 */ 1203 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); 1204 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); 1205 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0x00010000); 1206 mmio_write_32(PMU_BASE + PMU0_WAKEUP_INT_CON, 0x00010000); 1207 mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); 1208 1209 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), 1210 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[0])); 1211 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 1212 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[1])); 1213 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), 1214 WITH_16BITS_WMSK(ddr_data.pmu2_vol_gate_con[2])); 1215 1216 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), 1217 WITH_16BITS_WMSK(ddr_data.pmu2_submem_gate_sft_con0)); 1218 1219 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 1220 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con3)); 1221 mmio_write_32(PMU1GRF_BASE + PMU1_GRF_SOC_CON(2), 1222 WITH_16BITS_WMSK(ddr_data.pmu1grf_soc_con2)); 1223 1224 mmio_write_32(PMU0IOC_BASE + 0x4, 1225 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); 1226 mmio_write_32(PMU0IOC_BASE + 0, 1227 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); 1228 } 1229 1230 static void soc_sleep_config(void) 1231 { 1232 ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); 1233 1234 pmu_sleep_config(); 1235 ddr_sleep_config(); 1236 } 1237 1238 static void soc_sleep_restore(void) 1239 { 1240 ddr_sleep_config_restore(); 1241 pmu_sleep_restore(); 1242 1243 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); 1244 } 1245 1246 static void pm_pll_suspend(void) 1247 { 1248 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); 1249 ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); 1250 ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); 1251 ddr_data.cpll_con0 = mmio_read_32(CRU_BASE + CRU_PLLS_CON(2, 0)); 1252 ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); 1253 1254 /* disable bisr_init */ 1255 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), BITS_WITH_WMASK(0, 0x1, 0)); 1256 /* cpll bypass */ 1257 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), BITS_WITH_WMASK(1u, 1u, 15)); 1258 } 1259 1260 static void pm_pll_restore(void) 1261 { 1262 pm_pll_wait_lock(CRU_BASE + CRU_PLLS_CON(2, 0)); 1263 1264 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); 1265 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); 1266 mmio_write_32(CRU_BASE + CRU_PLLS_CON(2, 0), WITH_16BITS_WMSK(ddr_data.cpll_con0)); 1267 dsb(); 1268 isb(); 1269 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); 1270 } 1271 1272 int rockchip_soc_sys_pwr_dm_suspend(void) 1273 { 1274 clk_gate_con_save(); 1275 clk_gate_con_disable(); 1276 1277 psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; 1278 1279 pmu_power_domains_suspend(); 1280 soc_sleep_config(); 1281 dsu_core_save(); 1282 pm_pll_suspend(); 1283 1284 return 0; 1285 } 1286 1287 int rockchip_soc_sys_pwr_dm_resume(void) 1288 { 1289 pm_pll_restore(); 1290 dsu_core_restore(); 1291 soc_sleep_restore(); 1292 pmu_power_domains_resume(); 1293 plat_rockchip_gic_cpuif_enable(); 1294 1295 psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; 1296 1297 clk_gate_con_restore(); 1298 1299 return 0; 1300 } 1301 1302 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(const 1303 psci_power_state_t *target_state) 1304 { 1305 psci_power_down_wfi(); 1306 } 1307 1308 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) 1309 { 1310 cpus_pd_req_enter_wfi(); 1311 psci_power_down_wfi(); 1312 } 1313 1314 void __dead2 rockchip_soc_soft_reset(void) 1315 { 1316 /* pll slow mode */ 1317 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); 1318 mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); 1319 mmio_write_32(BIGCORE0CRU_BASE + 0x300, 0x60000000); 1320 mmio_write_32(BIGCORE0CRU_BASE + 0x304, 0x00600000); 1321 mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); 1322 mmio_write_32(BIGCORE1CRU_BASE + 0x300, 0x60000000); 1323 mmio_write_32(BIGCORE1CRU_BASE + 0x304, 0x00600000); 1324 mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000); 1325 mmio_write_32(DSUCRU_BASE + 0x318, 0x30600000); 1326 mmio_write_32(DSUCRU_BASE + 0x31c, 0x30600000); 1327 mmio_write_32(DSUCRU_BASE + 0x304, 0x00010000); 1328 mmio_write_32(BUSSCRU_BASE + 0x280, 0x0003000); 1329 dsb(); 1330 isb(); 1331 1332 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 1333 1334 /* 1335 * Maybe the HW needs some times to reset the system, 1336 * so we do not hope the core to execute valid codes. 1337 */ 1338 psci_power_down_wfi(); 1339 } 1340 1341 void __dead2 rockchip_soc_system_off(void) 1342 { 1343 /* set pmic_sleep pin(gpio0_a2) to gpio mode */ 1344 mmio_write_32(PMU0IOC_BASE + 0, BITS_WITH_WMASK(0, 0xf, 8)); 1345 1346 /* config output */ 1347 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, 1348 BITS_WITH_WMASK(1, 0x1, 2)); 1349 1350 /* config output high level */ 1351 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, 1352 BITS_WITH_WMASK(1, 0x1, 2)); 1353 dsb(); 1354 1355 /* 1356 * Maybe the HW needs some times to reset the system, 1357 * so we do not hope the core to execute valid codes. 1358 */ 1359 psci_power_down_wfi(); 1360 } 1361 1362 static void rockchip_pmu_pd_init(void) 1363 { 1364 mmio_write_32(PMU_BASE + PMU2_BISR_CON(1), 0xffffffff); 1365 mmio_write_32(PMU_BASE + PMU2_BISR_CON(2), 0xffffffff); 1366 mmio_write_32(PMU_BASE + PMU2_BISR_CON(3), 0xffffffff); 1367 1368 pmu_set_power_domain(PD_PHP, pmu_pd_on); 1369 pmu_set_power_domain(PD_PCIE, pmu_pd_on); 1370 pmu_set_power_domain(PD_GMAC, pmu_pd_on); 1371 pmu_set_power_domain(PD_SECURE, pmu_pd_on); 1372 pmu_set_power_domain(PD_VOP, pmu_pd_on); 1373 pmu_set_power_domain(PD_VO0, pmu_pd_on); 1374 pmu_set_power_domain(PD_VO1, pmu_pd_on); 1375 } 1376 1377 #define PLL_LOCKED_TIMEOUT 600000U 1378 1379 void pm_pll_wait_lock(uint32_t pll_base) 1380 { 1381 int delay = PLL_LOCKED_TIMEOUT; 1382 1383 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) 1384 return; 1385 1386 while (delay-- >= 0) { 1387 if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & 1388 CRU_PLLCON6_LOCK_STATUS) 1389 break; 1390 udelay(1); 1391 } 1392 1393 if (delay <= 0) 1394 ERROR("Can't wait pll(0x%x) lock\n", pll_base); 1395 } 1396 1397 void rockchip_plat_mmu_el3(void) 1398 { 1399 /* Nothing todo */ 1400 } 1401 1402 void plat_rockchip_pmu_init(void) 1403 { 1404 int cpu; 1405 1406 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1407 cpuson_flags[cpu] = 0; 1408 1409 psram_sleep_cfg->sp = PSRAM_SP_TOP; 1410 psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; 1411 psram_sleep_cfg->ddr_data = 0; 1412 psram_sleep_cfg->ddr_flag = 0; 1413 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1414 psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; 1415 1416 nonboot_cpus_off(); 1417 1418 /* 1419 * When perform idle operation, corresponding clock can be 1420 * opened or gated automatically. 1421 */ 1422 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(0), 0xffffffff); 1423 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(1), 0xffffffff); 1424 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(2), 0x00070007); 1425 1426 rockchip_pmu_pd_init(); 1427 1428 /* grf_con_pmic_sleep_sel 1429 * pmic sleep function selection 1430 * 1'b0: From reset pulse generator, can reset external PMIC 1431 * 1'b1: From pmu block, only support sleep function for external PMIC 1432 */ 1433 mmio_write_32(PMU0GRF_BASE + PMU0_GRF_SOC_CON(3), 0x03ff0000); 1434 1435 /* pmusram remap to 0xffff0000 */ 1436 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); 1437 1438 pm_reg_rgns_init(); 1439 } 1440