1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 30 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 31workaround_reset_end cortex_a720, ERRATUM(2844092) 32 33check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 34 35workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 36/* Erratum 2926083 workaround is required only if SPE is enabled */ 37#if ENABLE_SPE_FOR_NS != 0 38 /* Check if Static profiling extension is implemented or present. */ 39 mrs x1, id_aa64dfr0_el1 40 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 41 cbz x0, 1f 42 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 43 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57) 44 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58) 451: 46#endif 47workaround_reset_end cortex_a720, ERRATUM(2926083) 48 49check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 50 51workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 52 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 53workaround_reset_end cortex_a720, ERRATUM(2940794) 54 55check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 56 57workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 58#if IMAGE_BL31 59 /* 60 * The Cortex A720 generic vectors are overridden to apply errata 61 * mitigation on exception entry from lower ELs. 62 */ 63 override_vector_table wa_cve_vbar_cortex_a720 64#endif /* IMAGE_BL31 */ 65workaround_reset_end cortex_a720, CVE(2022, 23960) 66 67check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 68 69cpu_reset_func_start cortex_a720 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72cpu_reset_func_end cortex_a720 73 74 /* ---------------------------------------------------- 75 * HW will do the cache maintenance while powering down 76 * ---------------------------------------------------- 77 */ 78func cortex_a720_core_pwr_dwn 79 /* --------------------------------------------------- 80 * Enable CPU power down bit in power control register 81 * --------------------------------------------------- 82 */ 83 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 84 85 isb 86 ret 87endfunc cortex_a720_core_pwr_dwn 88 89errata_report_shim cortex_a720 90 91 /* --------------------------------------------- 92 * This function provides Cortex A720-specific 93 * register information for crash reporting. 94 * It needs to return with x6 pointing to 95 * a list of register names in ascii and 96 * x8 - x15 having values of registers to be 97 * reported. 98 * --------------------------------------------- 99 */ 100.section .rodata.cortex_a720_regs, "aS" 101cortex_a720_regs: /* The ascii list of register names to be reported */ 102 .asciz "cpuectlr_el1", "" 103 104func cortex_a720_cpu_reg_dump 105 adr x6, cortex_a720_regs 106 mrs x8, CORTEX_A720_CPUECTLR_EL1 107 ret 108endfunc cortex_a720_cpu_reg_dump 109 110declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 111 cortex_a720_reset_func, \ 112 cortex_a720_core_pwr_dwn 113