| a4e31cf0 | 01-Apr-2025 |
Boerge Struempfel <boerge.struempfel@gmail.com> |
feat(fdts): add support for STM32MP257D-based ultra-fly-sbc board
This commit adds support for the ultra-fly-sbc board, a rapid proto-
typing reference board developed by Ultratronik GmbH. It featur
feat(fdts): add support for STM32MP257D-based ultra-fly-sbc board
This commit adds support for the ultra-fly-sbc board, a rapid proto-
typing reference board developed by Ultratronik GmbH. It features an
STM32MP257D SoC with 4 GiB LPDDR4, 8 GiB eMMC, and a microSD slot.
The board includes various UART, USB, SPI, and I2C ports/headers,
along with a multipurpose E-Key M.2 connector and two Microbus headers.
Additionally, the board supports LVDS, parallel, and MIPI-DSI video
output.
These DTS(i) files are based on the STM32MP257F-DK board.
TF-A has been fully tested on this board with the latest OP-TEE
developer setup.
Change-Id: I8fdc7fe570d9c5d37eb59e76808c3b1e5b708bc2
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
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| 83ec7e45 | 06-Nov-2024 |
Boyan Karatotev <boyan.karatotev@arm.com> |
perf(amu): greatly simplify AMU context management
The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness
perf(amu): greatly simplify AMU context management
The current code is incredibly resilient to updates to the spec and
has worked quite well so far. However, recent implementations expose a
weakness in that this is rather slow. A large part of it is written in
assembly, making it opaque to the compiler for optimisations. The
future proofness requires reading registers that are effectively
`volatile`, making it even harder for the compiler, as well as adding
lots of implicit barriers, making it hard for the microarchitecutre to
optimise as well.
We can make a few assumptions, checked by a few well placed asserts, and
remove a lot of this burden. For a start, at the moment there are 4
group 0 counters with static assignments. Contexting them is a trivial
affair that doesn't need a loop. Similarly, there can only be up to 16
group 1 counters. Contexting them is a bit harder, but we can do with a
single branch with a falling through switch. If/when both of these
change, we have a pair of asserts and the feature detection mechanism to
guard us against pretending that we support something we don't.
We can drop contexting of the offset registers. They are fully
accessible by EL2 and as such are its responsibility to preserve on
powerdown.
Another small thing we can do, is pass the core_pos into the hook.
The caller already knows which core we're running on, we don't need to
call this non-trivial function again.
Finally, knowing this, we don't really need the auxiliary AMUs to be
described by the device tree. Linux doesn't care at the moment, and any
information we need for EL3 can be neatly placed in a simple array.
All of this, combined with lifting the actual saving out of assembly,
reduces the instructions to save the context from 180 to 40, including a
lot fewer branches. The code is also much shorter and easier to read.
Also propagate to aarch32 so that the two don't diverge too much.
Change-Id: Ib62e6e9ba5be7fb9fb8965c8eee148d5598a5361
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| 2e55a3d7 | 21-Jan-2025 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
feat(fvp): change size of PCIe memory region 2
Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.
Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: Al
feat(fvp): change size of PCIe memory region 2
Change size of PCIe memory region 2 from 256GB
to 3GB to fit in 1TB of GPT PPS.
Change-Id: Ic769bb784dd17d390b54ccef53b7788334373cb4
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
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