docs: update maintainers file with active code owners

Removed an inactive code owner and added new active
code owners to the maintainers file.

Change-Id: Id06ab0c05e7c9926768981fcc426831eeeaab141
S

docs: update maintainers file with active code owners

Removed an inactive code owner and added new active
code owners to the maintainers file.

Change-Id: Id06ab0c05e7c9926768981fcc426831eeeaab141
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(cpufeat): add support for FEAT_PAUTH_LR" into integration

Merge "chore(tc): remove TC2 platform variant" into integration

Merge "docs(rmmd): document the EL3-RMM IDE KM Interface" into integration

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch updates the documentation for the EL3-RMM IDE KM interface,
addressing errors found in the previous version and fixed formatting
issues a

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch updates the documentation for the EL3-RMM IDE KM interface,
addressing errors found in the previous version and fixed formatting
issues and added missing details.

Change-Id: I84ff734d3de755fa793620e9b1446cf9b75763b0
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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docs(versal-net): update documentation for SDEI

Update documentation to specify tf-a build option with SDEI support.

Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <

docs(versal-net): update documentation for SDEI

Update documentation to specify tf-a build option with SDEI support.

Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported

feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported by arm clang compiler and not GCC.

Change-Id: I7db1e34b661ed95cad75850b62878ac5d98466ea
Signed-off-by: John Powell <john.powell@arm.com>

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docs: updates for playbook

Mention the dependencies than could be taken in TF-A.
Add a dedicated entry for the other repositories updates.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-I

docs: updates for playbook

Mention the dependencies than could be taken in TF-A.
Add a dedicated entry for the other repositories updates.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If354105dcf94c0b305b8b6ac09822a4c42461e96

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docs(maintainers): update AMD-Xilinx Maintainers

Update "Xilinx" platform subheader with "AMD-Xilinx", to reuse
the maintainer list for legacy Xilinx platforms and
upcoming AMD platforms.
Update mai

docs(maintainers): update AMD-Xilinx Maintainers

Update "Xilinx" platform subheader with "AMD-Xilinx", to reuse
the maintainer list for legacy Xilinx platforms and
upcoming AMD platforms.
Update maintainer list for AMD-Xilinx platforms in TF-A repository.

Change-Id: I3ea81d36eb8bb5269fe69ca5362800dc309b21c1
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto

Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration

* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3

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Merge changes from topic "sudeep/multiple_uuid_clarification" into integration

* changes:
docs: clarify multiple UUID support in ffa manifest
docs: clarify packing of UUID in ffa manifest

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - c

refactor(gic): promote most of the GIC driver to common code

More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.

As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.

All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).

So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.

The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.

For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.

This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.

Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.

Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs: update TF-A Nov'25 release dates

Tentatively updating the plan for TF-A v2.14 release in Nov'25.

Change-Id: I279d935ef65de7ef993e0286e6ac8dc94a9866d9
Signed-off-by: Govindraj Raja <govindraj.

docs: update TF-A Nov'25 release dates

Tentatively updating the plan for TF-A v2.14 release in Nov'25.

Change-Id: I279d935ef65de7ef993e0286e6ac8dc94a9866d9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving

Merge changes Id942c20c,Idd286bea,I8917a26e,Iec8c3477,If3c25dcd, ... into integration

* changes:
feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED
perf(cpufeat): centralise PAuth key saving
refactor(cpufeat): convert FEAT_PAuth setup to C
refactor(cpufeat): prepare FEAT_PAuth for FEATURE_DETECTION
chore(cpufeat): remove PAuth presence checks
feat(cpufeat): enable FEAT_BTI to FEAT_STATE_CHECKED

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feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it

feat(cpufeat): enable FEAT_PAuth to FEAT_STATE_CHECKED

FEAT_PAuth is the second to last feature to be a boolean choice - it's
either unconditionally compiled in and must be present in hardware or
it's not compiled in. FEAT_PAuth is architected to be backwards
compatible - a subset of the branch guarding instructions (pacia/autia)
execute as NOPs when PAuth is not present. That subset is used with
`-mbranch-protection=standard` and -march pre-8.3. This patch adds the
necessary logic to also check accesses of the non-backward compatible
registers and allow a fully checked implementation.

Note that a checked support requires -march to be pre 8.3, as otherwise
the compiler will include branch protection instructions that are not
NOPs without PAuth (eg retaa) which cannot be checked.

Change-Id: Id942c20cae9d15d25b3d72b8161333642574ddaa
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management

Merge changes from topic "sm/rpkm" into integration

* changes:
docs(rmmd): document the EL3-RMM IDE KM Interface
feat(trp): test el3-rmm ide km interface
feat(rmmd): el3-rmm ide key management interface

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chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <M

chore(tc): remove TC2 platform variant

Remove TC2 platform support which was deprecated in the last release.

Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(maintainers): update Arm Total Compute maintainers

Add Artem Kopotev and Oleksandr Tarhunakov

Change-Id: Ic4ca4790f1a4f82ffdb91841b9d9112f9ce9e856
Signed-off-by: Artem Kopotev <artem.kopotev@a

docs(maintainers): update Arm Total Compute maintainers

Add Artem Kopotev and Oleksandr Tarhunakov

Change-Id: Ic4ca4790f1a4f82ffdb91841b9d9112f9ce9e856
Signed-off-by: Artem Kopotev <artem.kopotev@arm.com>

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Merge "feat(psci): remove cpu context init by index" into integration

Merge "docs(build): update GCC toolchain requirement to 14.2.Rel1" into integration

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of in

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
way of knowing the feature set of the waking core. If the two
diverge, the architectural feature discovery via ID registers breaks
down. We've thus far "fixed" this on a case by case basis which
doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
core has to initialise the context for when the core wakes up, but
should the core not powerdown it needs its old context intact. The only
way to work around this is by keeping two copies of context which
incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
it to make initialisation decisions. We can infer some of this from
registers that have already been written but this is awkwardly
limiting for what we can do. This also necessitates the split from
the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e

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Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neove

Merge changes from topic "nrd1_deprecation" into integration

* changes:
docs(changelog): remove RD-E1-Edge platform's scope
docs(maintainers): add RD-V3 variants to maintained paths
feat(neoverse_rd): deprecate and remove RD-V1 platform variants
feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants
feat(neoverse_rd): deprecate and remove SGI-575 platform

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Merge changes Ie33671b0,I1543aa6d into integration

* changes:
docs(fvp): clarify what `FVP` means
fix(fvp): allow PSCI 0.2 in the device tree

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch documents the EL3-RMM IDE KM interface.

Four IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch documents the EL3-RMM IDE KM interface.

Four IDE Key management smc calls have been added:
- RMM_IDE_KEY_PROG()
- RMM_IDE_KEY_SET_GO()
- RMM_IDE_KEY_SET_STOP()
- RMM_IDE_KM_PULL_RESPONSE()

Change-Id: Iea357ec16a2bee88573266c7a5c9fb36025f15f1
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "lto-by-default" into integration

* changes:
fix(libc): make sure __init functions are garbage collected
fix(platforms): remove platform_core_pos_helper()