1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* .global erratum_cortex_a520_2938996_wa */ 15.global check_erratum_cortex_a520_2938996 16 17/* Hardware handled coherency */ 18#if HW_ASSISTED_COHERENCY == 0 19#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 20#endif 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27cpu_reset_prologue cortex_a520 28 29workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 30 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 31workaround_reset_end cortex_a520, ERRATUM(2630792) 32 33check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 34 35workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 36 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 37workaround_reset_end cortex_a520, ERRATUM(2858100) 38 39check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 40 41workaround_runtime_start cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996, CORTEX_A520_MIDR 42workaround_runtime_end cortex_a520, ERRATUM(2938996) 43 44check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1) 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func cortex_a520_core_pwr_dwn 51 /* --------------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------------- 54 */ 55 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 56 isb 57 ret 58endfunc cortex_a520_core_pwr_dwn 59 60cpu_reset_func_start cortex_a520 61 /* Disable speculative loads */ 62 msr SSBS, xzr 63cpu_reset_func_end cortex_a520 64 65 /* --------------------------------------------- 66 * This function provides Cortex A520 specific 67 * register information for crash reporting. 68 * It needs to return with x6 pointing to 69 * a list of register names in ascii and 70 * x8 - x15 having values of registers to be 71 * reported. 72 * --------------------------------------------- 73 */ 74.section .rodata.cortex_a520_regs, "aS" 75cortex_a520_regs: /* The ascii list of register names to be reported */ 76 .asciz "cpuectlr_el1", "" 77 78func cortex_a520_cpu_reg_dump 79 adr x6, cortex_a520_regs 80 mrs x8, CORTEX_A520_CPUECTLR_EL1 81 ret 82endfunc cortex_a520_cpu_reg_dump 83 84declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 85 cortex_a520_reset_func, \ 86 cortex_a520_core_pwr_dwn 87