1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSE. Need to define if 262 platform supports RSE. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U_IMAGE_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP_BL2U_IMAGE_ID** 343 344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP_BL2U. 346 347 .. note:: 348 TF-A does not provide source code for this image. 349 350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 351also be defined: 352 353- **#define : NS_BL1U_BASE** 354 355 Defines the base address in non-secure ROM where NS_BL1U executes. 356 Must be aligned on a page-size boundary. 357 358 .. note:: 359 TF-A does not provide source code for this image. 360 361- **#define : NS_BL1U_IMAGE_ID** 362 363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS_BL1U. 365 366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 367be defined: 368 369- **#define : NS_BL2U_BASE** 370 371 Defines the base address in non-secure memory where NS_BL2U executes. 372 Must be aligned on a page-size boundary. 373 374 .. note:: 375 TF-A does not provide source code for this image. 376 377- **#define : NS_BL2U_IMAGE_ID** 378 379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 380 corresponding to NS_BL2U. 381 382For the the Firmware update capability of TRUSTED BOARD BOOT, the following 383macros may also be defined: 384 385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 386 387 Total number of images that can be loaded simultaneously. If the platform 388 doesn't specify any value, it defaults to 10. 389 390If a SCP_BL2 image is supported by the platform, the following constants must 391also be defined: 392 393- **#define : SCP_BL2_IMAGE_ID** 394 395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 396 from platform storage before being transferred to the SCP. 397 398- **#define : SCP_FW_KEY_CERT_ID** 399 400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 401 certificate (mandatory when Trusted Board Boot is enabled). 402 403- **#define : SCP_FW_CONTENT_CERT_ID** 404 405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 406 content certificate (mandatory when Trusted Board Boot is enabled). 407 408If a BL32 image is supported by the platform, the following constants must 409also be defined: 410 411- **#define : BL32_IMAGE_ID** 412 413 BL32 image identifier, used by BL2 to load BL32. 414 415- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 416 417 BL32 key certificate identifier, used by BL2 to load the BL32 key 418 certificate (mandatory when Trusted Board Boot is enabled). 419 420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 421 422 BL32 content certificate identifier, used by BL2 to load the BL32 content 423 certificate (mandatory when Trusted Board Boot is enabled). 424 425- **#define : BL32_BASE** 426 427 Defines the base address in secure memory where BL2 loads the BL32 binary 428 image. Must be aligned on a page-size boundary. 429 430- **#define : BL32_LIMIT** 431 432 Defines the maximum address that the BL32 image can occupy. 433 434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 435platform, the following constants must also be defined: 436 437- **#define : TSP_SEC_MEM_BASE** 438 439 Defines the base address of the secure memory used by the TSP image on the 440 platform. This must be at the same address or below ``BL32_BASE``. 441 442- **#define : TSP_SEC_MEM_SIZE** 443 444 Defines the size of the secure memory used by the BL32 image on the 445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 447 and ``BL32_LIMIT``. 448 449- **#define : TSP_IRQ_SEC_PHY_TIMER** 450 451 Defines the ID of the secure physical generic timer interrupt used by the 452 TSP's interrupt handling code. 453 454If the platform port uses the translation table library code, the following 455constants must also be defined: 456 457- **#define : PLAT_XLAT_TABLES_DYNAMIC** 458 459 Optional flag that can be set per-image to enable the dynamic allocation of 460 regions even when the MMU is enabled. If not defined, only static 461 functionality will be available, if defined and set to 1 it will also 462 include the dynamic functionality. 463 464- **#define : MAX_XLAT_TABLES** 465 466 Defines the maximum number of translation tables that are allocated by the 467 translation table library code. To minimize the amount of runtime memory 468 used, choose the smallest value needed to map the required virtual addresses 469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 471 as well. 472 473- **#define : MAX_MMAP_REGIONS** 474 475 Defines the maximum number of regions that are allocated by the translation 476 table library code. A region consists of physical base address, virtual base 477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 478 defined in the ``mmap_region_t`` structure. The platform defines the regions 479 that should be mapped. Then, the translation table library will create the 480 corresponding tables and descriptors at runtime. To minimize the amount of 481 runtime memory used, choose the smallest value needed to register the 482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 484 the dynamic regions as well. 485 486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 487 488 Defines the total size of the virtual address space in bytes. For example, 489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 490 491- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 492 493 Defines the total size of the physical address space in bytes. For example, 494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 495 496If the platform port uses the IO storage framework, the following constants 497must also be defined: 498 499- **#define : MAX_IO_DEVICES** 500 501 Defines the maximum number of registered IO devices. Attempting to register 502 more devices than this value using ``io_register_device()`` will fail with 503 -ENOMEM. 504 505- **#define : MAX_IO_HANDLES** 506 507 Defines the maximum number of open IO handles. Attempting to open more IO 508 entities than this value using ``io_open()`` will fail with -ENOMEM. 509 510- **#define : MAX_IO_BLOCK_DEVICES** 511 512 Defines the maximum number of registered IO block devices. Attempting to 513 register more devices this value using ``io_dev_open()`` will fail 514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 515 With this macro, multiple block devices could be supported at the same 516 time. 517 518If the platform needs to allocate data within the per-cpu data framework in 519BL31, it should define the following macro. Currently this is only required if 520the platform decides not to use the coherent memory section by undefining the 521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 522required memory within the the per-cpu data to minimize wastage. 523 524- **#define : PLAT_PCPU_DATA_SIZE** 525 526 Defines the memory (in bytes) to be reserved within the per-cpu data 527 structure for use by the platform layer. 528 529The following constants are optional. They should be defined when the platform 530memory layout implies some image overlaying like in Arm standard platforms. 531 532- **#define : BL31_PROGBITS_LIMIT** 533 534 Defines the maximum address in secure RAM that the BL31's progbits sections 535 can occupy. 536 537- **#define : TSP_PROGBITS_LIMIT** 538 539 Defines the maximum address that the TSP's progbits sections can occupy. 540 541If the platform supports OS-initiated mode, i.e. the build option 542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 544constant must be defined. 545 546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 547 548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 549 550If the platform port uses the PL061 GPIO driver, the following constant may 551optionally be defined: 552 553- **PLAT_PL061_MAX_GPIOS** 554 Maximum number of GPIOs required by the platform. This allows control how 555 much memory is allocated for PL061 GPIO controllers. The default value is 556 557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 558 559If the platform port uses the partition driver, the following constant may 560optionally be defined: 561 562- **PLAT_PARTITION_MAX_ENTRIES** 563 Maximum number of partition entries required by the platform. This allows 564 control how much memory is allocated for partition entries. The default 565 value is 128. 566 For example, define the build flag in ``platform.mk``: 567 PLAT_PARTITION_MAX_ENTRIES := 12 568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 569 570- **PLAT_PARTITION_BLOCK_SIZE** 571 The size of partition block. It could be either 512 bytes or 4096 bytes. 572 The default value is 512. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_BLOCK_SIZE := 4096 575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 576 577If the platform port uses the Arm® Ethos™-N NPU driver, the following 578configuration must be performed: 579 580- The NPU SiP service handler must be hooked up. This consists of both the 581 initial setup (``ethosn_smc_setup``) and the handler itself 582 (``ethosn_smc_handler``) 583 584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 585enabled, the following constants and configuration must also be defined: 586 587- **ETHOSN_NPU_PROT_FW_NSAID** 588 589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 590 access the protected memory that contains the NPU's firmware. 591 592- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 593 594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 595 read/write access to the protected memory that contains inference data. 596 597- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 598 599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 600 read-only access to the protected memory that contains inference data. 601 602- **ETHOSN_NPU_NS_RW_DATA_NSAID** 603 604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 605 read/write access to the non-protected memory. 606 607- **ETHOSN_NPU_NS_RO_DATA_NSAID** 608 609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 610 read-only access to the non-protected memory. 611 612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 613 614 Defines the physical address range that the NPU's firmware will be loaded 615 into and executed from. 616 617- Configure the platforms TrustZone Controller (TZC) with appropriate regions 618 of protected memory. At minimum this must include a region for the NPU's 619 firmware code and a region for protected inference data, and these must be 620 accessible using the NSAIDs defined above. 621 622- Include the NPU firmware and certificates in the FIP. 623 624- Provide FCONF entries to configure the image source for the NPU firmware 625 and certificates. 626 627- Add MMU mappings such that: 628 629 - BL2 can write the NPU firmware into the region defined by 630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 631 - BL31 (SiP service) can read the NPU firmware from the same region 632 633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 634 loaded by BL2. 635 636Please see the reference implementation code for the Juno platform as an example. 637 638 639The following constant is optional. It should be defined to override the default 640behaviour of the ``assert()`` function (for example, to save memory). 641 642- **PLAT_LOG_LEVEL_ASSERT** 643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 644 ``assert()`` prints the name of the file, the line number and the asserted 645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 648 defined, it defaults to ``LOG_LEVEL``. 649 650If the platform port uses the DRTM feature, the following constants must be 651defined: 652 653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 654 655 Maximum Event Log size used by the platform. Platform can decide the maximum 656 size of the Event Log buffer, depending upon the highest hash algorithm 657 chosen and the number of components selected to measure during the DRTM 658 execution flow. 659 660- **#define : PLAT_DRTM_MMAP_ENTRIES** 661 662 Number of the MMAP entries used by the DRTM implementation to calculate the 663 size of address map region of the platform. 664 665File : plat_macros.S [mandatory] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668Each platform must ensure a file of this name is in the system include path with 669the following macro defined. In the Arm development platforms, this file is 670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 671 672- **Macro : plat_crash_print_regs** 673 674 This macro allows the crash reporting routine to print relevant platform 675 registers in case of an unhandled exception in BL31. This aids in debugging 676 and this macro can be defined to be empty in case register reporting is not 677 desired. 678 679 For instance, GIC or interconnect registers may be helpful for 680 troubleshooting. 681 682Handling Reset 683-------------- 684 685BL1 by default implements the reset vector where execution starts from a cold 686or warm boot. BL31 can be optionally set as a reset vector using the 687``RESET_TO_BL31`` make variable. 688 689For each CPU, the reset vector code is responsible for the following tasks: 690 691#. Distinguishing between a cold boot and a warm boot. 692 693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 694 the CPU is placed in a platform-specific state until the primary CPU 695 performs the necessary steps to remove it from this state. 696 697#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 698 specific address in the BL31 image in the same processor mode as it was 699 when released from reset. 700 701The following functions need to be implemented by the platform port to enable 702reset vector code to perform the above tasks. 703 704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 706 707:: 708 709 Argument : void 710 Return : uintptr_t 711 712This function is called with the MMU and caches disabled 713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 714distinguishing between a warm and cold reset for the current CPU using 715platform-specific means. If it's a warm reset, then it returns the warm 716reset entrypoint point provided to ``plat_setup_psci_ops()`` during 717BL31 initialization. If it's a cold reset then this function must return zero. 718 719This function does not follow the Procedure Call Standard used by the 720Application Binary Interface for the Arm 64-bit architecture. The caller should 721not assume that callee saved registers are preserved across a call to this 722function. 723 724This function fulfills requirement 1 and 3 listed above. 725 726Note that for platforms that support programming the reset address, it is 727expected that a CPU will start executing code directly at the right address, 728both on a cold and warm reset. In this case, there is no need to identify the 729type of reset nor to query the warm reset entrypoint. Therefore, implementing 730this function is not required on such platforms. 731 732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735:: 736 737 Argument : void 738 739This function is called with the MMU and data caches disabled. It is responsible 740for placing the executing secondary CPU in a platform-specific state until the 741primary CPU performs the necessary actions to bring it out of that state and 742allow entry into the OS. This function must not return. 743 744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 745itself off. The primary CPU is responsible for powering up the secondary CPUs 746when normal world software requires them. When booting an EL3 payload instead, 747they stay powered on and are put in a holding pen until their mailbox gets 748populated. 749 750This function fulfills requirement 2 above. 751 752Note that for platforms that can't release secondary CPUs out of reset, only the 753primary CPU will execute the cold boot code. Therefore, implementing this 754function is not required on such platforms. 755 756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void 762 Return : unsigned int 763 764This function identifies whether the current CPU is the primary CPU or a 765secondary CPU. A return value of zero indicates that the CPU is not the 766primary CPU, while a non-zero return value indicates that the CPU is the 767primary CPU. 768 769Note that for platforms that can't release secondary CPUs out of reset, only the 770primary CPU will execute the cold boot code. Therefore, there is no need to 771distinguish between primary and secondary CPUs and implementing this function is 772not required. 773 774Function : platform_mem_init() [mandatory] 775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 776 777:: 778 779 Argument : void 780 Return : void 781 782This function is called before any access to data is made by the firmware, in 783order to carry out any essential memory initialization. 784 785Function: plat_get_rotpk_info() 786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 787 788:: 789 790 Argument : void *, void **, unsigned int *, unsigned int * 791 Return : int 792 793This function is mandatory when Trusted Board Boot is enabled. It returns a 794pointer to the ROTPK stored in the platform (or a hash of it) and its length. 795The ROTPK must be encoded in DER format according to the following ASN.1 796structure: 797 798:: 799 800 AlgorithmIdentifier ::= SEQUENCE { 801 algorithm OBJECT IDENTIFIER, 802 parameters ANY DEFINED BY algorithm OPTIONAL 803 } 804 805 SubjectPublicKeyInfo ::= SEQUENCE { 806 algorithm AlgorithmIdentifier, 807 subjectPublicKey BIT STRING 808 } 809 810In case the function returns a hash of the key: 811 812:: 813 814 DigestInfo ::= SEQUENCE { 815 digestAlgorithm AlgorithmIdentifier, 816 digest OCTET STRING 817 } 818 819The function returns 0 on success. Any other value is treated as error by the 820Trusted Board Boot. The function also reports extra information related 821to the ROTPK in the flags parameter: 822 823:: 824 825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 826 hash. 827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 828 verification while the platform ROTPK is not deployed. 829 When this flag is set, the function does not need to 830 return a platform ROTPK, and the authentication 831 framework uses the ROTPK in the certificate without 832 verifying it against the platform value. This flag 833 must not be used in a deployed production environment. 834 835Function: plat_get_nv_ctr() 836~~~~~~~~~~~~~~~~~~~~~~~~~~~ 837 838:: 839 840 Argument : void *, unsigned int * 841 Return : int 842 843This function is mandatory when Trusted Board Boot is enabled. It returns the 844non-volatile counter value stored in the platform in the second argument. The 845cookie in the first argument may be used to select the counter in case the 846platform provides more than one (for example, on platforms that use the default 847TBBR CoT, the cookie will correspond to the OID values defined in 848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 849 850The function returns 0 on success. Any other value means the counter value could 851not be retrieved from the platform. 852 853Function: plat_set_nv_ctr() 854~~~~~~~~~~~~~~~~~~~~~~~~~~~ 855 856:: 857 858 Argument : void *, unsigned int 859 Return : int 860 861This function is mandatory when Trusted Board Boot is enabled. It sets a new 862counter value in the platform. The cookie in the first argument may be used to 863select the counter (as explained in plat_get_nv_ctr()). The second argument is 864the updated counter value to be written to the NV counter. 865 866The function returns 0 on success. Any other value means the counter value could 867not be updated. 868 869Function: plat_set_nv_ctr2() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void *, const auth_img_desc_t *, unsigned int 875 Return : int 876 877This function is optional when Trusted Board Boot is enabled. If this 878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 879first argument passed is a cookie and is typically used to 880differentiate between a Non Trusted NV Counter and a Trusted NV 881Counter. The second argument is a pointer to an authentication image 882descriptor and may be used to decide if the counter is allowed to be 883updated or not. The third argument is the updated counter value to 884be written to the NV counter. 885 886The function returns 0 on success. Any other value means the counter value 887either could not be updated or the authentication image descriptor indicates 888that it is not allowed to be updated. 889 890Dynamic Root of Trust for Measurement support (in BL31) 891------------------------------------------------------- 892 893The functions mentioned in this section are mandatory, when platform enables 894DRTM_SUPPORT build flag. 895 896Function : plat_get_addr_mmap() 897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 898 899:: 900 901 Argument : void 902 Return : const mmap_region_t * 903 904This function is used to return the address of the platform *address-map* table, 905which describes the regions of normal memory, memory mapped I/O 906and non-volatile memory. 907 908Function : plat_has_non_host_platforms() 909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 910 911:: 912 913 Argument : void 914 Return : bool 915 916This function returns *true* if the platform has any trusted devices capable of 917DMA, otherwise returns *false*. 918 919Function : plat_has_unmanaged_dma_peripherals() 920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 921 922:: 923 924 Argument : void 925 Return : bool 926 927This function returns *true* if platform uses peripherals whose DMA is not 928managed by an SMMU, otherwise returns *false*. 929 930Note - 931If the platform has peripherals that are not managed by the SMMU, then the 932platform should investigate such peripherals to determine whether they can 933be trusted, and such peripherals should be moved under "Non-host platforms" 934if they can be trusted. 935 936Function : plat_get_total_num_smmus() 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939:: 940 941 Argument : void 942 Return : unsigned int 943 944This function returns the total number of SMMUs in the platform. 945 946Function : plat_enumerate_smmus() 947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 948:: 949 950 951 Argument : void 952 Return : const uintptr_t *, size_t 953 954This function returns an array of SMMU addresses and the actual number of SMMUs 955reported by the platform. 956 957Function : plat_drtm_get_dma_prot_features() 958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 959 960:: 961 962 Argument : void 963 Return : const plat_drtm_dma_prot_features_t* 964 965This function returns the address of plat_drtm_dma_prot_features_t structure 966containing the maximum number of protected regions and bitmap with the types 967of DMA protection supported by the platform. 968For more details see section 3.3 Table 6 of `DRTM`_ specification. 969 970Function : plat_drtm_dma_prot_get_max_table_bytes() 971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 972 973:: 974 975 Argument : void 976 Return : uint64_t 977 978This function returns the maximum size of DMA protected regions table in 979bytes. 980 981Function : plat_drtm_get_tpm_features() 982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 983 984:: 985 986 Argument : void 987 Return : const plat_drtm_tpm_features_t* 988 989This function returns the address of *plat_drtm_tpm_features_t* structure 990containing PCR usage schema, TPM-based hash, and firmware hash algorithm 991supported by the platform. 992 993Function : plat_drtm_get_min_size_normal_world_dce() 994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 995 996:: 997 998 Argument : void 999 Return : uint64_t 1000 1001This function returns the size normal-world DCE of the platform. 1002 1003Function : plat_drtm_get_imp_def_dlme_region_size() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : uint64_t 1010 1011This function returns the size of implementation defined DLME region 1012of the platform. 1013 1014Function : plat_drtm_get_tcb_hash_table_size() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : uint64_t 1021 1022This function returns the size of TCB hash table of the platform. 1023 1024Function : plat_drtm_get_acpi_tables_region_size() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : uint64_t 1031 1032This function returns the size of ACPI tables region of the platform. 1033 1034Function : plat_drtm_get_tcb_hash_features() 1035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1036 1037:: 1038 1039 Argument : void 1040 Return : uint64_t 1041 1042This function returns the Maximum number of TCB hashes recorded by the 1043platform. 1044For more details see section 3.3 Table 6 of `DRTM`_ specification. 1045 1046Function : plat_drtm_validate_ns_region() 1047~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1048 1049:: 1050 1051 Argument : uintptr_t, uintptr_t 1052 Return : int 1053 1054This function validates that given region is within the Non-Secure region 1055of DRAM. This function takes a region start address and size an input 1056arguments, and returns 0 on success and -1 on failure. 1057 1058Function : plat_set_drtm_error() 1059~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1060 1061:: 1062 1063 Argument : uint64_t 1064 Return : int 1065 1066This function writes a 64 bit error code received as input into 1067non-volatile storage and returns 0 on success and -1 on failure. 1068 1069Function : plat_get_drtm_error() 1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1071 1072:: 1073 1074 Argument : uint64_t* 1075 Return : int 1076 1077This function reads a 64 bit error code from the non-volatile storage 1078into the received address, and returns 0 on success and -1 on failure. 1079 1080Common mandatory function modifications 1081--------------------------------------- 1082 1083The following functions are mandatory functions which need to be implemented 1084by the platform port. 1085 1086Function : plat_my_core_pos() 1087~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1088 1089:: 1090 1091 Argument : void 1092 Return : unsigned int 1093 1094This function returns the index of the calling CPU which is used as a 1095CPU-specific linear index into blocks of memory (for example while allocating 1096per-CPU stacks). This function will be invoked very early in the 1097initialization sequence which mandates that this function should be 1098implemented in assembly and should not rely on the availability of a C 1099runtime environment. This function can clobber x0 - x8 and must preserve 1100x9 - x29. 1101 1102This function plays a crucial role in the power domain topology framework in 1103PSCI and details of this can be found in 1104:ref:`PSCI Power Domain Tree Structure`. 1105 1106Function : plat_core_pos_by_mpidr() 1107~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1108 1109:: 1110 1111 Argument : u_register_t 1112 Return : int 1113 1114This function validates the ``MPIDR`` of a CPU and converts it to an index, 1115which can be used as a CPU-specific linear index into blocks of memory. In 1116case the ``MPIDR`` is invalid, this function returns -1. This function will only 1117be invoked by BL31 after the power domain topology is initialized and can 1118utilize the C runtime environment. For further details about how TF-A 1119represents the power domain topology and how this relates to the linear CPU 1120index, please refer :ref:`PSCI Power Domain Tree Structure`. 1121 1122Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1123~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1124 1125:: 1126 1127 Arguments : void **heap_addr, size_t *heap_size 1128 Return : int 1129 1130This function is invoked during Mbed TLS library initialisation to get a heap, 1131by means of a starting address and a size. This heap will then be used 1132internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1133must be able to provide a heap to it. 1134 1135A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1136which a heap is statically reserved during compile time inside every image 1137(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1138the function simply returns the address and size of this "pre-allocated" heap. 1139For a platform to use this default implementation, only a call to the helper 1140from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1141 1142However, by writting their own implementation, platforms have the potential to 1143optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1144shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1145twice. 1146 1147On success the function should return 0 and a negative error code otherwise. 1148 1149Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1150~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1151 1152:: 1153 1154 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1155 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1156 size_t img_id_len 1157 Return : int 1158 1159This function provides a symmetric key (either SSK or BSSK depending on 1160fw_enc_status) which is invoked during runtime decryption of encrypted 1161firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1162implementation for testing purposes which must be overridden by the platform 1163trying to implement a real world firmware encryption use-case. 1164 1165It also allows the platform to pass symmetric key identifier rather than 1166actual symmetric key which is useful in cases where the crypto backend provides 1167secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1168flag must be set in ``flags``. 1169 1170In addition to above a platform may also choose to provide an image specific 1171symmetric key/identifier using img_id. 1172 1173On success the function should return 0 and a negative error code otherwise. 1174 1175Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1176 1177Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1178~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1179 1180:: 1181 1182 Argument : const struct fwu_metadata *metadata 1183 Return : void 1184 1185This function is mandatory when PSA_FWU_SUPPORT is enabled. 1186It provides a means to retrieve image specification (offset in 1187non-volatile storage and length) of active/updated images using the passed 1188FWU metadata, and update I/O policies of active/updated images using retrieved 1189image specification information. 1190Further I/O layer operations such as I/O open, I/O read, etc. on these 1191images rely on this function call. 1192 1193In Arm platforms, this function is used to set an I/O policy of the FIP image, 1194container of all active/updated secure and non-secure images. 1195 1196Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1197~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1198 1199:: 1200 1201 Argument : unsigned int image_id, uintptr_t *dev_handle, 1202 uintptr_t *image_spec 1203 Return : int 1204 1205This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1206responsible for setting up the platform I/O policy of the requested metadata 1207image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1208be used to load this image from the platform's non-volatile storage. 1209 1210FWU metadata can not be always stored as a raw image in non-volatile storage 1211to define its image specification (offset in non-volatile storage and length) 1212statically in I/O policy. 1213For example, the FWU metadata image is stored as a partition inside the GUID 1214partition table image. Its specification is defined in the partition table 1215that needs to be parsed dynamically. 1216This function provides a means to retrieve such dynamic information to set 1217the I/O policy of the FWU metadata image. 1218Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1219image relies on this function call. 1220 1221It returns '0' on success, otherwise a negative error value on error. 1222Alongside, returns device handle and image specification from the I/O policy 1223of the requested FWU metadata image. 1224 1225Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1226~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1227 1228:: 1229 1230 Argument : void 1231 Return : uint32_t 1232 1233This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1234means to retrieve the boot index value from the platform. The boot index is the 1235bank from which the platform has booted the firmware images. 1236 1237By default, the platform will read the metadata structure and try to boot from 1238the active bank. If the platform fails to boot from the active bank due to 1239reasons like an Authentication failure, or on crossing a set number of watchdog 1240resets while booting from the active bank, the platform can then switch to boot 1241from a different bank. This function then returns the bank that the platform 1242should boot its images from. 1243 1244Common optional modifications 1245----------------------------- 1246 1247The following are helper functions implemented by the firmware that perform 1248common platform-specific tasks. A platform may choose to override these 1249definitions. 1250 1251Function : plat_set_my_stack() 1252~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1253 1254:: 1255 1256 Argument : void 1257 Return : void 1258 1259This function sets the current stack pointer to the normal memory stack that 1260has been allocated for the current CPU. For BL images that only require a 1261stack for the primary CPU, the UP version of the function is used. The size 1262of the stack allocated to each CPU is specified by the platform defined 1263constant ``PLATFORM_STACK_SIZE``. 1264 1265Common implementations of this function for the UP and MP BL images are 1266provided in ``plat/common/aarch64/platform_up_stack.S`` and 1267``plat/common/aarch64/platform_mp_stack.S`` 1268 1269Function : plat_get_my_stack() 1270~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1271 1272:: 1273 1274 Argument : void 1275 Return : uintptr_t 1276 1277This function returns the base address of the normal memory stack that 1278has been allocated for the current CPU. For BL images that only require a 1279stack for the primary CPU, the UP version of the function is used. The size 1280of the stack allocated to each CPU is specified by the platform defined 1281constant ``PLATFORM_STACK_SIZE``. 1282 1283Common implementations of this function for the UP and MP BL images are 1284provided in ``plat/common/aarch64/platform_up_stack.S`` and 1285``plat/common/aarch64/platform_mp_stack.S`` 1286 1287Function : plat_report_exception() 1288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1289 1290:: 1291 1292 Argument : unsigned int 1293 Return : void 1294 1295A platform may need to report various information about its status when an 1296exception is taken, for example the current exception level, the CPU security 1297state (secure/non-secure), the exception type, and so on. This function is 1298called in the following circumstances: 1299 1300- In BL1, whenever an exception is taken. 1301- In BL2, whenever an exception is taken. 1302 1303The default implementation doesn't do anything, to avoid making assumptions 1304about the way the platform displays its status information. 1305 1306For AArch64, this function receives the exception type as its argument. 1307Possible values for exceptions types are listed in the 1308``include/common/bl_common.h`` header file. Note that these constants are not 1309related to any architectural exception code; they are just a TF-A convention. 1310 1311For AArch32, this function receives the exception mode as its argument. 1312Possible values for exception modes are listed in the 1313``include/lib/aarch32/arch.h`` header file. 1314 1315Function : plat_reset_handler() 1316~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1317 1318:: 1319 1320 Argument : void 1321 Return : void 1322 1323A platform may need to do additional initialization after reset. This function 1324allows the platform to do the platform specific initializations. Platform 1325specific errata workarounds could also be implemented here. The API should 1326preserve the values of callee saved registers x19 to x29. 1327 1328The default implementation doesn't do anything. If a platform needs to override 1329the default implementation, refer to the :ref:`Firmware Design` for general 1330guidelines. 1331 1332Function : plat_disable_acp() 1333~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1334 1335:: 1336 1337 Argument : void 1338 Return : void 1339 1340This API allows a platform to disable the Accelerator Coherency Port (if 1341present) during a cluster power down sequence. The default weak implementation 1342doesn't do anything. Since this API is called during the power down sequence, 1343it has restrictions for stack usage and it can use the registers x0 - x17 as 1344scratch registers. It should preserve the value in x18 register as it is used 1345by the caller to store the return address. 1346 1347Function : plat_error_handler() 1348~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1349 1350:: 1351 1352 Argument : int 1353 Return : void 1354 1355This API is called when the generic code encounters an error situation from 1356which it cannot continue. It allows the platform to perform error reporting or 1357recovery actions (for example, reset the system). This function must not return. 1358 1359The parameter indicates the type of error using standard codes from ``errno.h``. 1360Possible errors reported by the generic code are: 1361 1362- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1363 Board Boot is enabled) 1364- ``-ENOENT``: the requested image or certificate could not be found or an IO 1365 error was detected 1366- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1367 error is usually an indication of an incorrect array size 1368 1369The default implementation simply spins. 1370 1371Function : plat_panic_handler() 1372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1373 1374:: 1375 1376 Argument : void 1377 Return : void 1378 1379This API is called when the generic code encounters an unexpected error 1380situation from which it cannot recover. This function must not return, 1381and must be implemented in assembly because it may be called before the C 1382environment is initialized. 1383 1384.. note:: 1385 The address from where it was called is stored in x30 (Link Register). 1386 The default implementation simply spins. 1387 1388Function : plat_system_reset() 1389~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1390 1391:: 1392 1393 Argument : void 1394 Return : void 1395 1396This function is used by the platform to resets the system. It can be used 1397in any specific use-case where system needs to be resetted. For example, 1398in case of DRTM implementation this function reset the system after 1399writing the DRTM error code in the non-volatile storage. This function 1400never returns. Failure in reset results in panic. 1401 1402Function : plat_get_bl_image_load_info() 1403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1404 1405:: 1406 1407 Argument : void 1408 Return : bl_load_info_t * 1409 1410This function returns pointer to the list of images that the platform has 1411populated to load. This function is invoked in BL2 to load the 1412BL3xx images. 1413 1414Function : plat_get_next_bl_params() 1415~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1416 1417:: 1418 1419 Argument : void 1420 Return : bl_params_t * 1421 1422This function returns a pointer to the shared memory that the platform has 1423kept aside to pass TF-A related information that next BL image needs. This 1424function is invoked in BL2 to pass this information to the next BL 1425image. 1426 1427Function : plat_get_stack_protector_canary() 1428~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1429 1430:: 1431 1432 Argument : void 1433 Return : u_register_t 1434 1435This function returns a random value that is used to initialize the canary used 1436when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1437value will weaken the protection as the attacker could easily write the right 1438value as part of the attack most of the time. Therefore, it should return a 1439true random number. 1440 1441.. warning:: 1442 For the protection to be effective, the global data need to be placed at 1443 a lower address than the stack bases. Failure to do so would allow an 1444 attacker to overwrite the canary as part of the stack buffer overflow attack. 1445 1446Function : plat_flush_next_bl_params() 1447~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1448 1449:: 1450 1451 Argument : void 1452 Return : void 1453 1454This function flushes to main memory all the image params that are passed to 1455next image. This function is invoked in BL2 to flush this information 1456to the next BL image. 1457 1458Function : plat_log_get_prefix() 1459~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1460 1461:: 1462 1463 Argument : unsigned int 1464 Return : const char * 1465 1466This function defines the prefix string corresponding to the `log_level` to be 1467prepended to all the log output from TF-A. The `log_level` (argument) will 1468correspond to one of the standard log levels defined in debug.h. The platform 1469can override the common implementation to define a different prefix string for 1470the log output. The implementation should be robust to future changes that 1471increase the number of log levels. 1472 1473Function : plat_get_soc_version() 1474~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1475 1476:: 1477 1478 Argument : void 1479 Return : int32_t 1480 1481This function returns soc version which mainly consist of below fields 1482 1483:: 1484 1485 soc_version[30:24] = JEP-106 continuation code for the SiP 1486 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1487 soc_version[15:0] = Implementation defined SoC ID 1488 1489Function : plat_get_soc_revision() 1490~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1491 1492:: 1493 1494 Argument : void 1495 Return : int32_t 1496 1497This function returns soc revision in below format 1498 1499:: 1500 1501 soc_revision[0:30] = SOC revision of specific SOC 1502 1503Function : plat_is_smccc_feature_available() 1504~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1505 1506:: 1507 1508 Argument : u_register_t 1509 Return : int32_t 1510 1511This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1512the SMCCC function specified in the argument; otherwise returns 1513SMC_ARCH_CALL_NOT_SUPPORTED. 1514 1515Function : plat_can_cmo() 1516~~~~~~~~~~~~~~~~~~~~~~~~~ 1517 1518:: 1519 1520 Argument : void 1521 Return : uint64_t 1522 1523When CONDITIONAL_CMO flag is enabled: 1524 1525- This function indicates whether cache management operations should be 1526 performed. It returns 0 if CMOs should be skipped and non-zero 1527 otherwise. 1528- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1529 stack. Otherwise obey AAPCS. 1530 1531Struct: plat_try_images_ops [optional] 1532~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1533 1534This optional structure holds platform hooks for alternative images load. 1535It has to be defined in platform code and registered by calling 1536plat_setup_try_img_ops() function, passing it the address of the 1537plat_try_images_ops struct. 1538 1539Function : plat_setup_try_img_ops [optional] 1540............................................ 1541 1542:: 1543 1544 Argument : const struct plat_try_images_ops * 1545 Return : void 1546 1547This optional function is called to register platform try images ops, given 1548as argument. 1549 1550Function : plat_try_images_ops.next_instance [optional] 1551....................................................... 1552 1553:: 1554 1555 Argument : unsigned int image_id 1556 Return : int 1557 1558This optional function tries to load images from alternative places. 1559In case PSA FWU is not used, it can be any instance or media. If PSA FWU is 1560used, it is mandatory that the backup image is on the same media. 1561This is required for MTD devices like NAND. 1562The argument is the ID of the image for which we are looking for an alternative 1563place. It returns 0 in case of success and a negative errno value otherwise. 1564 1565Modifications specific to a Boot Loader stage 1566--------------------------------------------- 1567 1568Boot Loader Stage 1 (BL1) 1569------------------------- 1570 1571BL1 implements the reset vector where execution starts from after a cold or 1572warm boot. For each CPU, BL1 is responsible for the following tasks: 1573 1574#. Handling the reset as described in section 2.2 1575 1576#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1577 only this CPU executes the remaining BL1 code, including loading and passing 1578 control to the BL2 stage. 1579 1580#. Identifying and starting the Firmware Update process (if required). 1581 1582#. Loading the BL2 image from non-volatile storage into secure memory at the 1583 address specified by the platform defined constant ``BL2_BASE``. 1584 1585#. Populating a ``meminfo`` structure with the following information in memory, 1586 accessible by BL2 immediately upon entry. 1587 1588 :: 1589 1590 meminfo.total_base = Base address of secure RAM visible to BL2 1591 meminfo.total_size = Size of secure RAM visible to BL2 1592 1593 By default, BL1 places this ``meminfo`` structure at the end of secure 1594 memory visible to BL2. 1595 1596 It is possible for the platform to decide where it wants to place the 1597 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1598 BL2 by overriding the weak default implementation of 1599 ``bl1_plat_handle_post_image_load`` API. 1600 1601The following functions need to be implemented by the platform port to enable 1602BL1 to perform the above tasks. 1603 1604Function : bl1_early_platform_setup() [mandatory] 1605~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1606 1607:: 1608 1609 Argument : void 1610 Return : void 1611 1612This function executes with the MMU and data caches disabled. It is only called 1613by the primary CPU. 1614 1615On Arm standard platforms, this function: 1616 1617- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1618 1619- Initializes a UART (PL011 console), which enables access to the ``printf`` 1620 family of functions in BL1. 1621 1622- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1623 the CCI slave interface corresponding to the cluster that includes the 1624 primary CPU. 1625 1626Function : bl1_plat_arch_setup() [mandatory] 1627~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1628 1629:: 1630 1631 Argument : void 1632 Return : void 1633 1634This function performs any platform-specific and architectural setup that the 1635platform requires. Platform-specific setup might include configuration of 1636memory controllers and the interconnect. 1637 1638In Arm standard platforms, this function enables the MMU. 1639 1640This function helps fulfill requirement 2 above. 1641 1642Function : bl1_platform_setup() [mandatory] 1643~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1644 1645:: 1646 1647 Argument : void 1648 Return : void 1649 1650This function executes with the MMU and data caches enabled. It is responsible 1651for performing any remaining platform-specific setup that can occur after the 1652MMU and data cache have been enabled. 1653 1654In Arm standard platforms, this function initializes the storage abstraction 1655layer used to load the next bootloader image. 1656 1657This function helps fulfill requirement 4 above. 1658 1659Function : bl1_plat_sec_mem_layout() [mandatory] 1660~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1661 1662:: 1663 1664 Argument : void 1665 Return : meminfo * 1666 1667This function should only be called on the cold boot path. It executes with the 1668MMU and data caches enabled. The pointer returned by this function must point to 1669a ``meminfo`` structure containing the extents and availability of secure RAM for 1670the BL1 stage. 1671 1672:: 1673 1674 meminfo.total_base = Base address of secure RAM visible to BL1 1675 meminfo.total_size = Size of secure RAM visible to BL1 1676 1677This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1678populates a similar structure to tell BL2 the extents of memory available for 1679its own use. 1680 1681This function helps fulfill requirements 4 and 5 above. 1682 1683Function : bl1_plat_prepare_exit() [optional] 1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1685 1686:: 1687 1688 Argument : entry_point_info_t * 1689 Return : void 1690 1691This function is called prior to exiting BL1 in response to the 1692``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1693platform specific clean up or bookkeeping operations before transferring 1694control to the next image. It receives the address of the ``entry_point_info_t`` 1695structure passed from BL2. This function runs with MMU disabled. 1696 1697Function : bl1_plat_set_ep_info() [optional] 1698~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1699 1700:: 1701 1702 Argument : unsigned int image_id, entry_point_info_t *ep_info 1703 Return : void 1704 1705This function allows platforms to override ``ep_info`` for the given ``image_id``. 1706 1707The default implementation just returns. 1708 1709Function : bl1_plat_get_next_image_id() [optional] 1710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1711 1712:: 1713 1714 Argument : void 1715 Return : unsigned int 1716 1717This and the following function must be overridden to enable the FWU feature. 1718 1719BL1 calls this function after platform setup to identify the next image to be 1720loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1721with the normal boot sequence, which loads and executes BL2. If the platform 1722returns a different image id, BL1 assumes that Firmware Update is required. 1723 1724The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1725platforms override this function to detect if firmware update is required, and 1726if so, return the first image in the firmware update process. 1727 1728Function : bl1_plat_get_image_desc() [optional] 1729~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1730 1731:: 1732 1733 Argument : unsigned int image_id 1734 Return : image_desc_t * 1735 1736BL1 calls this function to get the image descriptor information ``image_desc_t`` 1737for the provided ``image_id`` from the platform. 1738 1739The default implementation always returns a common BL2 image descriptor. Arm 1740standard platforms return an image descriptor corresponding to BL2 or one of 1741the firmware update images defined in the Trusted Board Boot Requirements 1742specification. 1743 1744Function : bl1_plat_handle_pre_image_load() [optional] 1745~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1746 1747:: 1748 1749 Argument : unsigned int image_id 1750 Return : int 1751 1752This function can be used by the platforms to update/use image information 1753corresponding to ``image_id``. This function is invoked in BL1, both in cold 1754boot and FWU code path, before loading the image. 1755 1756Function : bl1_plat_calc_bl2_layout() [optional] 1757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1758 1759:: 1760 1761 Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout 1762 Return : void 1763 1764This utility function calculates the memory layout of BL2, representing it in a 1765`meminfo_t` structure. The default implementation derives this layout from the 1766positioning of BL1’s RW data at the top of the memory layout. 1767 1768Function : bl1_plat_handle_post_image_load() [optional] 1769~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1770 1771:: 1772 1773 Argument : unsigned int image_id 1774 Return : int 1775 1776This function can be used by the platforms to update/use image information 1777corresponding to ``image_id``. This function is invoked in BL1, both in cold 1778boot and FWU code path, after loading and authenticating the image. 1779 1780The default weak implementation of this function calculates the amount of 1781Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1782structure at the beginning of this free memory and populates it. The address 1783of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1784information to BL2. 1785 1786Function : bl1_plat_fwu_done() [optional] 1787~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1788 1789:: 1790 1791 Argument : unsigned int image_id, uintptr_t image_src, 1792 unsigned int image_size 1793 Return : void 1794 1795BL1 calls this function when the FWU process is complete. It must not return. 1796The platform may override this function to take platform specific action, for 1797example to initiate the normal boot flow. 1798 1799The default implementation spins forever. 1800 1801Function : bl1_plat_mem_check() [mandatory] 1802~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1803 1804:: 1805 1806 Argument : uintptr_t mem_base, unsigned int mem_size, 1807 unsigned int flags 1808 Return : int 1809 1810BL1 calls this function while handling FWU related SMCs, more specifically when 1811copying or authenticating an image. Its responsibility is to ensure that the 1812region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1813that this memory corresponds to either a secure or non-secure memory region as 1814indicated by the security state of the ``flags`` argument. 1815 1816This function can safely assume that the value resulting from the addition of 1817``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1818overflow. 1819 1820This function must return 0 on success, a non-null error code otherwise. 1821 1822The default implementation of this function asserts therefore platforms must 1823override it when using the FWU feature. 1824 1825Boot Loader Stage 2 (BL2) 1826------------------------- 1827 1828The BL2 stage is executed only by the primary CPU, which is determined in BL1 1829using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1830``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1831``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1832non-volatile storage to secure/non-secure RAM. After all the images are loaded 1833then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1834images to be passed to the next BL image. 1835 1836The following functions must be implemented by the platform port to enable BL2 1837to perform the above tasks. 1838 1839Function : bl2_early_platform_setup2() [mandatory] 1840~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1841 1842:: 1843 1844 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1845 Return : void 1846 1847This function executes with the MMU and data caches disabled. It is only called 1848by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1849are platform specific. 1850 1851On Arm standard platforms, the arguments received are : 1852 1853 arg0 - Points to load address of FW_CONFIG 1854 1855 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1856 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1857 1858On Arm standard platforms, this function also: 1859 1860- Initializes a UART (PL011 console), which enables access to the ``printf`` 1861 family of functions in BL2. 1862 1863- Initializes the storage abstraction layer used to load further bootloader 1864 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1865 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1866 1867Function : bl2_plat_arch_setup() [mandatory] 1868~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1869 1870:: 1871 1872 Argument : void 1873 Return : void 1874 1875This function executes with the MMU and data caches disabled. It is only called 1876by the primary CPU. 1877 1878The purpose of this function is to perform any architectural initialization 1879that varies across platforms. 1880 1881On Arm standard platforms, this function enables the MMU. 1882 1883Function : bl2_platform_setup() [mandatory] 1884~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1885 1886:: 1887 1888 Argument : void 1889 Return : void 1890 1891This function may execute with the MMU and data caches enabled if the platform 1892port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1893called by the primary CPU. 1894 1895The purpose of this function is to perform any platform initialization 1896specific to BL2. 1897 1898In Arm standard platforms, this function performs security setup, including 1899configuration of the TrustZone controller to allow non-secure masters access 1900to most of DRAM. Part of DRAM is reserved for secure world use. 1901 1902Function : bl2_plat_handle_pre_image_load() [optional] 1903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1904 1905:: 1906 1907 Argument : unsigned int 1908 Return : int 1909 1910This function can be used by the platforms to update/use image information 1911for given ``image_id``. This function is currently invoked in BL2 before 1912loading each image. 1913 1914Function : bl2_plat_handle_post_image_load() [optional] 1915~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1916 1917:: 1918 1919 Argument : unsigned int 1920 Return : int 1921 1922This function can be used by the platforms to update/use image information 1923for given ``image_id``. This function is currently invoked in BL2 after 1924loading each image. 1925 1926Function : bl2_plat_preload_setup [optional] 1927~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1928 1929:: 1930 1931 Argument : void 1932 Return : void 1933 1934This optional function performs any BL2 platform initialization 1935required before image loading, that is not done later in 1936bl2_platform_setup(). 1937 1938Boot Loader Stage 2 (BL2) at EL3 1939-------------------------------- 1940 1941When the platform has a non-TF-A Boot ROM it is desirable to jump 1942directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1943execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1944document for more information. 1945 1946All mandatory functions of BL2 must be implemented, except the functions 1947bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1948their work is done now by bl2_el3_early_platform_setup and 1949bl2_el3_plat_arch_setup. These functions should generally implement 1950the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1951 1952 1953Function : bl2_el3_early_platform_setup() [mandatory] 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956:: 1957 1958 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1959 Return : void 1960 1961This function executes with the MMU and data caches disabled. It is only called 1962by the primary CPU. This function receives four parameters which can be used 1963by the platform to pass any needed information from the Boot ROM to BL2. 1964 1965On Arm standard platforms, this function does the following: 1966 1967- Initializes a UART (PL011 console), which enables access to the ``printf`` 1968 family of functions in BL2. 1969 1970- Initializes the storage abstraction layer used to load further bootloader 1971 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1972 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1973 1974- Initializes the private variables that define the memory layout used. 1975 1976Function : bl2_el3_plat_arch_setup() [mandatory] 1977~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1978 1979:: 1980 1981 Argument : void 1982 Return : void 1983 1984This function executes with the MMU and data caches disabled. It is only called 1985by the primary CPU. 1986 1987The purpose of this function is to perform any architectural initialization 1988that varies across platforms. 1989 1990On Arm standard platforms, this function enables the MMU. 1991 1992Function : bl2_el3_plat_prepare_exit() [optional] 1993~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1994 1995:: 1996 1997 Argument : void 1998 Return : void 1999 2000This function is called prior to exiting BL2 and run the next image. 2001It should be used to perform platform specific clean up or bookkeeping 2002operations before transferring control to the next image. This function 2003runs with MMU disabled. 2004 2005FWU Boot Loader Stage 2 (BL2U) 2006------------------------------ 2007 2008The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 2009process and is executed only by the primary CPU. BL1 passes control to BL2U at 2010``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 2011 2012#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 2013 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 2014 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 2015 should be copied from. Subsequent handling of the SCP_BL2U image is 2016 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 2017 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 2018 2019#. Any platform specific setup required to perform the FWU process. For 2020 example, Arm standard platforms initialize the TZC controller so that the 2021 normal world can access DDR memory. 2022 2023The following functions must be implemented by the platform port to enable 2024BL2U to perform the tasks mentioned above. 2025 2026Function : bl2u_early_platform_setup() [mandatory] 2027~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2028 2029:: 2030 2031 Argument : meminfo *mem_info, void *plat_info 2032 Return : void 2033 2034This function executes with the MMU and data caches disabled. It is only 2035called by the primary CPU. The arguments to this function is the address 2036of the ``meminfo`` structure and platform specific info provided by BL1. 2037 2038The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2039private storage as the original memory may be subsequently overwritten by BL2U. 2040 2041On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2042to extract SCP_BL2U image information, which is then copied into a private 2043variable. 2044 2045Function : bl2u_plat_arch_setup() [mandatory] 2046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2047 2048:: 2049 2050 Argument : void 2051 Return : void 2052 2053This function executes with the MMU and data caches disabled. It is only 2054called by the primary CPU. 2055 2056The purpose of this function is to perform any architectural initialization 2057that varies across platforms, for example enabling the MMU (since the memory 2058map differs across platforms). 2059 2060Function : bl2u_platform_setup() [mandatory] 2061~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2062 2063:: 2064 2065 Argument : void 2066 Return : void 2067 2068This function may execute with the MMU and data caches enabled if the platform 2069port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2070called by the primary CPU. 2071 2072The purpose of this function is to perform any platform initialization 2073specific to BL2U. 2074 2075In Arm standard platforms, this function performs security setup, including 2076configuration of the TrustZone controller to allow non-secure masters access 2077to most of DRAM. Part of DRAM is reserved for secure world use. 2078 2079Function : bl2u_plat_handle_scp_bl2u() [optional] 2080~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2081 2082:: 2083 2084 Argument : void 2085 Return : int 2086 2087This function is used to perform any platform-specific actions required to 2088handle the SCP firmware. Typically it transfers the image into SCP memory using 2089a platform-specific protocol and waits until SCP executes it and signals to the 2090Application Processor (AP) for BL2U execution to continue. 2091 2092This function returns 0 on success, a negative error code otherwise. 2093This function is included if SCP_BL2U_BASE is defined. 2094 2095Boot Loader Stage 3-1 (BL31) 2096---------------------------- 2097 2098During cold boot, the BL31 stage is executed only by the primary CPU. This is 2099determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2100control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2101CPUs. BL31 executes at EL3 and is responsible for: 2102 2103#. Re-initializing all architectural and platform state. Although BL1 performs 2104 some of this initialization, BL31 remains resident in EL3 and must ensure 2105 that EL3 architectural and platform state is completely initialized. It 2106 should make no assumptions about the system state when it receives control. 2107 2108#. Passing control to a normal world BL image, pre-loaded at a platform- 2109 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2110 populated by BL2 in memory to do this. 2111 2112#. Providing runtime firmware services. Currently, BL31 only implements a 2113 subset of the Power State Coordination Interface (PSCI) API as a runtime 2114 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2115 implementation. 2116 2117#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2118 specific address by BL2. BL31 exports a set of APIs that allow runtime 2119 services to specify the security state in which the next image should be 2120 executed and run the corresponding image. On ARM platforms, BL31 uses the 2121 ``bl_params`` list populated by BL2 in memory to do this. 2122 2123If BL31 is a reset vector, It also needs to handle the reset as specified in 2124section 2.2 before the tasks described above. 2125 2126The following functions must be implemented by the platform port to enable BL31 2127to perform the above tasks. 2128 2129Function : bl31_early_platform_setup2() [mandatory] 2130~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2131 2132:: 2133 2134 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2135 Return : void 2136 2137This function executes with the MMU and data caches disabled. It is only called 2138by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2139platform specific. 2140 2141In Arm standard platforms, the arguments received are : 2142 2143 arg0 - The pointer to the head of `bl_params_t` list 2144 which is list of executable images following BL31, 2145 2146 arg1 - Points to load address of SOC_FW_CONFIG if present 2147 except in case of Arm FVP and Juno platform. 2148 2149 In case of Arm FVP and Juno platform, points to load address 2150 of FW_CONFIG. 2151 2152 arg2 - Points to load address of HW_CONFIG if present 2153 2154 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2155 used in release builds. 2156 2157The function runs through the `bl_param_t` list and extracts the entry point 2158information for BL32 and BL33. It also performs the following: 2159 2160- Initialize a UART (PL011 console), which enables access to the ``printf`` 2161 family of functions in BL31. 2162 2163- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2164 CCI slave interface corresponding to the cluster that includes the primary 2165 CPU. 2166 2167Function : bl31_plat_arch_setup() [mandatory] 2168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2169 2170:: 2171 2172 Argument : void 2173 Return : void 2174 2175This function executes with the MMU and data caches disabled. It is only called 2176by the primary CPU. 2177 2178The purpose of this function is to perform any architectural initialization 2179that varies across platforms. 2180 2181On Arm standard platforms, this function enables the MMU. 2182 2183Function : bl31_platform_setup() [mandatory] 2184~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2185 2186:: 2187 2188 Argument : void 2189 Return : void 2190 2191This function may execute with the MMU and data caches enabled if the platform 2192port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2193called by the primary CPU. 2194 2195The purpose of this function is to complete platform initialization so that both 2196BL31 runtime services and normal world software can function correctly. 2197 2198On Arm standard platforms, this function does the following: 2199 2200- Initialize the generic interrupt controller. 2201 2202 Depending on the GIC driver selected by the platform, the appropriate GICv2 2203 or GICv3 initialization will be done, which mainly consists of: 2204 2205 - Enable secure interrupts in the GIC CPU interface. 2206 - Disable the legacy interrupt bypass mechanism. 2207 - Configure the priority mask register to allow interrupts of all priorities 2208 to be signaled to the CPU interface. 2209 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2210 - Target all secure SPIs to CPU0. 2211 - Enable these secure interrupts in the GIC distributor. 2212 - Configure all other interrupts as non-secure. 2213 - Enable signaling of secure interrupts in the GIC distributor. 2214 2215- Enable system-level implementation of the generic timer counter through the 2216 memory mapped interface. 2217 2218- Grant access to the system counter timer module 2219 2220- Initialize the power controller device. 2221 2222 In particular, initialise the locks that prevent concurrent accesses to the 2223 power controller device. 2224 2225Function : bl31_plat_runtime_setup() [optional] 2226~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2227 2228:: 2229 2230 Argument : void 2231 Return : void 2232 2233The purpose of this function is to allow the platform to perform any BL31 runtime 2234setup just prior to BL31 exit during cold boot. The default weak implementation 2235of this function is empty. Any platform that needs to perform additional runtime 2236setup, before BL31 exits, will need to override this function. 2237 2238Function : bl31_plat_get_next_image_ep_info() [mandatory] 2239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2240 2241:: 2242 2243 Argument : uint32_t 2244 Return : entry_point_info * 2245 2246This function may execute with the MMU and data caches enabled if the platform 2247port does the necessary initializations in ``bl31_plat_arch_setup()``. 2248 2249This function is called by ``bl31_main()`` to retrieve information provided by 2250BL2 for the next image in the security state specified by the argument. BL31 2251uses this information to pass control to that image in the specified security 2252state. This function must return a pointer to the ``entry_point_info`` structure 2253(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2254should return NULL otherwise. 2255 2256Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2257~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2258 2259:: 2260 2261 Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t * 2262 Return : int 2263 2264This function returns the Platform attestation token. If the full token does 2265not fit in the buffer, the function will return a hunk of the token and 2266indicate how many bytes were copied and how many are pending. Multiple calls 2267to this function may be needed to retrieve the entire token. 2268 2269The parameters of the function are: 2270 2271 arg0 - A pointer to the buffer where the Platform token should be copied by 2272 this function. If the platform token does not completely fit in the 2273 buffer, the function may return a piece of the token only. 2274 2275 arg1 - Contains the size (in bytes) of the buffer passed in arg0. In 2276 addition, this parameter is used by the function to return the size 2277 of the platform token length hunk copied to the buffer. 2278 2279 arg2 - A pointer to the buffer where the challenge object is stored. 2280 2281 arg3 - The length of the challenge object in bytes. Possible values are 32, 2282 48 and 64. This argument must be zero for subsequent calls to 2283 retrieve the remaining hunks of the token. 2284 2285 arg4 - Returns the remaining length of the token (in bytes) that is yet to 2286 be returned in further calls. 2287 2288The function returns 0 on success, -EINVAL on failure and -EAGAIN if the 2289resource associated with the platform token retrieval is busy. 2290 2291Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2292~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2293 2294:: 2295 2296 Argument : uintptr_t, size_t *, unsigned int 2297 Return : int 2298 2299This function returns the delegated realm attestation key which will be used to 2300sign Realm attestation token. The API currently only supports P-384 ECC curve 2301key. 2302 2303The parameters of the function are: 2304 2305 arg0 - A pointer to the buffer where the attestation key should be copied 2306 by this function. The buffer must be big enough to hold the 2307 attestation key. 2308 2309 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2310 function returns the attestation key length in this parameter. 2311 2312 arg2 - The type of the elliptic curve to which the requested attestation key 2313 belongs. 2314 2315The function returns 0 on success, -EINVAL on failure. 2316 2317Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2318~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2319 2320:: 2321 2322 Argument : uintptr_t * 2323 Return : size_t 2324 2325This function returns the size of the shared area between EL3 and RMM (or 0 on 2326failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2327in the pointer passed as argument. 2328 2329Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2330~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2331 2332:: 2333 2334 Arguments : rmm_manifest_t *manifest 2335 Return : int 2336 2337When ENABLE_RME is enabled, this function populates a boot manifest for the 2338RMM image and stores it in the area specified by manifest. 2339 2340When ENABLE_RME is disabled, this function is not used. 2341 2342Function : plat_rmmd_el3_token_sign_push_req() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2343~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2344 2345:: 2346 2347 Arguments : const struct el3_token_sign_request *req 2348 Return : int 2349 2350Queue realm attestation token signing request from the RMM in EL3. The interface between 2351the RMM and EL3 is modeled as a queue but the underlying implementation may be different, 2352so long as the semantics of queuing and the error codes are used as defined below. 2353 2354See :ref:`el3_token_sign_request_struct` for definition of the request structure. 2355 2356Optional interface from the RMM-EL3 interface v0.4 onwards. 2357 2358The parameters of the functions are: 2359 arg0: Pointer to the token sign request to be pushed to EL3. 2360 The structure must be located in the RMM-EL3 shared 2361 memory buffer and must be locked before use. 2362 2363Return codes: 2364 - E_RMM_OK On Success. 2365 - E_RMM_INVAL If the arguments are invalid. 2366 - E_RMM_AGAIN Indicates that the request was not queued since the 2367 queue in EL3 is full. This may also be returned for any reason 2368 or situation in the system, that prevents accepting the request 2369 from the RMM. 2370 - E_RMM_UNK If the SMC is not implemented or if interface 2371 version is < 0.4. 2372 2373Function : plat_rmmd_el3_token_sign_pull_resp() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2374~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2375 2376:: 2377 2378 Arguments : struct el3_token_sign_response *resp 2379 Return : int 2380 2381Populate the attestation signing response in the ``resp`` parameter. The interface between 2382the RMM and EL3 is modeled as a queue for responses but the underlying implementation may 2383be different, so long as the semantics of queuing and the error codes are used as defined 2384below. 2385 2386See :ref:`el3_token_sign_response_struct` for definition of the response structure. 2387 2388Optional interface from the RMM-EL3 interface v0.4 onwards. 2389 2390The parameters of the functions are: 2391 resp: Pointer to the token sign response to get from EL3. 2392 The structure must be located in the RMM-EL3 shared 2393 memory buffer and must be locked before use. 2394 2395Return: 2396 - E_RMM_OK On Success. 2397 - E_RMM_INVAL If the arguments are invalid. 2398 - E_RMM_AGAIN Indicates that a response is not ready yet. 2399 - E_RMM_UNK If the SMC is not implemented or if interface 2400 version is < 0.4. 2401 2402Function : plat_rmmd_el3_token_sign_get_rak_pub() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2404 2405:: 2406 2407 Argument : uintptr_t, size_t *, unsigned int 2408 Return : int 2409 2410This function returns the public portion of the realm attestation key which will be used to 2411sign Realm attestation token. Typically, with delegated attestation, the private key is 2412returned, however, there may be platforms where the private key bits are better protected 2413in a platform specific manner such that the private key is not exposed. In such cases, 2414the RMM will only cache the public key and forward any requests such as signing, that 2415uses the private key to EL3. The API currently only supports P-384 ECC curve key. 2416 2417This is an optional interface from the RMM-EL3 interface v0.4 onwards. 2418 2419The parameters of the function are: 2420 2421 arg0 - A pointer to the buffer where the public key should be copied 2422 by this function. The buffer must be big enough to hold the 2423 attestation key. 2424 2425 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2426 function returns the attestation key length in this parameter. 2427 2428 arg2 - The type of the elliptic curve to which the requested attestation key 2429 belongs. 2430 2431The function returns E_RMM_OK on success, RMM_E_INVAL if arguments are invalid and 2432E_RMM_UNK if the SMC is not implemented or if interface version is < 0.4. 2433 2434Function : bl31_plat_enable_mmu [optional] 2435~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2436 2437:: 2438 2439 Argument : uint32_t 2440 Return : void 2441 2442This function enables the MMU. The boot code calls this function with MMU and 2443caches disabled. This function should program necessary registers to enable 2444translation, and upon return, the MMU on the calling PE must be enabled. 2445 2446The function must honor flags passed in the first argument. These flags are 2447defined by the translation library, and can be found in the file 2448``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2449 2450On DynamIQ systems, this function must not use stack while enabling MMU, which 2451is how the function in xlat table library version 2 is implemented. 2452 2453Function : plat_init_apkey [optional] 2454~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2455 2456:: 2457 2458 Argument : void 2459 Return : uint128_t 2460 2461This function returns the 128-bit value which can be used to program ARMv8.3 2462pointer authentication keys. 2463 2464The value should be obtained from a reliable source of randomness. 2465 2466This function is only needed if ARMv8.3 pointer authentication is used in the 2467Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to 1, 2 or 3. 2468 2469Function : plat_get_syscnt_freq2() [mandatory] 2470~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2471 2472:: 2473 2474 Argument : void 2475 Return : unsigned int 2476 2477This function is used by the architecture setup code to retrieve the counter 2478frequency for the CPU's generic timer. This value will be programmed into the 2479``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2480of the system counter, which is retrieved from the first entry in the frequency 2481modes table. 2482 2483#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2484~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2485 2486When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2487bytes) aligned to the cache line boundary that should be allocated per-cpu to 2488accommodate all the bakery locks. 2489 2490If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2491calculates the size of the ``.bakery_lock`` input section, aligns it to the 2492nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2493and stores the result in a linker symbol. This constant prevents a platform 2494from relying on the linker and provide a more efficient mechanism for 2495accessing per-cpu bakery lock information. 2496 2497If this constant is defined and its value is not equal to the value 2498calculated by the linker then a link time assertion is raised. A compile time 2499assertion is raised if the value of the constant is not aligned to the cache 2500line boundary. 2501 2502.. _porting_guide_sdei_requirements: 2503 2504SDEI porting requirements 2505~~~~~~~~~~~~~~~~~~~~~~~~~ 2506 2507The |SDEI| dispatcher requires the platform to provide the following macros 2508and functions, of which some are optional, and some others mandatory. 2509 2510Macros 2511...... 2512 2513Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2514^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2515 2516This macro must be defined to the EL3 exception priority level associated with 2517Normal |SDEI| events on the platform. This must have a higher value 2518(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2519 2520Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2521^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2522 2523This macro must be defined to the EL3 exception priority level associated with 2524Critical |SDEI| events on the platform. This must have a lower value 2525(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2526 2527**Note**: |SDEI| exception priorities must be the lowest among Secure 2528priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2529be higher than Normal |SDEI| priority. 2530 2531Functions 2532......... 2533 2534Function: int plat_sdei_validate_entry_point() [optional] 2535^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2536 2537:: 2538 2539 Argument: uintptr_t ep, unsigned int client_mode 2540 Return: int 2541 2542This function validates the entry point address of the event handler provided by 2543the client for both event registration and *Complete and Resume* |SDEI| calls. 2544The function ensures that the address is valid in the client translation regime. 2545 2546The second argument is the exception level that the client is executing in. It 2547can be Non-Secure EL1 or Non-Secure EL2. 2548 2549The function must return ``0`` for successful validation, or ``-1`` upon failure. 2550 2551The default implementation always returns ``0``. On Arm platforms, this function 2552translates the entry point address within the client translation regime and 2553further ensures that the resulting physical address is located in Non-secure 2554DRAM. 2555 2556Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2557^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2558 2559:: 2560 2561 Argument: uint64_t 2562 Argument: unsigned int 2563 Return: void 2564 2565|SDEI| specification requires that a PE comes out of reset with the events 2566masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2567|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2568time. 2569 2570Should a PE receive an interrupt that was bound to an |SDEI| event while the 2571events are masked on the PE, the dispatcher implementation invokes the function 2572``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2573interrupt and the interrupt ID are passed as parameters. 2574 2575The default implementation only prints out a warning message. 2576 2577.. _porting_guide_trng_requirements: 2578 2579TRNG porting requirements 2580~~~~~~~~~~~~~~~~~~~~~~~~~ 2581 2582The |TRNG| backend requires the platform to provide the following values 2583and mandatory functions. 2584 2585Values 2586...... 2587 2588value: uuid_t plat_trng_uuid [mandatory] 2589^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2590 2591This value must be defined to the UUID of the TRNG backend that is specific to 2592the hardware after ``plat_entropy_setup`` function is called. This value must 2593conform to the SMCCC calling convention; The most significant 32 bits of the 2594UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2595w0 indicates failure to get a TRNG source. 2596 2597Functions 2598......... 2599 2600Function: void plat_entropy_setup(void) [mandatory] 2601^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2602 2603:: 2604 2605 Argument: none 2606 Return: none 2607 2608This function is expected to do platform-specific initialization of any TRNG 2609hardware. This may include generating a UUID from a hardware-specific seed. 2610 2611Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2612^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2613 2614:: 2615 2616 Argument: uint64_t * 2617 Return: bool 2618 Out : when the return value is true, the entropy has been written into the 2619 storage pointed to 2620 2621This function writes entropy into storage provided by the caller. If no entropy 2622is available, it must return false and the storage must not be written. 2623 2624.. _psci_in_bl31: 2625 2626Power State Coordination Interface (in BL31) 2627-------------------------------------------- 2628 2629The TF-A implementation of the PSCI API is based around the concept of a 2630*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2631share some state on which power management operations can be performed as 2632specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2633a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2634*power domains* are arranged in a hierarchical tree structure and each 2635*power domain* can be identified in a system by the cpu index of any CPU that 2636is part of that domain and a *power domain level*. A processing element (for 2637example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2638logical grouping of CPUs that share some state, then level 1 is that group of 2639CPUs (for example, a cluster), and level 2 is a group of clusters (for 2640example, the system). More details on the power domain topology and its 2641organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2642 2643BL31's platform initialization code exports a pointer to the platform-specific 2644power management operations required for the PSCI implementation to function 2645correctly. This information is populated in the ``plat_psci_ops`` structure. The 2646PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2647power management operations on the power domains. For example, the target 2648CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2649handler (if present) is called for the CPU power domain. 2650 2651The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2652describe composite power states specific to a platform. The PSCI implementation 2653defines a generic representation of the power-state parameter, which is an 2654array of local power states where each index corresponds to a power domain 2655level. Each entry contains the local power state the power domain at that power 2656level could enter. It depends on the ``validate_power_state()`` handler to 2657convert the power-state parameter (possibly encoding a composite power state) 2658passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2659 2660The following functions form part of platform port of PSCI functionality. 2661 2662Function : plat_psci_stat_accounting_start() [optional] 2663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2664 2665:: 2666 2667 Argument : const psci_power_state_t * 2668 Return : void 2669 2670This is an optional hook that platforms can implement for residency statistics 2671accounting before entering a low power state. The ``pwr_domain_state`` field of 2672``state_info`` (first argument) can be inspected if stat accounting is done 2673differently at CPU level versus higher levels. As an example, if the element at 2674index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2675state, special hardware logic may be programmed in order to keep track of the 2676residency statistics. For higher levels (array indices > 0), the residency 2677statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2678default implementation will use PMF to capture timestamps. 2679 2680Function : plat_psci_stat_accounting_stop() [optional] 2681~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2682 2683:: 2684 2685 Argument : const psci_power_state_t * 2686 Return : void 2687 2688This is an optional hook that platforms can implement for residency statistics 2689accounting after exiting from a low power state. The ``pwr_domain_state`` field 2690of ``state_info`` (first argument) can be inspected if stat accounting is done 2691differently at CPU level versus higher levels. As an example, if the element at 2692index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2693state, special hardware logic may be programmed in order to keep track of the 2694residency statistics. For higher levels (array indices > 0), the residency 2695statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2696default implementation will use PMF to capture timestamps. 2697 2698Function : plat_psci_stat_get_residency() [optional] 2699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2700 2701:: 2702 2703 Argument : unsigned int, const psci_power_state_t *, unsigned int 2704 Return : u_register_t 2705 2706This is an optional interface that is is invoked after resuming from a low power 2707state and provides the time spent resident in that low power state by the power 2708domain at a particular power domain level. When a CPU wakes up from suspend, 2709all its parent power domain levels are also woken up. The generic PSCI code 2710invokes this function for each parent power domain that is resumed and it 2711identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2712argument) describes the low power state that the power domain has resumed from. 2713The current CPU is the first CPU in the power domain to resume from the low 2714power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2715CPU in the power domain to suspend and may be needed to calculate the residency 2716for that power domain. 2717 2718Function : plat_get_target_pwr_state() [optional] 2719~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2720 2721:: 2722 2723 Argument : unsigned int, const plat_local_state_t *, unsigned int 2724 Return : plat_local_state_t 2725 2726The PSCI generic code uses this function to let the platform participate in 2727state coordination during a power management operation. The function is passed 2728a pointer to an array of platform specific local power state ``states`` (second 2729argument) which contains the requested power state for each CPU at a particular 2730power domain level ``lvl`` (first argument) within the power domain. The function 2731is expected to traverse this array of upto ``ncpus`` (third argument) and return 2732a coordinated target power state by the comparing all the requested power 2733states. The target power state should not be deeper than any of the requested 2734power states. 2735 2736A weak definition of this API is provided by default wherein it assumes 2737that the platform assigns a local state value in order of increasing depth 2738of the power state i.e. for two power states X & Y, if X < Y 2739then X represents a shallower power state than Y. As a result, the 2740coordinated target local power state for a power domain will be the minimum 2741of the requested local power state values. 2742 2743Function : plat_get_power_domain_tree_desc() [mandatory] 2744~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2745 2746:: 2747 2748 Argument : void 2749 Return : const unsigned char * 2750 2751This function returns a pointer to the byte array containing the power domain 2752topology tree description. The format and method to construct this array are 2753described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2754initialization code requires this array to be described by the platform, either 2755statically or dynamically, to initialize the power domain topology tree. In case 2756the array is populated dynamically, then plat_core_pos_by_mpidr() and 2757plat_my_core_pos() should also be implemented suitably so that the topology tree 2758description matches the CPU indices returned by these APIs. These APIs together 2759form the platform interface for the PSCI topology framework. 2760 2761Function : plat_setup_psci_ops() [mandatory] 2762~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2763 2764:: 2765 2766 Argument : uintptr_t, const plat_psci_ops ** 2767 Return : int 2768 2769This function may execute with the MMU and data caches enabled if the platform 2770port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2771called by the primary CPU. 2772 2773This function is called by PSCI initialization code. Its purpose is to let 2774the platform layer know about the warm boot entrypoint through the 2775``sec_entrypoint`` (first argument) and to export handler routines for 2776platform-specific psci power management actions by populating the passed 2777pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2778 2779A description of each member of this structure is given below. Please refer to 2780the Arm FVP specific implementation of these handlers in 2781``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2782platform wants to support, the associated operation or operations in this 2783structure must be provided and implemented (Refer section 4 of 2784:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2785function in a platform port, the operation should be removed from this 2786structure instead of providing an empty implementation. 2787 2788plat_psci_ops.cpu_standby() 2789........................... 2790 2791Perform the platform-specific actions to enter the standby state for a cpu 2792indicated by the passed argument. This provides a fast path for CPU standby 2793wherein overheads of PSCI state management and lock acquisition is avoided. 2794For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2795the suspend state type specified in the ``power-state`` parameter should be 2796STANDBY and the target power domain level specified should be the CPU. The 2797handler should put the CPU into a low power retention state (usually by 2798issuing a wfi instruction) and ensure that it can be woken up from that 2799state by a normal interrupt. The generic code expects the handler to succeed. 2800 2801plat_psci_ops.pwr_domain_on() 2802............................. 2803 2804Perform the platform specific actions to power on a CPU, specified 2805by the ``MPIDR`` (first argument). The generic code expects the platform to 2806return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2807 2808plat_psci_ops.pwr_domain_off_early() [optional] 2809............................................... 2810 2811This optional function performs the platform specific actions to check if 2812powering off the calling CPU and its higher parent power domain levels as 2813indicated by the ``target_state`` (first argument) is possible or allowed. 2814 2815The ``target_state`` encodes the platform coordinated target local power states 2816for the CPU power domain and its parent power domain levels. 2817 2818For this handler, the local power state for the CPU power domain will be a 2819power down state where as it could be either power down, retention or run state 2820for the higher power domain levels depending on the result of state 2821coordination. The generic code expects PSCI_E_DENIED return code if the 2822platform thinks that CPU_OFF should not proceed on the calling CPU. 2823 2824plat_psci_ops.pwr_domain_off() 2825.............................. 2826 2827Perform the platform specific actions to prepare to power off the calling CPU 2828and its higher parent power domain levels as indicated by the ``target_state`` 2829(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2830 2831The ``target_state`` encodes the platform coordinated target local power states 2832for the CPU power domain and its parent power domain levels. The handler 2833needs to perform power management operation corresponding to the local state 2834at each power level. 2835 2836For this handler, the local power state for the CPU power domain will be a 2837power down state where as it could be either power down, retention or run state 2838for the higher power domain levels depending on the result of state 2839coordination. The generic code expects the handler to succeed. 2840 2841plat_psci_ops.pwr_domain_validate_suspend() [optional] 2842...................................................... 2843 2844This is an optional function that is only compiled into the build if the build 2845option ``PSCI_OS_INIT_MODE`` is enabled. 2846 2847If implemented, this function allows the platform to perform platform specific 2848validations based on hardware states. The generic code expects this function to 2849return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 2850PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 2851 2852plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2853........................................................... 2854 2855This optional function may be used as a performance optimization to replace 2856or complement pwr_domain_suspend() on some platforms. Its calling semantics 2857are identical to pwr_domain_suspend(), except the PSCI implementation only 2858calls this function when suspending to a power down state, and it guarantees 2859that data caches are enabled. 2860 2861When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2862before calling pwr_domain_suspend(). If the target_state corresponds to a 2863power down state and it is safe to perform some or all of the platform 2864specific actions in that function with data caches enabled, it may be more 2865efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2866= 1, data caches remain enabled throughout, and so there is no advantage to 2867moving platform specific actions to this function. 2868 2869plat_psci_ops.pwr_domain_suspend() 2870.................................. 2871 2872Perform the platform specific actions to prepare to suspend the calling 2873CPU and its higher parent power domain levels as indicated by the 2874``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2875API implementation. 2876 2877The ``target_state`` has a similar meaning as described in 2878the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2879target local power states for the CPU power domain and its parent 2880power domain levels. The handler needs to perform power management operation 2881corresponding to the local state at each power level. The generic code 2882expects the handler to succeed. 2883 2884The difference between turning a power domain off versus suspending it is that 2885in the former case, the power domain is expected to re-initialize its state 2886when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2887case, the power domain is expected to save enough state so that it can resume 2888execution by restoring this state when its powered on (see 2889``pwr_domain_suspend_finish()``). 2890 2891When suspending a core, the platform can also choose to power off the GICv3 2892Redistributor and ITS through an implementation-defined sequence. To achieve 2893this safely, the ITS context must be saved first. The architectural part is 2894implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2895sequence is implementation defined and it is therefore the responsibility of 2896the platform code to implement the necessary sequence. Then the GIC 2897Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2898Powering off the Redistributor requires the implementation to support it and it 2899is the responsibility of the platform code to execute the right implementation 2900defined sequence. 2901 2902When a system suspend is requested, the platform can also make use of the 2903``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2904it has saved the context of the Redistributors and ITS of all the cores in the 2905system. The context of the Distributor can be large and may require it to be 2906allocated in a special area if it cannot fit in the platform's global static 2907data, for example in DRAM. The Distributor can then be powered down using an 2908implementation-defined sequence. 2909 2910plat_psci_ops.pwr_domain_pwr_down() 2911....................................... 2912 2913This is an optional function and, if implemented, is expected to perform 2914platform specific actions before the CPU is powered down. Since this function is 2915invoked outside the PSCI locks, the actions performed in this hook must be local 2916to the CPU or the platform must ensure that races between multiple CPUs cannot 2917occur. 2918 2919The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2920operation and it encodes the platform coordinated target local power states for 2921the CPU power domain and its parent power domain levels. 2922 2923It is preferred that this function returns. The caller will invoke 2924``psci_power_down_wfi()`` to powerdown the CPU, mitigate any powerdown errata, 2925and handle any wakeups that may arise. Previously, this function did not return 2926and instead called ``wfi`` (in an infinite loop) directly. This is still 2927possible on platforms where this is guaranteed to be terminal, however, it is 2928strongly discouraged going forward. 2929 2930plat_psci_ops.pwr_domain_on_finish() 2931.................................... 2932 2933This function is called by the PSCI implementation after the calling CPU is 2934powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2935It performs the platform-specific setup required to initialize enough state for 2936this CPU to enter the normal world and also provide secure runtime firmware 2937services. 2938 2939The ``target_state`` (first argument) is the prior state of the power domains 2940immediately before the CPU was turned on. It indicates which power domains 2941above the CPU might require initialization due to having previously been in 2942low power states. The generic code expects the handler to succeed. 2943 2944plat_psci_ops.pwr_domain_on_finish_late() [optional] 2945........................................................... 2946 2947This optional function is called by the PSCI implementation after the calling 2948CPU is fully powered on with respective data caches enabled. The calling CPU and 2949the associated cluster are guaranteed to be participating in coherency. This 2950function gives the flexibility to perform any platform-specific actions safely, 2951such as initialization or modification of shared data structures, without the 2952overhead of explicit cache maintainace operations. 2953 2954The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2955operation. The generic code expects the handler to succeed. 2956 2957plat_psci_ops.pwr_domain_suspend_finish() 2958......................................... 2959 2960This function is called by the PSCI implementation after the calling CPU is 2961powered on and released from reset in response to an asynchronous wakeup 2962event, for example a timer interrupt that was programmed by the CPU during the 2963``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2964setup required to restore the saved state for this CPU to resume execution 2965in the normal world and also provide secure runtime firmware services. 2966 2967The ``target_state`` (first argument) has a similar meaning as described in 2968the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2969to succeed. 2970 2971If the Distributor, Redistributors or ITS have been powered off as part of a 2972suspend, their context must be restored in this function in the reverse order 2973to how they were saved during suspend sequence. 2974 2975plat_psci_ops.system_off() 2976.......................... 2977 2978This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2979call. It performs the platform-specific system poweroff sequence after 2980notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 2981function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 2982 2983plat_psci_ops.system_reset() 2984............................ 2985 2986This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2987call. It performs the platform-specific system reset sequence after 2988notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 2989function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 2990 2991plat_psci_ops.validate_power_state() 2992.................................... 2993 2994This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2995call to validate the ``power_state`` parameter of the PSCI API and if valid, 2996populate it in ``req_state`` (second argument) array as power domain level 2997specific local states. If the ``power_state`` is invalid, the platform must 2998return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2999normal world PSCI client. 3000 3001plat_psci_ops.validate_ns_entrypoint() 3002...................................... 3003 3004This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 3005``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 3006parameter passed by the normal world. If the ``entry_point`` is invalid, 3007the platform must return PSCI_E_INVALID_ADDRESS as error, which is 3008propagated back to the normal world PSCI client. 3009 3010plat_psci_ops.get_sys_suspend_power_state() 3011........................................... 3012 3013This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 3014call to get the ``req_state`` parameter from platform which encodes the power 3015domain level specific local states to suspend to system affinity level. The 3016``req_state`` will be utilized to do the PSCI state coordination and 3017``pwr_domain_suspend()`` will be invoked with the coordinated target state to 3018enter system suspend. 3019 3020plat_psci_ops.get_pwr_lvl_state_idx() 3021..................................... 3022 3023This is an optional function and, if implemented, is invoked by the PSCI 3024implementation to convert the ``local_state`` (first argument) at a specified 3025``pwr_lvl`` (second argument) to an index between 0 and 3026``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 3027supports more than two local power states at each power domain level, that is 3028``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 3029local power states. 3030 3031plat_psci_ops.translate_power_state_by_mpidr() 3032.............................................. 3033 3034This is an optional function and, if implemented, verifies the ``power_state`` 3035(second argument) parameter of the PSCI API corresponding to a target power 3036domain. The target power domain is identified by using both ``MPIDR`` (first 3037argument) and the power domain level encoded in ``power_state``. The power domain 3038level specific local states are to be extracted from ``power_state`` and be 3039populated in the ``output_state`` (third argument) array. The functionality 3040is similar to the ``validate_power_state`` function described above and is 3041envisaged to be used in case the validity of ``power_state`` depend on the 3042targeted power domain. If the ``power_state`` is invalid for the targeted power 3043domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 3044function is not implemented, then the generic implementation relies on 3045``validate_power_state`` function to translate the ``power_state``. 3046 3047This function can also be used in case the platform wants to support local 3048power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 3049APIs as described in Section 5.18 of `PSCI`_. 3050 3051plat_psci_ops.get_node_hw_state() 3052................................. 3053 3054This is an optional function. If implemented this function is intended to return 3055the power state of a node (identified by the first parameter, the ``MPIDR``) in 3056the power domain topology (identified by the second parameter, ``power_level``), 3057as retrieved from a power controller or equivalent component on the platform. 3058Upon successful completion, the implementation must map and return the final 3059status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 3060must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 3061appropriate. 3062 3063Implementations are not expected to handle ``power_levels`` greater than 3064``PLAT_MAX_PWR_LVL``. 3065 3066plat_psci_ops.system_reset2() 3067............................. 3068 3069This is an optional function. If implemented this function is 3070called during the ``SYSTEM_RESET2`` call to perform a reset 3071based on the first parameter ``reset_type`` as specified in 3072`PSCI`_. The parameter ``cookie`` can be used to pass additional 3073reset information. If the ``reset_type`` is not supported, the 3074function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 3075resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 3076and vendor reset can return other PSCI error codes as defined 3077in `PSCI`_. If this function returns success, the caller will call 3078``wfi`` similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3079 3080plat_psci_ops.write_mem_protect() 3081................................. 3082 3083This is an optional function. If implemented it enables or disables the 3084``MEM_PROTECT`` functionality based on the value of ``val``. 3085A non-zero value enables ``MEM_PROTECT`` and a value of zero 3086disables it. Upon encountering failures it must return a negative value 3087and on success it must return 0. 3088 3089plat_psci_ops.read_mem_protect() 3090................................ 3091 3092This is an optional function. If implemented it returns the current 3093state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 3094failures it must return a negative value and on success it must 3095return 0. 3096 3097plat_psci_ops.mem_protect_chk() 3098............................... 3099 3100This is an optional function. If implemented it checks if a memory 3101region defined by a base address ``base`` and with a size of ``length`` 3102bytes is protected by ``MEM_PROTECT``. If the region is protected 3103then it must return 0, otherwise it must return a negative number. 3104 3105.. _porting_guide_imf_in_bl31: 3106 3107Interrupt Management framework (in BL31) 3108---------------------------------------- 3109 3110BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 3111generated in either security state and targeted to EL1 or EL2 in the non-secure 3112state or EL3/S-EL1 in the secure state. The design of this framework is 3113described in the :ref:`Interrupt Management Framework` 3114 3115A platform should export the following APIs to support the IMF. The following 3116text briefly describes each API and its implementation in Arm standard 3117platforms. The API implementation depends upon the type of interrupt controller 3118present in the platform. Arm standard platform layer supports both 3119`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 3120and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 3121FVP can be configured to use either GICv2 or GICv3 depending on the build flag 3122``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 3123details). 3124 3125See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 3126 3127Function : plat_interrupt_type_to_line() [mandatory] 3128~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3129 3130:: 3131 3132 Argument : uint32_t, uint32_t 3133 Return : uint32_t 3134 3135The Arm processor signals an interrupt exception either through the IRQ or FIQ 3136interrupt line. The specific line that is signaled depends on how the interrupt 3137controller (IC) reports different interrupt types from an execution context in 3138either security state. The IMF uses this API to determine which interrupt line 3139the platform IC uses to signal each type of interrupt supported by the framework 3140from a given security state. This API must be invoked at EL3. 3141 3142The first parameter will be one of the ``INTR_TYPE_*`` values (see 3143:ref:`Interrupt Management Framework`) indicating the target type of the 3144interrupt, the second parameter is the security state of the originating 3145execution context. The return result is the bit position in the ``SCR_EL3`` 3146register of the respective interrupt trap: IRQ=1, FIQ=2. 3147 3148In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3149configured as FIQs and Non-secure interrupts as IRQs from either security 3150state. 3151 3152In the case of Arm standard platforms using GICv3, the interrupt line to be 3153configured depends on the security state of the execution context when the 3154interrupt is signalled and are as follows: 3155 3156- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3157 NS-EL0/1/2 context. 3158- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3159 in the NS-EL0/1/2 context. 3160- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3161 context. 3162 3163Function : plat_ic_get_pending_interrupt_type() [mandatory] 3164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3165 3166:: 3167 3168 Argument : void 3169 Return : uint32_t 3170 3171This API returns the type of the highest priority pending interrupt at the 3172platform IC. The IMF uses the interrupt type to retrieve the corresponding 3173handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3174pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3175``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3176 3177In the case of Arm standard platforms using GICv2, the *Highest Priority 3178Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3179the pending interrupt. The type of interrupt depends upon the id value as 3180follows. 3181 3182#. id < 1022 is reported as a S-EL1 interrupt 3183#. id = 1022 is reported as a Non-secure interrupt. 3184#. id = 1023 is reported as an invalid interrupt type. 3185 3186In the case of Arm standard platforms using GICv3, the system register 3187``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3188is read to determine the id of the pending interrupt. The type of interrupt 3189depends upon the id value as follows. 3190 3191#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3192#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3193#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3194#. All other interrupt id's are reported as EL3 interrupt. 3195 3196Function : plat_ic_get_pending_interrupt_id() [mandatory] 3197~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3198 3199:: 3200 3201 Argument : void 3202 Return : uint32_t 3203 3204This API returns the id of the highest priority pending interrupt at the 3205platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3206pending. 3207 3208In the case of Arm standard platforms using GICv2, the *Highest Priority 3209Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3210pending interrupt. The id that is returned by API depends upon the value of 3211the id read from the interrupt controller as follows. 3212 3213#. id < 1022. id is returned as is. 3214#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3215 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3216 This id is returned by the API. 3217#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3218 3219In the case of Arm standard platforms using GICv3, if the API is invoked from 3220EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3221group 0 Register*, is read to determine the id of the pending interrupt. The id 3222that is returned by API depends upon the value of the id read from the 3223interrupt controller as follows. 3224 3225#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3226#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3227 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3228 Register* is read to determine the id of the group 1 interrupt. This id 3229 is returned by the API as long as it is a valid interrupt id 3230#. If the id is any of the special interrupt identifiers, 3231 ``INTR_ID_UNAVAILABLE`` is returned. 3232 3233When the API invoked from S-EL1 for GICv3 systems, the id read from system 3234register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3235Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3236``INTR_ID_UNAVAILABLE`` is returned. 3237 3238Function : plat_ic_acknowledge_interrupt() [mandatory] 3239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3240 3241:: 3242 3243 Argument : void 3244 Return : uint32_t 3245 3246This API is used by the CPU to indicate to the platform IC that processing of 3247the highest pending interrupt has begun. It should return the raw, unmodified 3248value obtained from the interrupt controller when acknowledging an interrupt. 3249The actual interrupt number shall be extracted from this raw value using the API 3250`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3251 3252This function in Arm standard platforms using GICv2, reads the *Interrupt 3253Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3254priority pending interrupt from pending to active in the interrupt controller. 3255It returns the value read from the ``GICC_IAR``, unmodified. 3256 3257In the case of Arm standard platforms using GICv3, if the API is invoked 3258from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3259Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3260reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3261group 1*. The read changes the state of the highest pending interrupt from 3262pending to active in the interrupt controller. The value read is returned 3263unmodified. 3264 3265The TSP uses this API to start processing of the secure physical timer 3266interrupt. 3267 3268Function : plat_ic_end_of_interrupt() [mandatory] 3269~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3270 3271:: 3272 3273 Argument : uint32_t 3274 Return : void 3275 3276This API is used by the CPU to indicate to the platform IC that processing of 3277the interrupt corresponding to the id (passed as the parameter) has 3278finished. The id should be the same as the id returned by the 3279``plat_ic_acknowledge_interrupt()`` API. 3280 3281Arm standard platforms write the id to the *End of Interrupt Register* 3282(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3283system register in case of GICv3 depending on where the API is invoked from, 3284EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3285controller. 3286 3287The TSP uses this API to finish processing of the secure physical timer 3288interrupt. 3289 3290Function : plat_ic_get_interrupt_type() [mandatory] 3291~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3292 3293:: 3294 3295 Argument : uint32_t 3296 Return : uint32_t 3297 3298This API returns the type of the interrupt id passed as the parameter. 3299``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3300interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3301returned depending upon how the interrupt has been configured by the platform 3302IC. This API must be invoked at EL3. 3303 3304Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3305and Non-secure interrupts as Group1 interrupts. It reads the group value 3306corresponding to the interrupt id from the relevant *Interrupt Group Register* 3307(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3308 3309In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3310Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3311(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3312as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3313 3314Registering a console 3315--------------------- 3316 3317Platforms will need to implement the TF-A console framework to register and use 3318a console for visual data output in TF-A. These can be used for data output during 3319the different stages of the firmware boot process and also for debugging purposes. 3320 3321The console framework can be used to output data on to a console using a number of 3322TF-A supported UARTs. Multiple consoles can be registered at the same time with 3323different output scopes (BOOT, RUNTIME, CRASH) so that data can be displayed on 3324their respective consoles without unnecessary cluttering of a single console. 3325 3326Information for registering a console can be found in the :ref:`Console Framework` section 3327of the :ref:`System Design` documentation. 3328 3329Common helper functions 3330----------------------- 3331Function : elx_panic() 3332~~~~~~~~~~~~~~~~~~~~~~ 3333 3334:: 3335 3336 Argument : void 3337 Return : void 3338 3339This API is called from assembly files when reporting a critical failure 3340that has occured in lower EL and is been trapped in EL3. This call 3341**must not** return. 3342 3343Function : el3_panic() 3344~~~~~~~~~~~~~~~~~~~~~~ 3345 3346:: 3347 3348 Argument : void 3349 Return : void 3350 3351This API is called from assembly files when encountering a critical failure that 3352cannot be recovered from. This function assumes that it is invoked from a C 3353runtime environment i.e. valid stack exists. This call **must not** return. 3354 3355Function : panic() 3356~~~~~~~~~~~~~~~~~~ 3357 3358:: 3359 3360 Argument : void 3361 Return : void 3362 3363This API called from C files when encountering a critical failure that cannot 3364be recovered from. This function in turn prints backtrace (if enabled) and calls 3365el3_panic(). This call **must not** return. 3366 3367Crash Reporting mechanism (in BL31) 3368----------------------------------- 3369 3370BL31 implements a crash reporting mechanism which prints the various registers 3371of the CPU to enable quick crash analysis and debugging. This mechanism relies 3372on the platform implementing ``plat_crash_console_init``, 3373``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3374 3375The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3376implementation of all of them. Platforms may include this file to their 3377makefiles in order to benefit from them. By default, they will cause the crash 3378output to be routed over the normal console infrastructure and get printed on 3379consoles configured to output in crash state. ``console_set_scope()`` can be 3380used to control whether a console is used for crash output. 3381 3382.. note:: 3383 Platforms are responsible for making sure that they only mark consoles for 3384 use in the crash scope that are able to support this, i.e. that are written 3385 in assembly and conform with the register clobber rules for putc() 3386 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3387 3388In some cases (such as debugging very early crashes that happen before the 3389normal boot console can be set up), platforms may want to control crash output 3390more explicitly. These platforms may instead provide custom implementations for 3391these. They are executed outside of a C environment and without a stack. Many 3392console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3393that are designed to be used by these functions. See Arm platforms (like juno) 3394for an example of this. 3395 3396Function : plat_crash_console_init [mandatory] 3397~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3398 3399:: 3400 3401 Argument : void 3402 Return : int 3403 3404This API is used by the crash reporting mechanism to initialize the crash 3405console. It must only use the general purpose registers x0 through x7 to do the 3406initialization and returns 1 on success. 3407 3408Function : plat_crash_console_putc [mandatory] 3409~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3410 3411:: 3412 3413 Argument : int 3414 Return : int 3415 3416This API is used by the crash reporting mechanism to print a character on the 3417designated crash console. It must only use general purpose registers x1 and 3418x2 to do its work. The parameter and the return value are in general purpose 3419register x0. 3420 3421Function : plat_crash_console_flush [mandatory] 3422~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3423 3424:: 3425 3426 Argument : void 3427 Return : void 3428 3429This API is used by the crash reporting mechanism to force write of all buffered 3430data on the designated crash console. It should only use general purpose 3431registers x0 through x5 to do its work. 3432 3433Function : plat_setup_early_console [optional] 3434~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3435 3436:: 3437 3438 Argument : void 3439 Return : void 3440 3441This API is used to setup the early console, it is required only if the flag 3442``EARLY_CONSOLE`` is enabled. 3443 3444.. _External Abort handling and RAS Support: 3445 3446External Abort handling and RAS Support 3447--------------------------------------- 3448 3449Function : plat_ea_handler 3450~~~~~~~~~~~~~~~~~~~~~~~~~~ 3451 3452:: 3453 3454 Argument : int 3455 Argument : uint64_t 3456 Argument : void * 3457 Argument : void * 3458 Argument : uint64_t 3459 Return : void 3460 3461This function is invoked by the runtime exception handling framework for the 3462platform to handle an External Abort received at EL3. The intention of the 3463function is to attempt to resolve the cause of External Abort and return; 3464if that's not possible then an orderly shutdown of the system is initiated. 3465 3466The first parameter (``int ea_reason``) indicates the reason for External Abort. 3467Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3468 3469The second parameter (``uint64_t syndrome``) is the respective syndrome 3470presented to EL3 after having received the External Abort. Depending on the 3471nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3472can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3473 3474The third parameter (``void *cookie``) is unused for now. The fourth parameter 3475(``void *handle``) is a pointer to the preempted context. The fifth parameter 3476(``uint64_t flags``) indicates the preempted security state. These parameters 3477are received from the top-level exception handler. 3478 3479This function must be implemented if a platform expects Firmware First handling 3480of External Aborts. 3481 3482Function : plat_handle_uncontainable_ea 3483~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3484 3485:: 3486 3487 Argument : int 3488 Argument : uint64_t 3489 Return : void 3490 3491This function is invoked by the RAS framework when an External Abort of 3492Uncontainable type is received at EL3. Due to the critical nature of 3493Uncontainable errors, the intention of this function is to initiate orderly 3494shutdown of the system, and is not expected to return. 3495 3496This function must be implemented in assembly. 3497 3498The first and second parameters are the same as that of ``plat_ea_handler``. 3499 3500The default implementation of this function calls 3501``report_unhandled_exception``. 3502 3503Function : plat_handle_double_fault 3504~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3505 3506:: 3507 3508 Argument : int 3509 Argument : uint64_t 3510 Return : void 3511 3512This function is invoked by the RAS framework when another External Abort is 3513received at EL3 while one is already being handled. I.e., a call to 3514``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3515this function is to initiate orderly shutdown of the system, and is not expected 3516recover or return. 3517 3518This function must be implemented in assembly. 3519 3520The first and second parameters are the same as that of ``plat_ea_handler``. 3521 3522The default implementation of this function calls 3523``report_unhandled_exception``. 3524 3525Function : plat_handle_el3_ea 3526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3527 3528:: 3529 3530 Return : void 3531 3532This function is invoked when an External Abort is received while executing in 3533EL3. Due to its critical nature, the intention of this function is to initiate 3534orderly shutdown of the system, and is not expected recover or return. 3535 3536This function must be implemented in assembly. 3537 3538The default implementation of this function calls 3539``report_unhandled_exception``. 3540 3541Function : plat_handle_rng_trap 3542~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3543 3544:: 3545 3546 Argument : uint64_t 3547 Argument : cpu_context_t * 3548 Return : int 3549 3550This function is invoked by BL31's exception handler when there is a synchronous 3551system register trap caused by access to the RNDR or RNDRRS registers. It allows 3552platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3553emulate those system registers by returing back some entropy to the lower EL. 3554 3555The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3556syndrome register, which encodes the instruction that was trapped. The interesting 3557information in there is the target register (``get_sysreg_iss_rt()``). 3558 3559The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3560lower exception level, at the time when the execution of the ``mrs`` instruction 3561was trapped. Its content can be changed, to put the entropy into the target 3562register. 3563 3564The return value indicates how to proceed: 3565 3566- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3567- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3568 to the same instruction, so its execution will be repeated. 3569- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3570 to the next instruction. 3571 3572This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3573 3574Function : plat_handle_impdef_trap 3575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3576 3577:: 3578 3579 Argument : uint64_t 3580 Argument : cpu_context_t * 3581 Return : int 3582 3583This function is invoked by BL31's exception handler when there is a synchronous 3584system register trap caused by access to the implementation defined registers. 3585It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3586registers choosing to program bits of their choice. If using in combination with 3587``ARCH_FEATURE_AVAILABILITY``, the macros 3588{SCR,MDCR,CPTR}_PLAT_{BITS,IGNORED,FLIPPED} should be defined to report correct 3589results. 3590 3591The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3592syndrome register, which encodes the instruction that was trapped. 3593 3594The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3595lower exception level, at the time when the execution of the ``mrs`` instruction 3596was trapped. 3597 3598The return value indicates how to proceed: 3599 3600- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3601- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3602 to the same instruction, so its execution will be repeated. 3603- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3604 to the next instruction. 3605 3606This function needs to be implemented by a platform if it enables 3607IMPDEF_SYSREG_TRAP. 3608 3609Build flags 3610----------- 3611 3612There are some build flags which can be defined by the platform to control 3613inclusion or exclusion of certain BL stages from the FIP image. These flags 3614need to be defined in the platform makefile which will get included by the 3615build system. 3616 3617- **NEED_BL33** 3618 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3619 build option should be supplied as a build option. The platform has the 3620 option of excluding the BL33 image in the ``fip`` image by defining this flag 3621 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3622 are used, this flag will be set to ``no`` automatically. 3623 3624- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** 3625 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, 3626 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and 3627 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch 3628 version will be enabled by default and any optional Arch feature supported by 3629 the Architecture and available in TF-A can be enabled from platform specific 3630 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory 3631 and optional Arch specific features. 3632 3633Platform include paths 3634---------------------- 3635 3636Platforms are allowed to add more include paths to be passed to the compiler. 3637The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3638particular for the file ``platform_def.h``. 3639 3640Example: 3641 3642.. code:: c 3643 3644 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3645 3646C Library 3647--------- 3648 3649To avoid subtle toolchain behavioral dependencies, the header files provided 3650by the compiler are not used. The software is built with the ``-nostdinc`` flag 3651to ensure no headers are included from the toolchain inadvertently. Instead the 3652required headers are included in the TF-A source tree. The library only 3653contains those C library definitions required by the local implementation. If 3654more functionality is required, the needed library functions will need to be 3655added to the local implementation. 3656 3657Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3658been written specifically for TF-A. Some implementation files have been obtained 3659from `FreeBSD`_, others have been written specifically for TF-A as well. The 3660files can be found in ``include/lib/libc`` and ``lib/libc``. 3661 3662SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3663can be obtained from http://github.com/freebsd/freebsd. 3664 3665Storage abstraction layer 3666------------------------- 3667 3668In order to improve platform independence and portability a storage abstraction 3669layer is used to load data from non-volatile platform storage. Currently 3670storage access is only required by BL1 and BL2 phases and performed inside the 3671``load_image()`` function in ``bl_common.c``. 3672 3673.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3674 3675It is mandatory to implement at least one storage driver. For the Arm 3676development platforms the Firmware Image Package (FIP) driver is provided as 3677the default means to load data from storage (see :ref:`firmware_design_fip`). 3678The storage layer is described in the header file 3679``include/drivers/io/io_storage.h``. The implementation of the common library is 3680in ``drivers/io/io_storage.c`` and the driver files are located in 3681``drivers/io/``. 3682 3683.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3684 3685Each IO driver must provide ``io_dev_*`` structures, as described in 3686``drivers/io/io_driver.h``. These are returned via a mandatory registration 3687function that is called on platform initialization. The semi-hosting driver 3688implementation in ``io_semihosting.c`` can be used as an example. 3689 3690Each platform should register devices and their drivers via the storage 3691abstraction layer. These drivers then need to be initialized by bootloader 3692phases as required in their respective ``blx_platform_setup()`` functions. 3693 3694.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3695 3696The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3697initialize storage devices before IO operations are called. 3698 3699.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3700 3701The basic operations supported by the layer 3702include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3703Drivers do not have to implement all operations, but each platform must 3704provide at least one driver for a device capable of supporting generic 3705operations such as loading a bootloader image. 3706 3707The current implementation only allows for known images to be loaded by the 3708firmware. These images are specified by using their identifiers, as defined in 3709``include/plat/common/common_def.h`` (or a separate header file included from 3710there). The platform layer (``plat_get_image_source()``) then returns a reference 3711to a device and a driver-specific ``spec`` which will be understood by the driver 3712to allow access to the image data. 3713 3714The layer is designed in such a way that is it possible to chain drivers with 3715other drivers. For example, file-system drivers may be implemented on top of 3716physical block devices, both represented by IO devices with corresponding 3717drivers. In such a case, the file-system "binding" with the block device may 3718be deferred until the file-system device is initialised. 3719 3720The abstraction currently depends on structures being statically allocated 3721by the drivers and callers, as the system does not yet provide a means of 3722dynamically allocating memory. This may also have the affect of limiting the 3723amount of open resources per driver. 3724 3725Measured Boot Platform Interface 3726-------------------------------- 3727 3728Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 3729to :ref:`Measured Boot Design` for more details. 3730 3731-------------- 3732 3733*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 3734 3735.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 3736.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3737.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3738.. _FreeBSD: https://www.freebsd.org 3739.. _SCC: http://www.simple-cc.org/ 3740.. _DRTM: https://developer.arm.com/documentation/den0113/a 3741