1/* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_a77, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_a77, CVE(2024, 5660) 33 34check_erratum_ls cortex_a77, CVE(2024, 5660), CPU_REV(1, 1) 35 36workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 37 /* move cpu revision in again and compare against r0p0 */ 38 mov x0, x7 39 cpu_rev_var_ls CPU_REV(0, 0) 40 cbz x0, 1f 41 42 ldr x0, =0x0 43 msr CORTEX_A77_CPUPSELR_EL3, x0 44 ldr x0, =0x00E8400000 45 msr CORTEX_A77_CPUPOR_EL3, x0 46 ldr x0, =0x00FFE00000 47 msr CORTEX_A77_CPUPMR_EL3, x0 48 ldr x0, =0x4004003FF 49 msr CORTEX_A77_CPUPCR_EL3, x0 50 ldr x0, =0x1 51 msr CORTEX_A77_CPUPSELR_EL3, x0 52 ldr x0, =0x00E8C00040 53 msr CORTEX_A77_CPUPOR_EL3, x0 54 ldr x0, =0x00FFE00040 55 msr CORTEX_A77_CPUPMR_EL3, x0 56 b 2f 571: 58 ldr x0, =0x0 59 msr CORTEX_A77_CPUPSELR_EL3, x0 60 ldr x0, =0x00E8400000 61 msr CORTEX_A77_CPUPOR_EL3, x0 62 ldr x0, =0x00FF600000 63 msr CORTEX_A77_CPUPMR_EL3, x0 64 ldr x0, =0x00E8E00080 65 msr CORTEX_A77_CPUPOR2_EL3, x0 66 ldr x0, =0x00FFE000C0 67 msr CORTEX_A77_CPUPMR2_EL3, x0 682: 69 ldr x0, =0x04004003FF 70 msr CORTEX_A77_CPUPCR_EL3, x0 71workaround_reset_end cortex_a77, ERRATUM(1508412) 72 73check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 74 75workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 76 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 77workaround_reset_end cortex_a77, ERRATUM(1791578) 78 79check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 80 81workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 82 /* Disable allocation of splintered pages in the L2 TLB */ 83 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 84workaround_reset_end cortex_a77, ERRATUM(1800714) 85 86check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 87 88workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 89 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 90workaround_reset_end cortex_a77, ERRATUM(1925769) 91 92check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 93 94workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 95 ldr x0,=0x4 96 msr CORTEX_A77_CPUPSELR_EL3,x0 97 ldr x0,=0x10E3900002 98 msr CORTEX_A77_CPUPOR_EL3,x0 99 ldr x0,=0x10FFF00083 100 msr CORTEX_A77_CPUPMR_EL3,x0 101 ldr x0,=0x2001003FF 102 msr CORTEX_A77_CPUPCR_EL3,x0 103 104 ldr x0,=0x5 105 msr CORTEX_A77_CPUPSELR_EL3,x0 106 ldr x0,=0x10E3800082 107 msr CORTEX_A77_CPUPOR_EL3,x0 108 ldr x0,=0x10FFF00083 109 msr CORTEX_A77_CPUPMR_EL3,x0 110 ldr x0,=0x2001003FF 111 msr CORTEX_A77_CPUPCR_EL3,x0 112 113 ldr x0,=0x6 114 msr CORTEX_A77_CPUPSELR_EL3,x0 115 ldr x0,=0x10E3800200 116 msr CORTEX_A77_CPUPOR_EL3,x0 117 ldr x0,=0x10FFF003E0 118 msr CORTEX_A77_CPUPMR_EL3,x0 119 ldr x0,=0x2001003FF 120 msr CORTEX_A77_CPUPCR_EL3,x0 121workaround_reset_end cortex_a77, ERRATUM(1946167) 122 123check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 124 125workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 126 sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 127workaround_reset_end cortex_a77, ERRATUM(2356587) 128 129check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 130 131workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 132 /* dsb before isb of power down sequence */ 133 dsb sy 134workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 135 136check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 137 138workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 139#if IMAGE_BL31 140 /* 141 * The Cortex-A77 generic vectors are overridden to apply errata 142 * mitigation on exception entry from lower ELs. 143 */ 144 adr x0, wa_cve_vbar_cortex_a77 145 msr vbar_el3, x0 146#endif /* IMAGE_BL31 */ 147workaround_reset_end cortex_a77, CVE(2022, 23960) 148 149check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 150 151 /* ------------------------------------------------- 152 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 153 * ------------------------------------------------- 154 */ 155cpu_reset_func_start cortex_a77 156cpu_reset_func_end cortex_a77 157 158 /* --------------------------------------------- 159 * HW will do the cache maintenance while powering down 160 * --------------------------------------------- 161 */ 162func cortex_a77_core_pwr_dwn 163 /* --------------------------------------------- 164 * Enable CPU power down bit in power control register 165 * --------------------------------------------- 166 */ 167 sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ 168 CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 169 170 apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV 171 172 isb 173 ret 174endfunc cortex_a77_core_pwr_dwn 175 176 /* --------------------------------------------- 177 * This function provides Cortex-A77 specific 178 * register information for crash reporting. 179 * It needs to return with x6 pointing to 180 * a list of register names in ascii and 181 * x8 - x15 having values of registers to be 182 * reported. 183 * --------------------------------------------- 184 */ 185.section .rodata.cortex_a77_regs, "aS" 186cortex_a77_regs: /* The ascii list of register names to be reported */ 187 .asciz "cpuectlr_el1", "" 188 189func cortex_a77_cpu_reg_dump 190 adr x6, cortex_a77_regs 191 mrs x8, CORTEX_A77_CPUECTLR_EL1 192 ret 193endfunc cortex_a77_cpu_reg_dump 194 195declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 196 cortex_a77_reset_func, \ 197 cortex_a77_core_pwr_dwn 198