1/* 2 * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720_ae.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue cortex_a720_ae 25 26.global check_erratum_cortex_a720_ae_3699562 27 28add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562 29 30check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0) 31 32cpu_reset_func_start cortex_a720_ae 33 /* Disable speculative loads */ 34 msr SSBS, xzr 35cpu_reset_func_end cortex_a720_ae 36 37 /* ---------------------------------------------------- 38 * HW will do the cache maintenance while powering down 39 * ---------------------------------------------------- 40 */ 41func cortex_a720_ae_core_pwr_dwn 42 /* --------------------------------------------------- 43 * Enable CPU power down bit in power control register 44 * --------------------------------------------------- 45 */ 46 sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 47 48 isb 49 ret 50endfunc cortex_a720_ae_core_pwr_dwn 51 52 /* --------------------------------------------- 53 * This function provides Cortex-A720AE specific 54 * register information for crash reporting. 55 * It needs to return with x6 pointing to 56 * a list of register names in ascii and 57 * x8 - x15 having values of registers to be 58 * reported. 59 * --------------------------------------------- 60 */ 61.section .rodata.cortex_a720_ae_regs, "aS" 62cortex_a720_ae_regs: /* The ascii list of register names to be reported */ 63 .asciz "cpuectlr_el1", "" 64 65func cortex_a720_ae_cpu_reg_dump 66 adr x6, cortex_a720_ae_regs 67 mrs x8, CORTEX_A720_AE_CPUECTLR_EL1 68 ret 69endfunc cortex_a720_ae_cpu_reg_dump 70 71declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \ 72 cortex_a720_ae_reset_func, \ 73 cortex_a720_ae_core_pwr_dwn 74