1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <cpu_macros.S> 9#include <qemu_max.h> 10 11func qemu_max_core_pwr_dwn 12 /* --------------------------------------------- 13 * Disable the Data Cache. 14 * --------------------------------------------- 15 */ 16 mrs x1, sctlr_el3 17 bic x1, x1, #SCTLR_C_BIT 18 msr sctlr_el3, x1 19 isb 20 21 /* --------------------------------------------- 22 * Flush L1 cache to L2. 23 * --------------------------------------------- 24 */ 25 mov x18, lr 26 mov x0, #DCCISW 27 bl dcsw_op_level1 28 mov lr, x18 29 ret 30endfunc qemu_max_core_pwr_dwn 31 32func qemu_max_cluster_pwr_dwn 33 /* --------------------------------------------- 34 * Disable the Data Cache. 35 * --------------------------------------------- 36 */ 37 mrs x1, sctlr_el3 38 bic x1, x1, #SCTLR_C_BIT 39 msr sctlr_el3, x1 40 isb 41 42 /* --------------------------------------------- 43 * Flush all caches to PoC. 44 * --------------------------------------------- 45 */ 46 mov x0, #DCCISW 47 b dcsw_op_all 48endfunc qemu_max_cluster_pwr_dwn 49 50cpu_reset_func_start qemu_max 51cpu_reset_func_end qemu_max 52 53 /* --------------------------------------------- 54 * This function provides cpu specific 55 * register information for crash reporting. 56 * It needs to return with x6 pointing to 57 * a list of register names in ascii and 58 * x8 - x15 having values of registers to be 59 * reported. 60 * --------------------------------------------- 61 */ 62.section .rodata.qemu_max_regs, "aS" 63qemu_max_regs: /* The ascii list of register names to be reported */ 64 .asciz "" /* no registers to report */ 65 66func qemu_max_cpu_reg_dump 67 adr x6, qemu_max_regs 68 ret 69endfunc qemu_max_cpu_reg_dump 70 71 72/* cpu_ops for QEMU MAX */ 73declare_cpu_ops qemu_max, QEMU_MAX_MIDR, qemu_max_reset_func, \ 74 qemu_max_core_pwr_dwn, \ 75 qemu_max_cluster_pwr_dwn 76