| d9bb9779 | 22-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
docs(maintainers): update nxp layerscape maintainers
Added myself to be NXP common code and ls1028a, ls1043a platforms
maintainer.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iadffc56
docs(maintainers): update nxp layerscape maintainers
Added myself to be NXP common code and ls1028a, ls1043a platforms
maintainer.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iadffc5600e9bb2e94b1d545b8dd1a819358cabcb
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| 168a2012 | 22-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
docs(plat/nxp/layerscape): add ls1043a soc and board support
Update document for nxp-layerscape to add ls1043a SoC and ls1043ardb
board support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Chang
docs(plat/nxp/layerscape): add ls1043a soc and board support
Update document for nxp-layerscape to add ls1043a SoC and ls1043ardb
board support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8442daf08a0f7c1ba982a3ed1d0ad24c4c420185
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| ff4ec0a0 | 22-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
refactor(plat/ls1043): remove old implementation for platform ls1043
Remove old implementation for Layerscape ls1043a platform, and
will added it back with unified software architecture of all
Layer
refactor(plat/ls1043): remove old implementation for platform ls1043
Remove old implementation for Layerscape ls1043a platform, and
will added it back with unified software architecture of all
Layerscape platforms.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If038c19ab04d70050ec8e6ab2097b1c4f8324e87
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| 0aa0b3af | 16-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by m
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
Measured-Boot and Trusted-Boot are orthogonal to each other and hence
removed dependency of Trusted-Boot on Measured-Boot by making below
changes -
1. BL1 and BL2 main functions are used for initializing Crypto module
instead of the authentication module
2. Updated Crypto module registration macro for MEASURED_BOOT with only
necessary callbacks for calculating image hashes
3. The 'load_auth_image' function is now used for the image measurement
during Trusted or Non-Trusted Boot flow
Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 42309987 | 06-Jan-2022 |
André Przywara <andre.przywara@arm.com> |
Merge changes Icf5e3045,Ie5fb0b72 into integration
* changes:
docs(allwinner): update SoC list and build options
docs(allwinner): add SUNXI_SETUP_REGULATORS build option |
| f2b2cc14 | 27-Dec-2021 |
Andre Przywara <andre.przywara@arm.com> |
docs(allwinner): update SoC list and build options
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to t
docs(allwinner): update SoC list and build options
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
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| aa616990 | 27-Dec-2021 |
Andre Przywara <andre.przywara@arm.com> |
docs(allwinner): add SUNXI_SETUP_REGULATORS build option
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.
Signed-off-by:
docs(allwinner): add SUNXI_SETUP_REGULATORS build option
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a
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| b48121b6 | 22-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2058056" into integration |
| 47833abd | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integration |
| c2d75fa7 | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration |
| c8076a0e | 21-Dec-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(doc): update TF-A v2.7 release date in the release information page" into integration |
| e16045de | 03-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)
However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
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| 3e80e840 | 21-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(doc): update TF-A v2.7 release date in the release information page
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iae84f82518ab89edc204a23083d5f4168449c2bf |
| 34ee76db | 02-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
SDEN can b
fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
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|
| 1db6cd60 | 01-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found he
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
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| e6b1a9ab | 16-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integration |
| e119c205 | 16-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(ff-a): boot order field of SPs manifest" into integration |
| dc669220 | 10-Nov-2021 |
Gary Morrison <gary.morrison@arm.com> |
feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support
Threat model for the current, BL1-only R-class support.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf391928
feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support
Threat model for the current, BL1-only R-class support.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf3919281cc8dc1f21cada9511e0
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| c1ff1791 | 14-Dec-2021 |
J-Alves <joao.alves@arm.com> |
docs(ff-a): boot order field of SPs manifest
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
docs(ff-a): boot order field of SPs manifest
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9fd070100ee52e0d465d2cce830cc91d78bddfc0
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| a5645148 | 13-Dec-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "jc/AMUv1" into integration
* changes:
docs(build-options): add build macros for features FGT,AMUv1 and ECV
fix(amu): fault handling on EL2 context switch |
| 64017767 | 05-Dec-2021 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
docs(build-options): add build macros for features FGT,AMUv1 and ECV
This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access
docs(build-options): add build macros for features FGT,AMUv1 and ECV
This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access to the set
of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the
influence of these features during context save and restore routines.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0
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| 43997d22 | 21-Oct-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(measured-boot): add a platform function for critical data
Added a platform function to measure the critical data and record its
measurement.
Also, corrected a return value of 'plat_mboot_measur
docs(measured-boot): add a platform function for critical data
Added a platform function to measure the critical data and record its
measurement.
Also, corrected a return value of 'plat_mboot_measure_image' function
in the documentation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I576676f654e517c2010ca1d5a87a1f7277d581c3
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| 8b3e2cc7 | 06-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(docs): update the v2.6 change-log
Updated the v2.6 change-log for below:
1. Moved ETE/ETM related changes under separate scope
2. Added manually commit log for Demeter CPU
Change-Id: Ib5b5f994f
fix(docs): update the v2.6 change-log
Updated the v2.6 change-log for below:
1. Moved ETE/ETM related changes under separate scope
2. Added manually commit log for Demeter CPU
Change-Id: Ib5b5f994f603af6c82b1400256752581a7931268
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 53863c84 | 19-Nov-2021 |
Yann Gautier <yann.gautier@st.com> |
docs: mark STM32MP_USE_STM32IMAGE as deprecated
This macro was used for the legacy boot mode on SPM32MP platforms.
The recommended boot method is now FIP.
The code under this macro will be removed a
docs: mark STM32MP_USE_STM32IMAGE as deprecated
This macro was used for the legacy boot mode on SPM32MP platforms.
The recommended boot method is now FIP.
The code under this macro will be removed after tag v2.7.
Change-Id: Id3b7baea2d3e6ea8b36a4cd0b107cb92591a172b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 27132f13 | 28-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=bu
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
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