1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #if ENABLE_RME 17 #include <lib/gpt_rme/gpt_rme.h> 18 #endif 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_compat.h> 21 #include <plat/arm/common/plat_arm.h> 22 #include <plat/common/platform.h> 23 #include <platform_def.h> 24 25 /* 26 * Placeholder variables for copying the arguments that have been passed to 27 * BL31 from BL2. 28 */ 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 #if ENABLE_RME 32 static entry_point_info_t rmm_image_ep_info; 33 #endif 34 35 #if !RESET_TO_BL31 36 /* 37 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 38 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 39 */ 40 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 41 #endif 42 43 /* Weak definitions may be overridden in specific ARM standard platform */ 44 #pragma weak bl31_early_platform_setup2 45 #pragma weak bl31_platform_setup 46 #pragma weak bl31_plat_arch_setup 47 #pragma weak bl31_plat_get_next_image_ep_info 48 49 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 50 BL31_START, \ 51 BL31_END - BL31_START, \ 52 MT_MEMORY | MT_RW | EL3_PAS) 53 #if RECLAIM_INIT_CODE 54 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 55 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 56 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 57 58 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 59 ~(PAGE_SIZE - 1)) 60 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 61 ~(PAGE_SIZE - 1)) 62 63 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 64 BL_INIT_CODE_BASE, \ 65 BL_INIT_CODE_END \ 66 - BL_INIT_CODE_BASE, \ 67 MT_CODE | EL3_PAS) 68 #endif 69 70 #if SEPARATE_NOBITS_REGION 71 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 72 BL31_NOBITS_BASE, \ 73 BL31_NOBITS_LIMIT \ 74 - BL31_NOBITS_BASE, \ 75 MT_MEMORY | MT_RW | EL3_PAS) 76 77 #endif 78 /******************************************************************************* 79 * Return a pointer to the 'entry_point_info' structure of the next image for the 80 * security state specified. BL33 corresponds to the non-secure image type 81 * while BL32 corresponds to the secure image type. A NULL pointer is returned 82 * if the image does not exist. 83 ******************************************************************************/ 84 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 85 { 86 entry_point_info_t *next_image_info; 87 88 assert(sec_state_is_valid(type)); 89 if (type == NON_SECURE) { 90 next_image_info = &bl33_image_ep_info; 91 } 92 #if ENABLE_RME 93 else if (type == REALM) { 94 next_image_info = &rmm_image_ep_info; 95 } 96 #endif 97 else { 98 next_image_info = &bl32_image_ep_info; 99 } 100 101 /* 102 * None of the images on the ARM development platforms can have 0x0 103 * as the entrypoint 104 */ 105 if (next_image_info->pc) 106 return next_image_info; 107 else 108 return NULL; 109 } 110 111 /******************************************************************************* 112 * Perform any BL31 early platform setup common to ARM standard platforms. 113 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 114 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 115 * done before the MMU is initialized so that the memory layout can be used 116 * while creating page tables. BL2 has flushed this information to memory, so 117 * we are guaranteed to pick up good data. 118 ******************************************************************************/ 119 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 120 uintptr_t hw_config, void *plat_params_from_bl2) 121 { 122 /* Initialize the console to provide early debug support */ 123 arm_console_boot_init(); 124 125 #if RESET_TO_BL31 126 /* There are no parameters from BL2 if BL31 is a reset vector */ 127 assert(from_bl2 == NULL); 128 assert(plat_params_from_bl2 == NULL); 129 130 # ifdef BL32_BASE 131 /* Populate entry point information for BL32 */ 132 SET_PARAM_HEAD(&bl32_image_ep_info, 133 PARAM_EP, 134 VERSION_1, 135 0); 136 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 137 bl32_image_ep_info.pc = BL32_BASE; 138 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 139 140 #if defined(SPD_spmd) 141 /* SPM (hafnium in secure world) expects SPM Core manifest base address 142 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 143 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 144 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 145 * keep it in the last page. 146 */ 147 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 148 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 149 #endif 150 151 # endif /* BL32_BASE */ 152 153 /* Populate entry point information for BL33 */ 154 SET_PARAM_HEAD(&bl33_image_ep_info, 155 PARAM_EP, 156 VERSION_1, 157 0); 158 /* 159 * Tell BL31 where the non-trusted software image 160 * is located and the entry state information 161 */ 162 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 163 164 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 165 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 166 167 #else /* RESET_TO_BL31 */ 168 169 /* 170 * In debug builds, we pass a special value in 'plat_params_from_bl2' 171 * to verify platform parameters from BL2 to BL31. 172 * In release builds, it's not used. 173 */ 174 assert(((unsigned long long)plat_params_from_bl2) == 175 ARM_BL31_PLAT_PARAM_VAL); 176 177 /* 178 * Check params passed from BL2 should not be NULL, 179 */ 180 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 181 assert(params_from_bl2 != NULL); 182 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 183 assert(params_from_bl2->h.version >= VERSION_2); 184 185 bl_params_node_t *bl_params = params_from_bl2->head; 186 187 /* 188 * Copy BL33, BL32 and RMM (if present), entry point information. 189 * They are stored in Secure RAM, in BL2's address space. 190 */ 191 while (bl_params != NULL) { 192 if (bl_params->image_id == BL32_IMAGE_ID) { 193 bl32_image_ep_info = *bl_params->ep_info; 194 } 195 #if ENABLE_RME 196 else if (bl_params->image_id == RMM_IMAGE_ID) { 197 rmm_image_ep_info = *bl_params->ep_info; 198 } 199 #endif 200 else if (bl_params->image_id == BL33_IMAGE_ID) { 201 bl33_image_ep_info = *bl_params->ep_info; 202 } 203 204 bl_params = bl_params->next_params_info; 205 } 206 207 if (bl33_image_ep_info.pc == 0U) 208 panic(); 209 #if ENABLE_RME 210 if (rmm_image_ep_info.pc == 0U) 211 panic(); 212 #endif 213 #endif /* RESET_TO_BL31 */ 214 215 # if ARM_LINUX_KERNEL_AS_BL33 216 /* 217 * According to the file ``Documentation/arm64/booting.txt`` of the 218 * Linux kernel tree, Linux expects the physical address of the device 219 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 220 * must be 0. 221 */ 222 #if RESET_TO_BL31 223 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 224 #else 225 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; 226 #endif 227 bl33_image_ep_info.args.arg1 = 0U; 228 bl33_image_ep_info.args.arg2 = 0U; 229 bl33_image_ep_info.args.arg3 = 0U; 230 # endif 231 232 #if defined(SPD_spmd) 233 /* 234 * Hafnium in normal world expects its manifest address in x0, In CI 235 * configuration manifest is preloaded at 0x80000000(start of DRAM). 236 */ 237 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 238 #endif 239 } 240 241 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 242 u_register_t arg2, u_register_t arg3) 243 { 244 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 245 246 /* 247 * Initialize Interconnect for this cluster during cold boot. 248 * No need for locks as no other CPU is active. 249 */ 250 plat_arm_interconnect_init(); 251 252 /* 253 * Enable Interconnect coherency for the primary CPU's cluster. 254 * Earlier bootloader stages might already do this (e.g. Trusted 255 * Firmware's BL1 does it) but we can't assume so. There is no harm in 256 * executing this code twice anyway. 257 * Platform specific PSCI code will enable coherency for other 258 * clusters. 259 */ 260 plat_arm_interconnect_enter_coherency(); 261 } 262 263 /******************************************************************************* 264 * Perform any BL31 platform setup common to ARM standard platforms 265 ******************************************************************************/ 266 void arm_bl31_platform_setup(void) 267 { 268 /* Initialize the GIC driver, cpu and distributor interfaces */ 269 plat_arm_gic_driver_init(); 270 plat_arm_gic_init(); 271 272 #if RESET_TO_BL31 273 /* 274 * Do initial security configuration to allow DRAM/device access 275 * (if earlier BL has not already done so). 276 */ 277 plat_arm_security_setup(); 278 279 #if defined(PLAT_ARM_MEM_PROT_ADDR) 280 arm_nor_psci_do_dyn_mem_protect(); 281 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 282 283 #endif /* RESET_TO_BL31 */ 284 285 /* Enable and initialize the System level generic timer */ 286 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 287 CNTCR_FCREQ(0U) | CNTCR_EN); 288 289 /* Allow access to the System counter timer module */ 290 arm_configure_sys_timer(); 291 292 /* Initialize power controller before setting up topology */ 293 plat_arm_pwrc_setup(); 294 295 #if RAS_EXTENSION 296 ras_init(); 297 #endif 298 299 #if USE_DEBUGFS 300 debugfs_init(); 301 #endif /* USE_DEBUGFS */ 302 } 303 304 /******************************************************************************* 305 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 306 * standard platforms 307 * Perform BL31 platform setup 308 ******************************************************************************/ 309 void arm_bl31_plat_runtime_setup(void) 310 { 311 console_switch_state(CONSOLE_FLAG_RUNTIME); 312 313 /* Initialize the runtime console */ 314 arm_console_runtime_init(); 315 316 #if RECLAIM_INIT_CODE 317 arm_free_init_memory(); 318 #endif 319 320 #if PLAT_RO_XLAT_TABLES 321 arm_xlat_make_tables_readonly(); 322 #endif 323 } 324 325 #if RECLAIM_INIT_CODE 326 /* 327 * Make memory for image boot time code RW to reclaim it as stack for the 328 * secondary cores, or RO where it cannot be reclaimed: 329 * 330 * |-------- INIT SECTION --------| 331 * ----------------------------------------- 332 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 333 * | STACK | STACK | STACK | SPACE | 334 * ----------------------------------------- 335 * <-------------------> <------> 336 * MAKE RW AND XN MAKE 337 * FOR STACKS RO AND XN 338 */ 339 void arm_free_init_memory(void) 340 { 341 int ret = 0; 342 343 if (BL_STACKS_END < BL_INIT_CODE_END) { 344 /* Reclaim some of the init section as stack if possible. */ 345 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 346 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 347 BL_STACKS_END - BL_INIT_CODE_BASE, 348 MT_RW_DATA); 349 } 350 /* Make the rest of the init section read-only. */ 351 ret |= xlat_change_mem_attributes(BL_STACKS_END, 352 BL_INIT_CODE_END - BL_STACKS_END, 353 MT_RO_DATA); 354 } else { 355 /* The stacks cover the init section, so reclaim it all. */ 356 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 357 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 358 MT_RW_DATA); 359 } 360 361 if (ret != 0) { 362 ERROR("Could not reclaim initialization code"); 363 panic(); 364 } 365 } 366 #endif 367 368 void __init bl31_platform_setup(void) 369 { 370 arm_bl31_platform_setup(); 371 } 372 373 void bl31_plat_runtime_setup(void) 374 { 375 arm_bl31_plat_runtime_setup(); 376 } 377 378 /******************************************************************************* 379 * Perform the very early platform specific architectural setup shared between 380 * ARM standard platforms. This only does basic initialization. Later 381 * architectural setup (bl31_arch_setup()) does not do anything platform 382 * specific. 383 ******************************************************************************/ 384 void __init arm_bl31_plat_arch_setup(void) 385 { 386 const mmap_region_t bl_regions[] = { 387 MAP_BL31_TOTAL, 388 #if ENABLE_RME 389 ARM_MAP_L0_GPT_REGION, 390 #endif 391 #if RECLAIM_INIT_CODE 392 MAP_BL_INIT_CODE, 393 #endif 394 #if SEPARATE_NOBITS_REGION 395 MAP_BL31_NOBITS, 396 #endif 397 ARM_MAP_BL_RO, 398 #if USE_ROMLIB 399 ARM_MAP_ROMLIB_CODE, 400 ARM_MAP_ROMLIB_DATA, 401 #endif 402 #if USE_COHERENT_MEM 403 ARM_MAP_BL_COHERENT_RAM, 404 #endif 405 {0} 406 }; 407 408 setup_page_tables(bl_regions, plat_arm_get_mmap()); 409 410 enable_mmu_el3(0); 411 412 #if ENABLE_RME 413 /* 414 * Initialise Granule Protection library and enable GPC for the primary 415 * processor. The tables have already been initialized by a previous BL 416 * stage, so there is no need to provide any PAS here. This function 417 * sets up pointers to those tables. 418 */ 419 if (gpt_runtime_init() < 0) { 420 ERROR("gpt_runtime_init() failed!\n"); 421 panic(); 422 } 423 #endif /* ENABLE_RME */ 424 425 arm_setup_romlib(); 426 } 427 428 void __init bl31_plat_arch_setup(void) 429 { 430 arm_bl31_plat_arch_setup(); 431 } 432