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Searched refs:_VPU_WriteWordMask (Results 1 – 25 of 62) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK ); in HAL_VPU_ClockSpeed()
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV ); in HAL_VPU_ClockInv()
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_CPUSetting()
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_CPUSetting()
513 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR ); in HAL_VPU_MBoxClear()
516 … _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR ); in HAL_VPU_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DhalVPU_EX.c897 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1158 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1159 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1162 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1163 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1184 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1188 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1193 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1197 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1202 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DhalVPU_EX.c895 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1157 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1158 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1161 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1162 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1183 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1187 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1192 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1196 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1201 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DhalVPU_EX.c893 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1154 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1155 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1158 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1159 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1180 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1184 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1189 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1193 …_VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_… in _VPU_EX_InitAddressLimiter()
1198 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DhalVPU_EX.c887 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1356 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1360 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1376 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1379 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1382 …_VPU_WriteWordMask((CLKGEN0_REG_BASE+(0x006a<<1)), 0x0, BMASK(2:1));//20160817 patch for mooney cl… in _VPU_EX_ClockSpeed()
2382 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2384 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2386 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2416 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DhalVPU_EX.c894 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1378 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1382 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1398 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1401 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
2436 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2438 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2440 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2470 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
2472 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_DeInit()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DhalVPU_EX.c905 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1396 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1400 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1416 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1419 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
2454 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2456 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2458 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2488 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
2490 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_DeInit()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DhalVPU_EX.c911 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1395 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1399 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1415 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1418 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
2602 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2604 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2606 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2636 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
2638 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_DeInit()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DhalVPU_EX.c1083 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1087 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1101 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1104 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_320MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1857 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1858 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2075 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2078 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DhalVPU_EX.c923 …_VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); /… in _VPU_EX_InitHW()
1414 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1418 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1434 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1437 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
2621 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2623 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2625 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2655 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
2657 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_DeInit()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DhalVPU_EX.c1109 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1113 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1126 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1129 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_240MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1855 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1860 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1888 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1889 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2167 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2170 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DhalVPU_EX.c1109 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1113 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1126 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1129 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_240MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1855 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1860 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1888 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT ); in HAL_VPU_EX_CPUSetting()
1889 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT ); in HAL_VPU_EX_CPUSetting()
2167 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR); in HAL_VPU_EX_MBoxClear()
2170 … _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR); in HAL_VPU_EX_MBoxClear()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DhalVPU_EX.c1430 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1434 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV); in _VPU_EX_ClockInv()
1445 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
1448 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_480MHZ, TOP_CKG_VPU_CLK_MASK); in _VPU_EX_ClockSpeed()
2666 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_Init()
2668 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_Init()
2670 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP); in HAL_VPU_EX_Init()
2675 …_VPU_WriteWordMask(REG_HICODEC_LITE_SRAM_SD_EN, HICODEC_LITE_SRAM_HICODEC1, HICODEC_LITE_SRAM_HICO… in HAL_VPU_EX_Init()
2724 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2); in HAL_VPU_EX_DeInit()
2726 … _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP); in HAL_VPU_EX_DeInit()
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