1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216 typedef struct
217 {
218 MS_BOOL bSTCSetMode;
219 MS_U32 u32STCIndex;
220 } VPU_EX_STC;
221
222 #define VPU_MSG_ERR(format, args...) \
223 do \
224 { \
225 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
226 { \
227 printf("[VPU][ERR]%s:", __FUNCTION__); \
228 printf(format, ##args); \
229 } \
230 } while (0)
231
232 #define VPU_MSG_DBG(format, args...) \
233 do \
234 { \
235 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
236 { \
237 printf("[VPU][DBG]%s:", __FUNCTION__); \
238 printf(format, ##args); \
239 } \
240 } while (0)
241
242 #define VPU_MSG_INFO(format, args...) \
243 do \
244 { \
245 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
246 { \
247 printf("[VPU][INF]%s:", __FUNCTION__); \
248 printf(format, ##args); \
249 } \
250 } while (0)
251
252 //------------------------------ MIU SETTINGS ----------------------------------
253 #ifdef EVDR2
254 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
255 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
256 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2)) // G32
257
258 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
259 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
260 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2)) // G32
261
262 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
263 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
264 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
265
266 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
267 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
268 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
269 #endif
270
271
272
273 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
274 do \
275 { \
276 if (miu_clients##_ON_MIU0 == 1) \
277 { \
278 _MaskMiuReq_##miu_clients(mask); \
279 } \
280 else \
281 { \
282 if (miu_clients##_ON_MIU1 == 1) \
283 { \
284 _MaskMiu1Req_##miu_clients(mask); \
285 } \
286 } \
287 } while(0)
288
289
290
291
292 #if ENABLE_VPU_MUTEX_PROTECTION
293 MS_S32 s32VPUMutexID = -1;
294 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
295
296 #define _HAL_VPU_MutexCreate() \
297 if (s32VPUMutexID < 0) \
298 { \
299 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
300 }
301
302 #define _HAL_VPU_MutexDelete() \
303 if (s32VPUMutexID >= 0) \
304 { \
305 MsOS_DeleteMutex(s32VPUMutexID); \
306 s32VPUMutexID = -1; \
307 }
308
309 #define _HAL_VPU_Entry() \
310 if (s32VPUMutexID >= 0) \
311 { \
312 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
313 { \
314 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
315 } \
316 }
317
318 #define _HAL_VPU_Return(_ret) \
319 { \
320 if (s32VPUMutexID >= 0) \
321 { \
322 MsOS_ReleaseMutex(s32VPUMutexID); \
323 } \
324 return _ret; \
325 }
326
327 #define _HAL_VPU_Release() \
328 { \
329 if (s32VPUMutexID >= 0) \
330 { \
331 MsOS_ReleaseMutex(s32VPUMutexID); \
332 } \
333 }
334 #else
335 #define _HAL_VPU_MutexCreate()
336 #define _HAL_VPU_MutexDelete()
337 #define _HAL_VPU_Entry()
338 #define _HAL_VPU_Return(_ret) {return _ret;}
339 #define _HAL_VPU_Release()
340 #endif
341
342 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
343 #define VPU_CMD_TIMEOUT 1000 // 1 sec
344
345
346 #if( !defined(MSOS_TYPE_LINUX_KERNEL) && !defined(ANDROID))
347 #define VPU_FIELD_DETECTOR TRUE
348 #else
349 #define VPU_FIELD_DETECTOR FALSE
350 #endif
351
352 //-------------------------------------------------------------------------------------------------
353 // Local Structures
354 //-------------------------------------------------------------------------------------------------
355 typedef struct _VPU_HWInitFunc
356 {
357 MS_BOOL (*pfMVDHW_Init)(void);
358 MS_BOOL (*pfMVDHW_Deinit)(void);
359 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
360 MS_BOOL (*pfHVDHW_Deinit)(void);
361 } VPU_HWInitFunc;
362
363 typedef struct
364 {
365 MS_U32 u32ApiHW_Version; //<Version of current structure>
366 MS_U16 u16ApiHW_Length; //<Length of this structure>
367
368 MS_U8 u8Cap_Support_Decoder_Num;
369
370 MS_BOOL bCap_Support_MPEG2;
371 MS_BOOL bCap_Support_H263;
372 MS_BOOL bCap_Support_MPEG4;
373 MS_BOOL bCap_Support_DIVX311;
374 MS_BOOL bCap_Support_DIVX412;
375 MS_BOOL bCap_Support_FLV;
376 MS_BOOL bCap_Support_VC1ADV;
377 MS_BOOL bCap_Support_VC1MAIN;
378
379 MS_BOOL bCap_Support_RV8;
380 MS_BOOL bCap_Support_RV9;
381 MS_BOOL bCap_Support_H264;
382 MS_BOOL bCap_Support_AVS;
383 MS_BOOL bCap_Support_AVS_PLUS;
384 MS_BOOL bCap_Support_MJPEG;
385 MS_BOOL bCap_Support_MVC;
386 MS_BOOL bCap_Support_VP8;
387 MS_BOOL bCap_Support_VP9;
388 MS_BOOL bCap_Support_HEVC;
389
390 /*New HW Cap and Feature add in struct at the end*/
391 }VDEC_HwCap;
392
393 //-------------------------------------------------------------------------------------------------
394 // Local Functions Prototype
395 //-------------------------------------------------------------------------------------------------
396 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
397 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
398 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
399
400 //-------------------------------------------------------------------------------------------------
401 // Global Variables
402 //-------------------------------------------------------------------------------------------------
403 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
404 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
405 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
406 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
407 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
408 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
409 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
410 #if SUPPORT_G2VP9 && defined(VDEC3)
411 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
412 #endif
413 #if defined (__aeon__)
414 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
415 #else
416 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
417 #endif
418
419 //-------------------------------------------------------------------------------------------------
420 // Local Variables
421 //-------------------------------------------------------------------------------------------------
422 #if 0
423
424 static MS_BOOL _bVPUPowered = FALSE;
425 static MS_BOOL _bVPURsted = FALSE;
426 static MS_BOOL _bVPUSingleMode = FALSE;
427 static VPU_EX_DecModCfg _stVPUDecMode;
428
429 static MS_U8 u8TaskCnt = 0;
430
431 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
432
433 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
434 static VPU_EX_Stream _stVPUStream[] =
435 {
436 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
437 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
438 };
439 static VPU_HWInitFunc stHWInitFunc =
440 {
441 &HAL_MVD_InitHW,
442 &HAL_MVD_DeinitHW,
443 &HAL_HVD_EX_InitHW,
444 &HAL_HVD_EX_DeinitHW,
445 };
446
447 #endif
448
449 #if VPU_ENABLE_EMBEDDED_FW_BINARY
450 static const MS_U8 u8HVD_FW_Binary[] = {
451 #include "fwVPU.dat"
452 };
453
454 #if HVD_ENABLE_RV_FEATURE
455 static const MS_U8 u8HVD_VLC_Binary[] = {
456 #include "fwVPU_VLC.dat"
457 };
458 #endif
459 #endif
460
461
462 #ifdef VDEC3
463 typedef struct
464 {
465 MS_BOOL bTSP;
466 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
467 MS_U32 u32Used;
468 } BBU_STATE;
469
470 typedef struct
471 {
472 MS_BOOL bTSP;
473 MS_BOOL bUsedbyMVD;
474 MS_U32 u32Used;
475 } SLQ_STATE;
476 #endif
477
478 typedef struct
479 {
480 MS_BOOL _bVPUPowered;
481 MS_BOOL _bVPURsted;
482 MS_BOOL _bVPUSingleMode;
483 VPU_EX_DecModCfg _stVPUDecMode;
484 MS_U8 u8TaskCnt;
485 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
486 #ifdef VDEC3
487 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
488 #else
489 VPU_EX_Stream _stVPUStream[2];
490 #endif
491
492 VPU_HWInitFunc stHWInitFunc;
493
494 MS_BOOL bVpuExReloadFW;
495 MS_BOOL bVpuExLoadFWRlt;
496 MS_VIRT u32VPUSHMAddr; //PA
497 MS_BOOL bEnableVPUSecureMode;
498
499 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
500 MS_BOOL bEnableDymanicFBMode;
501 MS_PHY u32DynamicFBAddress;
502 MS_U32 u32DynamicFBSize;
503 #ifdef VDEC3
504 MS_VIRT u32FWCodeAddr;
505 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
506
507 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
508 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
509 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
510
511 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
512 #endif
513 MS_U8 u8ForceRst;
514 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
515
516 MS_S32 s32VpuFdTaskId[MAX_SUPPORT_DECODER_NUM];
517 MS_BOOL bFDInit[MAX_SUPPORT_DECODER_NUM];
518
519 } VPU_Hal_CTX;
520
521 //global variables
522 VPU_Hal_CTX* pVPUHalContext = NULL;
523 VPU_Hal_CTX gVPUHalContext;
524 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
525 MS_BOOL bVPUMbxInitFlag = 0;
526 MS_U8 u8VPUMbxMsgClass = 0;
527 MBX_Msg VPUReeToTeeMbxMsg;
528 MBX_Msg VPUTeeToReeMbxMsg;
529
530 //-------------------------------------------------------------------------------------------------
531 // Debug Functions
532 //-------------------------------------------------------------------------------------------------
533
534
535 //-------------------------------------------------------------------------------------------------
536 // Local Functions
537 //-------------------------------------------------------------------------------------------------
538
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)539 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
540 {
541 #if HVD_ENABLE_RV_FEATURE
542 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
543 {
544 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
545 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
546 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
547
548 if (pVlcCfg->u32BinSize)
549 {
550 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
551
552 MS_U32 u32Start;
553 MS_U32 u32StartOffset;
554 MS_U8 u8MiuSel;
555
556 // Get MIU selection and offset from physical address = 0x30000000
557 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
558
559
560 if(u8MiuSel == E_CHIP_MIU_0)
561 cpyflag = E_SPIDMA_DEV_MIU0;
562 else if(u8MiuSel == E_CHIP_MIU_1)
563 cpyflag = E_SPIDMA_DEV_MIU1;
564 else if(u8MiuSel == E_CHIP_MIU_2)
565 cpyflag = E_SPIDMA_DEV_MIU2;
566
567 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
568 {
569 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
570 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
571
572 return FALSE;
573 }
574 }
575 else
576 {
577 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
578 return FALSE;
579 }
580 #else
581 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
582 return FALSE;
583 #endif
584 }
585 else
586 {
587 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
588 {
589 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
590 {
591 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
592 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
593
594 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
595 BDMA_Result bdmaRlt;
596 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
597
598 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
599 u32SrcAdd = pVlcCfg->u32BinAddr;
600 u32tabsize = pVlcCfg->u32BinSize;
601 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
602 MsOS_FlushMemory();
603 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
604
605 if (E_BDMA_OK != bdmaRlt)
606 {
607 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
608 }
609 #else
610 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
611 #endif
612 }
613 else
614 {
615 VPU_MSG_ERR
616 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
617 return FALSE;
618 }
619 }
620 else
621 {
622 #if VPU_ENABLE_EMBEDDED_FW_BINARY
623 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
624 MS_U8 *pu8HVD_VLC_Binary;
625
626 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
627
628 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
629 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
630 (MS_U32) sizeof(u8HVD_VLC_Binary));
631
632 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
633 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
634 #else
635 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
636 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
637 (MS_U32) sizeof(u8HVD_VLC_Binary));
638
639 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
640 #endif
641 #else
642 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
643 return FALSE;
644 #endif
645 }
646 }
647 #endif
648
649 return TRUE;
650 }
651
652 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)653 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
654 {
655 MS_U8 u8OffsetIdx = 0;
656 MS_U8 u8VSidBaseMask = 0xF0;
657 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
658
659 switch (eVSidBase)
660 {
661 case E_HAL_VPU_MAIN_STREAM_BASE:
662 {
663 u8OffsetIdx = 0;
664 break;
665 }
666 case E_HAL_VPU_SUB_STREAM_BASE:
667 {
668 u8OffsetIdx = 1;
669 break;
670 }
671 case E_HAL_VPU_MVC_STREAM_BASE:
672 {
673 u8OffsetIdx = 0;
674 break;
675 }
676 #ifdef VDEC3
677 case E_HAL_VPU_N_STREAM_BASE:
678 {
679 u8OffsetIdx = u32Id & 0x0F;
680 break;
681 }
682 #endif
683 default:
684 {
685 u8OffsetIdx = 0;
686 break;
687 }
688 }
689
690 /*
691 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
692 u32Id, eVSidBase, u8OffsetIdx);
693 */
694 return u8OffsetIdx;
695 }
696
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)697 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
698 {
699 return _VPU_EX_GetOffsetIdx(u32Id);
700 }
701
_VPU_EX_Context_Init(void)702 static void _VPU_EX_Context_Init(void)
703 {
704 #ifdef VDEC3
705 MS_U8 i;
706
707 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
708 {
709 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
710 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
711 }
712
713 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
714 {
715 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
716 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
717 }
718
719 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
720 {
721 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
722 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
723 }
724
725 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
726 {
727 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
728 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
729 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
730 }
731 #else
732 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
733 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
734 #endif
735 pVPUHalContext->bVpuExReloadFW = TRUE;
736 pVPUHalContext->u8ForceRst = 0;
737
738 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
739 {
740 pVPUHalContext->s32VpuFdTaskId[i] = -1;
741 pVPUHalContext->bFDInit[i] = FALSE;
742 }
743
744 }
745
HAL_VPU_EX_ForceSwRst(void)746 void HAL_VPU_EX_ForceSwRst(void)
747 {
748 pVPUHalContext->u8ForceRst = 1;
749 }
750
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)751 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
752 {
753 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
754 MS_U8 u8OffsetIdx = 0;
755
756 if (NULL == pTaskInfo)
757 {
758 return eCmd;
759 }
760
761 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
762
763 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
764 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
765
766 #ifdef VDEC3
767 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
768 {
769 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
770 {
771 eCmd = E_NST_CMD_TASK_MVD_TSP;
772 }
773 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
774 {
775 eCmd = E_NST_CMD_TASK_MVD_SLQ;
776 }
777 }
778 #else
779 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
780 {
781 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
782 {
783 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
784 }
785 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
786 {
787 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
788 }
789 }
790 #endif
791 #ifdef VDEC3
792 #if SUPPORT_G2VP9
793 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
794 #else
795 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
796 #endif
797 {
798 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
799 {
800 eCmd = E_NST_CMD_TASK_HVD_TSP;
801 }
802 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
803 {
804 eCmd = E_NST_CMD_TASK_HVD_BBU;
805 }
806 }
807 #else
808 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
809 {
810 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
811 {
812 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
813 }
814 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
815 {
816 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
817 }
818 }
819 #endif
820
821 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
822 return eCmd;
823 }
824
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)825 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
826 {
827 if (!pTaskInfo)
828 {
829 VPU_MSG_ERR("null input\n");
830 return FALSE;
831 }
832
833 //Check if we need to init MVD HW
834 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
835 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
836 {
837 //Init HW
838 if (FALSE == HAL_VPU_EX_MVDInUsed())
839 {
840 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
841 {
842 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
843 return FALSE;
844 }
845 }
846 else
847 {
848 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
849 }
850 }
851
852 //MVD use sub mvop
853 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
854 #ifdef VDEC3
855 (pTaskInfo->u8HalId == 1) )
856 #else
857 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
858 #endif
859 {
860 VPU_MSG_ERR("Force turn on HVD\n");
861 if(!HAL_VPU_EX_HVDInUsed())
862 {
863 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
864 {
865 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
866 {
867 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
868 return FALSE;
869 }
870 }
871 else
872 {
873 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
874 #ifdef CONFIG_MSTAR_CLKM
875 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
876 #else
877 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
878 #endif
879 }
880 }
881 else
882 {
883 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
884 }
885 }
886
887 //Check if we need to init HVD HW
888 #ifdef VDEC3
889 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
890 #else
891 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
892 #endif
893 {
894 if (!HAL_VPU_EX_MVDInUsed())
895 {
896 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
897 {
898 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
899 return FALSE;
900 }
901 }
902
903 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
904 {
905 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
906 return FALSE;
907 }
908 #if SUPPORT_MSVP9
909 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
910 {
911 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
912 }
913 #endif
914 }
915
916 #if SUPPORT_G2VP9 && defined(VDEC3)
917 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
918 {
919 if (!HAL_VPU_EX_MVDInUsed())
920 {
921 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
922 {
923 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
924 return FALSE;
925 }
926 }
927 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
928 {
929 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
930 return FALSE;
931 }
932 }
933 #endif
934
935 return TRUE;
936 }
937
_VPU_EX_InClock(MS_U32 u32type)938 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
939 {
940 switch (u32type)
941 {
942 case VPU_CLOCK_240MHZ:
943 return 240000000UL;
944 case VPU_CLOCK_216MHZ:
945 return 216000000UL;
946 case VPU_CLOCK_192MHZ:
947 return 192000000UL;
948 case VPU_CLOCK_12MHZ:
949 return 12000000UL;
950 case VPU_CLOCK_320MHZ:
951 return 320000000UL;
952 case VPU_CLOCK_288MHZ:
953 return 288000000UL;
954 case VPU_CLOCK_432MHZ:
955 return 432000000UL;
956 default:
957 return 384000000UL;
958 }
959 }
960
961
962 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
963 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)964 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
965 {
966 //#ifndef MSOS_TYPE_LINUX_KERNEL
967 #if 1
968 MS_U8 ClassNum = 0;
969 MBX_Result result;
970
971 #if 0
972 if (bVPUMbxInitFlag == TRUE)
973 {
974 return TRUE;
975 }
976 #endif
977
978 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
979 {
980 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
981 return FALSE;
982 }
983 else
984 {
985 MApi_MBX_Enable(TRUE);
986 }
987
988 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
989
990 if (E_MBX_SUCCESS != result)
991 {
992 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
993 return FALSE;
994 }
995
996 result = MApi_MBX_RegisterMSG(ClassNum, 10);
997
998 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
999 {
1000 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
1001 return FALSE;
1002 }
1003 else
1004 {
1005 bVPUMbxInitFlag = TRUE;
1006 u8VPUMbxMsgClass = ClassNum;
1007 return TRUE;
1008 }
1009 #else
1010 return FALSE;
1011 #endif
1012 }
1013
1014 //#ifdef MBX_2K
1015 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)1016 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
1017 {
1018 MBX_Result result;
1019 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
1020
1021 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1022 {
1023 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1024 }
1025
1026 if (bVPUMbxInitFlag == FALSE)
1027 {
1028 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1029 }
1030
1031 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1032 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1033 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1034 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1035 VPUReeToTeeMbxMsg.u8Index = msg_type;
1036
1037 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1038 if (E_MBX_SUCCESS != result)
1039 {
1040 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1041 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1042 }
1043
1044 // Receive Reply ACK from TEE side.
1045 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1046
1047 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1048
1049 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1050 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1051 {
1052 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1053 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1054 }
1055 else
1056 #else
1057 do
1058 {
1059 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1060 } while(E_MBX_SUCCESS != result);
1061 #endif
1062 {
1063 u8Index = VPUTeeToReeMbxMsg.u8Index;
1064 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1065
1066 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1067 {
1068 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1069 }
1070 }
1071
1072 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1073 }
1074 #endif
1075
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1076 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1077 {
1078 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1079 {
1080 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1081 {
1082 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1083 return FALSE;
1084 }
1085 else
1086 {
1087 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1088 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1089 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1090 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1091 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1092 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1093 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1094 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1095
1096 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1097
1098
1099 MS_U32 u32Start;
1100
1101 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1102 {
1103 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1104 pVPUHalContext->u32VPUSHMAddr = u32Start;
1105 }
1106 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1107 {
1108 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1109 pVPUHalContext->u32VPUSHMAddr = u32Start;
1110
1111 }
1112 else // == 0
1113 {
1114 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1115 }
1116 }
1117 }
1118 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1119 {
1120 MS_U32 u32Offset;
1121 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1122 {
1123 u32Offset = u32SHMAddr-u32MIU1Addr;
1124 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1125 }
1126 else
1127 {
1128 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1129 }
1130 }
1131 return TRUE;
1132 }
1133
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1134 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1135 {
1136 bVPUMbxInitFlag = TRUE;
1137 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1138 return TRUE;
1139 }
1140
1141 #endif
1142
HAL_VPU_EX_GetFWReload(void)1143 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1144 {
1145 return pVPUHalContext->bVpuExReloadFW;
1146 }
1147
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1148 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1149 {
1150 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1151 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1152 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1153 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1154 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1155 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1156 )
1157 {
1158 return FALSE;
1159 }
1160 else
1161 {
1162 return TRUE;
1163 }
1164 }
1165
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1166 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1167 {
1168 MS_PHY u32fwPA = NULL; //physical address
1169 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1170
1171 if (TRUE == HAL_VPU_EX_IsPowered())
1172 {
1173 VPU_MSG_DBG("IsPowered\n");
1174 return TRUE;
1175 }
1176 else
1177 {
1178 //VPU hold
1179 HAL_VPU_EX_SwRst(FALSE);
1180
1181 //VPU clock on
1182 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1183
1184 if (VPU_I_R_ON_MIU0)
1185 VPUInitParams.u8MiuSel = 0;
1186 else if (VPU_I_R_ON_MIU1)
1187 VPUInitParams.u8MiuSel = 1;
1188
1189 HAL_VPU_EX_Init(&VPUInitParams);
1190 }
1191
1192 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1193 VPU_EX_TaskInfo *pTaskInfo = NULL;
1194 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1195
1196 if (pInitPara)
1197 {
1198 pFWCodeCfg = pInitPara->pFWCodeCfg;
1199 pTaskInfo = pInitPara->pTaskInfo;
1200 pVlcCfg = pInitPara->pVLCCfg;
1201 }
1202 else
1203 {
1204 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1205 return FALSE;
1206 }
1207
1208 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1209 //#ifdef MBX_2K
1210 #if 1
1211 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1212 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1213 {
1214 SYS_TEEINFO teemode;
1215 MDrv_SYS_ReadKernelCmdLine();
1216 MDrv_SYS_GetTEEInfo(&teemode);
1217 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1218 {
1219 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1220
1221 if (FALSE == HAL_VPU_EX_GetFWReload())
1222 {
1223 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1224 {
1225 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1226 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1227 {
1228 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1229 return FALSE;
1230 }
1231 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1232 }
1233 else
1234 {
1235 //Check f/w prefix "VDEC30"
1236 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1237 {
1238 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1239 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1240 {
1241 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1242 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1243 return FALSE;
1244 }
1245 }
1246 else
1247 {
1248 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1249 }
1250 }
1251 }
1252 else
1253 {
1254 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1255 {
1256 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1257 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1258 return FALSE;
1259 }
1260 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1261 }
1262 }
1263 }
1264 else
1265 #endif
1266 #endif
1267 {
1268 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1269
1270 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1271 {
1272 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1273 return FALSE;
1274 }
1275 }
1276
1277 if (pVlcCfg)
1278 {
1279 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1280 {
1281 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1282 return FALSE;
1283 }
1284 }
1285
1286 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1287 {
1288 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1289 return FALSE;
1290 }
1291
1292 //Init HW
1293 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1294 {
1295 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1296 //_MVD_INIT_FAIL_RET();
1297 return FALSE;
1298 }
1299 else
1300 {
1301 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1302 }
1303
1304 //set vpu clock to FW
1305 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1306 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1307
1308 ctl_ptr->statue = CTL_STU_NONE;
1309 //notify controller the interface version of VPU driver.
1310 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1311 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1312 MsOS_FlushMemory();
1313 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1314
1315 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1316 if (TRUE == HAL_VPU_EX_IsRsted())
1317 {
1318 VPU_MSG_DBG("VPU_IsRsted\n");
1319 return TRUE;
1320 }
1321 else
1322 {
1323 HAL_VPU_EX_SwRstRelse();
1324 }
1325
1326 return TRUE;
1327 }
1328
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1329 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1330 {
1331 MS_BOOL bRet = FALSE;
1332 #if defined(VDEC3)
1333 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1334 #else
1335 MS_BOOL isEVD = FALSE ;
1336 #endif
1337 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1338 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1339 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1340
1341 if (TRUE == isHVD)
1342 {
1343 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1344 }
1345
1346 #if defined(VDEC3)
1347 if (TRUE == isEVD)
1348 {
1349 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1350 }
1351 #endif
1352
1353 #if SUPPORT_G2VP9 && defined(VDEC3)
1354 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1355 {
1356 bRet = HAL_VP9_EX_DeinitHW();
1357 }
1358 #endif
1359 return bRet;
1360 }
1361
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1362 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1363 {
1364 HAL_VPU_EX_SwRst(TRUE);
1365 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1366 HAL_VPU_EX_DeInit();
1367
1368 return TRUE;
1369 }
1370
_VPU_EX_GetActiveCodecCnt(void)1371 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1372 {
1373 MS_U32 i;
1374 MS_U8 u8ActiveCnt = 0;
1375 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1376 {
1377 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1378 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1379 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1380 {
1381 u8ActiveCnt++;
1382 }
1383 }
1384 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1385 {
1386 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1387 }
1388 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1389 return u8ActiveCnt;
1390 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1391 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1392 {
1393 if (TRUE)
1394 {
1395 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1396 }
1397 else
1398 {
1399 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1400 }
1401 }
1402
_VPU_EX_ClockSpeed(MS_U32 u32type)1403 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1404 {
1405 switch (u32type)
1406 {
1407 case VPU_CLOCK_240MHZ:
1408 case VPU_CLOCK_216MHZ:
1409 case VPU_CLOCK_192MHZ:
1410 case VPU_CLOCK_12MHZ:
1411 case VPU_CLOCK_320MHZ:
1412 case VPU_CLOCK_288MHZ:
1413 case VPU_CLOCK_384MHZ:
1414 case VPU_CLOCK_432MHZ:
1415 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1416 break;
1417 default:
1418 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1419 break;
1420 }
1421 }
1422 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1423 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1424 {
1425 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1426 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1427 {
1428 return TRUE;
1429 }
1430 return FALSE;
1431 }
1432 #endif
1433
1434
1435 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1436 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1437 {
1438 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1439 {
1440 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1441 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1442 ms_VDECDecompressDeInit();
1443 return TRUE;
1444 }
1445 else
1446 {
1447 return FALSE;
1448 }
1449 }
1450 #endif
1451
1452 #if VPU_FIELD_DETECTOR
1453
1454 #include "FieldDetection.h"
1455
_HAL_VPU_EX_Field_Detecor_Task_HVD(MS_U32 u32Id)1456 static MS_BOOL _HAL_VPU_EX_Field_Detecor_Task_HVD(MS_U32 u32Id)
1457 {
1458 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1459 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1460 //VPU_FD_DispFrameInfo DispFrmInfo;
1461 MsOS_ReadMemory();
1462 //memset(&DispFrmInfo,0,sizeof(VPU_FD_DispFrameInfo));
1463
1464 if(pShm->u32CodecType == E_HVD_Codec_AVS)
1465 {
1466 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_FIELD_DETECT;
1467 }
1468
1469 while (1)
1470 {
1471 MsOS_DelayTask(1);
1472 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueWPtr];
1473 MS_U32 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
1474
1475 FrameInfo stFrameInfo;
1476 stFrameInfo.bFieldOrderSet = (pFrmInfo->u8ModeFlag & E_HVD_PP_FD_TOP_FIELD_FIRST)? 1:0;
1477 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32LumaAddr, stFrameInfo.phyBuffAddr);
1478 stFrameInfo.u16Height = pFrmInfo->u16Height;
1479 stFrameInfo.u16Width= pFrmInfo->u16Width;
1480 stFrameInfo.u32BuffSize = (pFrmInfo->u16Height)*(pFrmInfo->u16Width);
1481
1482 if(pShm->u32CodecType == E_HVD_Codec_AVS
1483 && pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_FIELD_DETECT_ONGOING)
1484 {
1485 if(pVPUHalContext->bFDInit[u8Offset]==FALSE)
1486 {
1487 FODInfo stFod;
1488 stFod.height =pFrmInfo->u16Height;
1489 stFod.width=pFrmInfo->u16Width;
1490 stFod.pitch=pFrmInfo->u16Pitch;
1491 stFod.tile_width = 16;
1492 stFod.tile_height= 32;
1493 VPU_MSG_INFO("Init Field Detector!!\n");
1494 InitFieldDetection(&stFod);
1495
1496 InitMemoryFromVPU(stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*20,
1497 stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*21,
1498 stFrameInfo.phyBuffAddr+stFrameInfo.u32BuffSize*22);
1499 pVPUHalContext->bFDInit[u8Offset] = TRUE;
1500 }
1501
1502 VPU_MSG_INFO("[%dx%d], [0x%x, 0x%x], %d ", stFrameInfo.u16Width, stFrameInfo.u16Height,
1503 (MS_U32)stFrameInfo.phyBuffAddr, (MS_U32)stFrameInfo.u32BuffSize, stFrameInfo.bFieldOrderSet);
1504
1505 MS_U32 u32Timer= MsOS_GetSystemTime();
1506 eIsFieldOrderInverse eResult = IsFieldOrderInverse(&stFrameInfo);
1507 VPU_MSG_INFO("[%dms] ", MsOS_GetSystemTime()-u32Timer);
1508 if(eResult == E_VDEC_IFOI_TRUE)
1509 {
1510 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_FIELD_DETECT_NEED_REVERSE;
1511 VPU_MSG_INFO("reverse=1\n");
1512 }
1513 else if(eResult == E_VDEC_IFOI_FALSE)
1514 {
1515 pShm->u8FrmPostProcSupport &= ~E_HVD_POST_PROC_FIELD_DETECT_NEED_REVERSE;
1516 VPU_MSG_INFO("reverse=0\n");
1517 }
1518
1519 pShm->u8FrmPostProcSupport &= ~E_HVD_POST_PROC_FIELD_DETECT_ONGOING;
1520
1521 MsOS_FlushMemory();
1522 }
1523 MsOS_ReadMemory();
1524
1525 }
1526
1527 return TRUE;
1528 }
1529
_HAL_VPU_EX_Field_Detecor_Task_MVD(MS_U32 u32Id)1530 static MS_BOOL _HAL_VPU_EX_Field_Detecor_Task_MVD(MS_U32 u32Id)
1531 {
1532 u32Id = u32Id;
1533 while(1)
1534 {
1535 MsOS_DelayTask(1);
1536 // TODO: handle MVD case here
1537 }
1538 return TRUE;
1539 }
1540
_HAL_VPU_EX_FdTask_Delete(MS_U32 u32Id,VPU_Hal_CTX * pVPUHalContext)1541 static void _HAL_VPU_EX_FdTask_Delete(MS_U32 u32Id, VPU_Hal_CTX* pVPUHalContext)
1542 {
1543 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1544 FInitFieldDetection();
1545 pVPUHalContext->bFDInit[u8Offset] = FALSE;
1546 MsOS_DeleteTask(pVPUHalContext->s32VpuFdTaskId[u8Offset]);
1547 pVPUHalContext->s32VpuFdTaskId[u8Offset] = -1;
1548 }
1549
1550
1551 #endif
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1552 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1553 {
1554 MS_BOOL bRet = TRUE;
1555 pVPUHalContext->_bVPUSingleMode = bEnable;
1556 return bRet;
1557 }
1558
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1559 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1560 {
1561 MS_BOOL bRet = TRUE;
1562 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1563 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1564 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1565
1566 return bRet;
1567 }
1568
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1569 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1570 {
1571 MS_BOOL bRet = TRUE;
1572 MS_U8 i=0;
1573 if (pstCfg != NULL)
1574 {
1575 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1576 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1577 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1578 {
1579 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1580 }
1581 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1582 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1583 }
1584 else
1585 {
1586 bRet = FALSE;
1587 }
1588 return bRet;
1589 }
1590
1591 //static MS_BOOL bVpuExReloadFW = TRUE;
1592 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1593 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1594 {
1595 pVPUHalContext->bVpuExReloadFW = bReload;
1596 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1597 return TRUE;
1598 }
1599
1600
1601 //-------------------------------------------------------------------------------------------------
1602 // Global Functions
1603 //-------------------------------------------------------------------------------------------------
1604 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1605 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1606 {
1607 #if HVD_ENABLE_RV_FEATURE
1608 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1609 {
1610 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1611 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1612 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1613
1614 if (pVlcCfg->u32BinSize)
1615 {
1616 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1617
1618 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1619 {
1620 cpyflag = E_SPIDMA_DEV_MIU1;
1621 }
1622 else
1623 {
1624 cpyflag = E_SPIDMA_DEV_MIU0;
1625 }
1626
1627 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1628 {
1629 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1630 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1631
1632 return FALSE;
1633 }
1634 }
1635 else
1636 {
1637 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1638 return FALSE;
1639 }
1640 #else
1641 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1642 return FALSE;
1643 #endif
1644 }
1645 else
1646 {
1647 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1648 {
1649 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1650 {
1651 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1652 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1653
1654 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1655 BDMA_Result bdmaRlt;
1656
1657 MsOS_FlushMemory();
1658 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1659
1660 if (E_BDMA_OK != bdmaRlt)
1661 {
1662 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1663 }
1664 #else
1665 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1666 #endif
1667 }
1668 else
1669 {
1670 VPU_MSG_ERR
1671 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1672 return FALSE;
1673 }
1674 }
1675 else
1676 {
1677 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1678 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1679 MS_U8 *pu8HVD_VLC_Binary;
1680
1681 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1682
1683 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1684 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1685 (MS_U32) sizeof(u8HVD_VLC_Binary));
1686
1687 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1688 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1689 #else
1690 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1691 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1692 (MS_U32) sizeof(u8HVD_VLC_Binary));
1693
1694 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1695 #endif
1696 #else
1697 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1698 return FALSE;
1699 #endif
1700 }
1701 }
1702 #endif
1703
1704 return TRUE;
1705 }
1706 #endif
1707 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1708 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1709 #else
1710 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1711 #endif
1712 {
1713 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1714 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1715 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1716 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1717 MS_U32 u32Arg = 0xFFFFFFFF;
1718 MS_U32 u32Timeout = 0;
1719 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1720 MS_U32 u32CmdArg = 0;
1721 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1722 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1723
1724 _HAL_VPU_Entry();
1725 //Check FW buffer size
1726 if (1 == u8Offset)
1727 {
1728 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1729 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1730
1731 if (u32CurFWBuffSize < u32MinFWBuffSize)
1732 {
1733 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1734 _HAL_VPU_Release();
1735 return FALSE;
1736 }
1737 }
1738
1739 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1740 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1741 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1742 {
1743 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1744 }
1745 #ifdef VDEC3
1746 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1747 #endif
1748
1749 if (0 == pVPUHalContext->u8TaskCnt)
1750 {
1751 //No task is created, need to load f/w, etc.
1752 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1753
1754 if (!_VPU_EX_InitAll(pInitPara))
1755 {
1756 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1757 _HAL_VPU_Release();
1758 return FALSE;
1759 }
1760
1761 //Check if controller finish initialization: clear mailbox, etc.
1762 //Need to check it before sending any controller commands!
1763 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1764 while (CTL_STU_NONE == ctl_ptr->statue)
1765 {
1766 if (HVD_GetSysTime_ms() > u32Timeout)
1767 {
1768 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1769 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1770 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1771 MS_U32 t=0;
1772 for (t=0; t<30; t++)
1773 {
1774 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1775 }
1776 _HAL_VPU_Release();
1777 return FALSE;
1778 }
1779
1780 MsOS_ReadMemory();
1781 }
1782
1783 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1784 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1785
1786 }
1787 else
1788 {
1789 if (pVPUHalContext->_bVPUSingleMode)
1790 {
1791 //Show error message
1792 printf("This task will use dram instead of sram!!!\n");
1793 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1794 }
1795
1796 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1797 {
1798 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1799 _HAL_VPU_Release();
1800 return FALSE;
1801 }
1802 if (pInitPara->pVLCCfg)
1803 {
1804 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1805 {
1806 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1807 _HAL_VPU_Release();
1808 return FALSE;
1809 }
1810 }
1811 }
1812
1813
1814 #ifdef VDEC3
1815 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1816 {
1817 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1818
1819 memset(pTemp4,0,sizeof(VDEC_VBBU));
1820
1821 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1822
1823 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1824
1825 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1826
1827 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1828
1829 memset(pTemp2,0,sizeof(CMD_QUEUE));
1830
1831 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1832
1833 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1834
1835 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1836
1837 memset(pTemp3,0,0x2000);
1838
1839 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1840
1841 memset((void*)pVersion,0,0x8);
1842
1843 *pVersion = 1; //0:diu, 1:wb
1844 }
1845
1846 #endif
1847
1848 #if 1 // For TEE
1849 #ifdef VDEC3
1850 #if SUPPORT_G2VP9
1851 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1852 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1853 #else
1854 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1855 #endif
1856 #else
1857 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1858 #endif
1859 {
1860 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1861
1862 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1863 {
1864 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1865 }
1866 else
1867 {
1868 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1869 }
1870
1871 MsOS_FlushMemory();
1872 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1873
1874 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1875 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1876 }
1877 #endif
1878
1879 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1880 {
1881 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1882 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1883
1884 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1885
1886 MsOS_FlushMemory();
1887 }
1888
1889 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1890 {
1891 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1892 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1893 {
1894 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1895 }
1896 }
1897
1898 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1899 {
1900 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1901 //arg=1 to get better performance for single task
1902 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1903 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1904 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1905 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1906 {
1907 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1908 }
1909 }
1910 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1911 {
1912 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1913 {
1914 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1915 {
1916 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1917 u32CmdArg = CTL_MODE_3DTV;
1918 break;
1919 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1920 u32CmdArg = CTL_MODE_3DTV_PROG;
1921 break;
1922 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1923 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1924 break;
1925 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1926 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1927 break;
1928 default:
1929 u32CmdArg = CTL_MODE_3DTV;
1930 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1931 break;
1932 }
1933 }
1934 else
1935 {
1936 u32CmdArg = CTL_MODE_3DWMV;
1937 }
1938 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1939 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1940 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1941 {
1942 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1943 }
1944 }
1945 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1946 {
1947 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1948 {
1949 u32CmdArg = CTL_MODE_ONE_STC;
1950 }
1951 else
1952 {
1953 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1954 }
1955 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1956 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1957 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1958 {
1959 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1960 }
1961 }
1962
1963 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1964 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1965 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1966 #ifdef VDEC3
1967 {
1968 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1969 }
1970 #else
1971 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1972 #endif
1973
1974 #ifdef VDEC3
1975 #if SUPPORT_G2VP9
1976 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1977 #else
1978 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1979 #endif
1980 {
1981 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1982 }
1983 #else
1984 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1985 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1986 #endif
1987 else
1988 {
1989 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1990 _HAL_VPU_Release();
1991 return FALSE;
1992 }
1993 #else
1994 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1995 #endif
1996
1997 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1998 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1999
2000 MsOS_ReadMemory();
2001 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2002 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2003
2004 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2005 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2006 {
2007 if (HVD_GetSysTime_ms() > u32Timeout)
2008 {
2009 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2010 MS_U32 t=0;
2011 for (t=0; t<30; t++)
2012 {
2013 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
2014 }
2015 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2016 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2017 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2018 _HAL_VPU_Release();
2019 return FALSE;
2020 //#endif
2021 }
2022
2023 MsOS_ReadMemory();
2024 }
2025
2026 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2027 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2028
2029 #ifdef VDEC3
2030 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2031 #else
2032 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2033 #endif
2034 {
2035 HAL_HVD_EX_SetNalTblAddr(u32Id);
2036 }
2037
2038 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2039 {
2040 eDecType = E_VPU_EX_DECODER_MVD;
2041 }
2042 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2043 {
2044 eDecType = E_VPU_EX_DECODER_HVD;
2045 }
2046 #ifdef VDEC3
2047 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2048 {
2049 eDecType = E_VPU_EX_DECODER_EVD;
2050 }
2051 #if SUPPORT_G2VP9
2052 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2053 {
2054 eDecType = E_VPU_EX_DECODER_G2VP9;
2055 }
2056 #endif
2057 #endif
2058 else
2059 {
2060 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2061 _HAL_VPU_Release();
2062 return FALSE;
2063 }
2064
2065 #ifdef VDEC3
2066 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
2067 {
2068 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2069 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2070 }
2071 #endif
2072
2073 if (pTaskInfo->eDecType != eDecType)
2074 {
2075 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2076 pTaskInfo->eDecType, eDecType);
2077 }
2078 goto _SAVE_DEC_TYPE;
2079
2080 _SAVE_DEC_TYPE:
2081 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2082 {
2083 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
2084 }
2085 else
2086 {
2087 VPU_MSG_ERR("Cannot save eDecType!!\n");
2088 }
2089
2090 #if VPU_FIELD_DETECTOR
2091 if(pVPUHalContext->s32VpuFdTaskId[0] == -1 && pVPUHalContext->s32VpuFdTaskId[1] == -1
2092 && pVPUHalContext->s32VpuFdTaskId[2] == -1 && pVPUHalContext->s32VpuFdTaskId[3] == -1
2093 && pVPUHalContext->s32VpuFdTaskId[4] == -1 && pVPUHalContext->s32VpuFdTaskId[5] == -1
2094 && pVPUHalContext->s32VpuFdTaskId[6] == -1 && pVPUHalContext->s32VpuFdTaskId[7] == -1
2095 && pVPUHalContext->s32VpuFdTaskId[8] == -1 && pVPUHalContext->s32VpuFdTaskId[9] == -1
2096 && pVPUHalContext->s32VpuFdTaskId[10] == -1 && pVPUHalContext->s32VpuFdTaskId[11] == -1
2097 && pVPUHalContext->s32VpuFdTaskId[12] == -1 && pVPUHalContext->s32VpuFdTaskId[13] == -1
2098 && pVPUHalContext->s32VpuFdTaskId[14] == -1 && pVPUHalContext->s32VpuFdTaskId[15] == -1
2099 )
2100 {
2101 MS_S32 s32VPUFDTaskId = -1;
2102 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2103 {
2104 s32VPUFDTaskId = MsOS_CreateTask((TaskEntry)_HAL_VPU_EX_Field_Detecor_Task_MVD,
2105 u32Id,
2106 E_TASK_PRI_MEDIUM,
2107 TRUE,
2108 NULL,
2109 32, // stack size..
2110 "VPU_FieldDetector_MVD_task");
2111 }
2112 else if(E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType ||E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2113 {
2114 VPU_MSG_INFO(" Create _HAL_VPU_EX_Field_Detecor_Task_HVD()\n");
2115 s32VPUFDTaskId = MsOS_CreateTask((TaskEntry)_HAL_VPU_EX_Field_Detecor_Task_HVD,
2116 u32Id,
2117 E_TASK_PRI_MEDIUM,
2118 TRUE,
2119 NULL,
2120 32, // stack size..
2121 "VPU_FieldDetector_HVD_task");
2122 }
2123 if (s32VPUFDTaskId < 0)
2124 {
2125 VPU_MSG_ERR("Field Detector Task create failed\n");
2126 }
2127 else
2128 {
2129 pVPUHalContext->s32VpuFdTaskId[u8Offset]= s32VPUFDTaskId;
2130 }
2131
2132 }
2133 #endif
2134
2135 (pVPUHalContext->u8TaskCnt)++;
2136 _HAL_VPU_Release();
2137 return TRUE;
2138 }
2139
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2140 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2141 {
2142 HVD_Return eRet;
2143 #ifdef VDEC3
2144 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2145 #else
2146 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2147 #endif
2148 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2149 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2150
2151 _HAL_VPU_Entry();
2152 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2153
2154 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2155 if(eRet != E_HVD_RETURN_SUCCESS)
2156 {
2157 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2158 }
2159
2160 {
2161 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2162 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2163 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2164
2165 MsOS_ReadMemory();
2166
2167 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2168 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2169
2170 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2171 {
2172 if (HVD_GetSysTime_ms() > u32Timeout)
2173 {
2174 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2175 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2176 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2177
2178 if(pVPUHalContext->u8TaskCnt == 1)
2179 {
2180 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2181 break;
2182 }
2183 else if(pVPUHalContext->u8TaskCnt == 2)
2184 {
2185 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2186 break;
2187 }
2188 else
2189 {
2190 VPU_MSG_ERR("Task number is not correct\n");
2191 _HAL_VPU_Release();
2192 return FALSE;
2193 }
2194 }
2195
2196 MsOS_ReadMemory();
2197 }
2198
2199 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2200 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2201 }
2202 #if SUPPORT_EVD
2203 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2204 {
2205 HAL_EVD_EX_ClearTSPInput(u32Id);
2206 }
2207 #endif
2208
2209 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2210 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2211 {
2212 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2213 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2214 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2215 }
2216
2217 #if VPU_FIELD_DETECTOR
2218 _HAL_VPU_EX_FdTask_Delete(u32Id, pVPUHalContext);
2219 #endif
2220
2221 if (pVPUHalContext->u8TaskCnt)
2222 {
2223 (pVPUHalContext->u8TaskCnt)--;
2224 }
2225 else
2226 {
2227 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2228 }
2229
2230 if (0 == pVPUHalContext->u8TaskCnt)
2231 {
2232 int i;
2233 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2234 _VPU_EX_DeinitAll(pInitPara);
2235 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2236 pVPUHalContext->u32VPUSHMAddr = 0;
2237
2238 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2239 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2240 }
2241 else
2242 {
2243 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2244 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2245 }
2246
2247 _HAL_VPU_Release();
2248 return TRUE;
2249 }
2250
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2251 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2252 {
2253 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2254 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2255 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2256 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2257 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2258 #endif
2259
2260 if (FALSE == HAL_VPU_EX_GetFWReload())
2261 {
2262 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2263 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2264 {
2265 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2266 }
2267 else
2268 {
2269 //Check f/w prefix "VDEC30"
2270 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2271 {
2272 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2273 }
2274 else
2275 {
2276 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2277 return TRUE;
2278 }
2279 }
2280 }
2281
2282 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2283 {
2284 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2285 if (u32Size != 0)
2286 {
2287 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2288
2289
2290 MS_U32 u32Start;
2291 MS_U32 u32StartOffset;
2292 MS_U8 u8MiuSel;
2293
2294 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2295
2296
2297 if(u8MiuSel == E_CHIP_MIU_0)
2298 cpyflag = E_SPIDMA_DEV_MIU0;
2299 else if(u8MiuSel == E_CHIP_MIU_1)
2300 cpyflag = E_SPIDMA_DEV_MIU1;
2301 else if(u8MiuSel == E_CHIP_MIU_2)
2302 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2303
2304 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2305 {
2306 goto _load_code_fail;
2307 }
2308 }
2309 else
2310 {
2311 goto _load_code_fail;
2312 }
2313 #else
2314 goto _load_code_fail;
2315 #endif
2316 }
2317 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2318 {
2319 if (u32BinAddr != 0 && u32Size != 0)
2320 {
2321 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2322 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2323 {
2324 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2325 {
2326 VPU_MSG_INFO("Decompress ok!!!\n");
2327 }
2328 else
2329 {
2330 VPU_MSG_INFO("Decompress fail!!!\n");
2331 }
2332 }
2333 else
2334 #endif
2335 {
2336 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2337 }
2338 }
2339 else
2340 {
2341 goto _load_code_fail;
2342 }
2343 }
2344 else
2345 {
2346 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2347 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2348 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2349 (MS_U32) sizeof(u8HVD_FW_Binary));
2350
2351 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2352 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2353 {
2354 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2355 {
2356 VPU_MSG_INFO("Decompress ok!!!\n");
2357 }
2358 else
2359 {
2360 VPU_MSG_INFO("Decompress fail!!!\n");
2361 }
2362 }
2363 else
2364 #endif
2365 {
2366 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2367 }
2368 #else
2369 goto _load_code_fail;
2370 #endif
2371 }
2372
2373 MAsm_CPU_Sync();
2374 MsOS_FlushMemory();
2375
2376 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2377 {
2378 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2379 goto _load_code_fail;
2380 }
2381
2382 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2383 return TRUE;
2384
2385 _load_code_fail:
2386 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2387 return FALSE;
2388 }
2389
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2390 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2391 {
2392 u32VPURegOSBase = u32RegBase;
2393 }
2394
HAL_VPU_EX_Init_Share_Mem(void)2395 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2396 {
2397 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2398
2399 MS_U32 u32ShmId;
2400 MS_VIRT u32Addr;
2401 MS_U32 u32BufSize;
2402
2403
2404 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2405 sizeof(VPU_Hal_CTX),
2406 &u32ShmId,
2407 &u32Addr,
2408 &u32BufSize,
2409 MSOS_SHM_QUERY))
2410 {
2411 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2412 sizeof(VPU_Hal_CTX),
2413 &u32ShmId,
2414 &u32Addr,
2415 &u32BufSize,
2416 MSOS_SHM_CREATE))
2417 {
2418 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2419 if(pVPUHalContext == NULL)
2420 {
2421 pVPUHalContext = &gVPUHalContext;
2422 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2423 _VPU_EX_Context_Init();
2424 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2425 }
2426 else
2427 {
2428 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2429 }
2430 //return FALSE;
2431 }
2432 else
2433 {
2434 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2435 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2436 _VPU_EX_Context_Init();
2437 }
2438 }
2439 else
2440 {
2441 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2442 }
2443 #else
2444 if(pVPUHalContext == NULL)
2445 {
2446 pVPUHalContext = &gVPUHalContext;
2447 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2448 _VPU_EX_Context_Init();
2449 }
2450 #endif
2451
2452 return TRUE;
2453
2454 }
2455
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2456 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2457 {
2458 MS_U32 i = 0;
2459
2460 _HAL_VPU_MutexCreate();
2461
2462 _HAL_VPU_Entry();
2463
2464 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2465 {
2466 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2467 {
2468 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2469 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2470 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2471 _HAL_VPU_Release();
2472 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2473 }
2474 }
2475 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2476 {
2477 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2478 {
2479 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2480 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2481 {
2482 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2483 _HAL_VPU_Release();
2484 return pVPUHalContext->_stVPUStream[i].eStreamId;
2485 }
2486 }
2487 }
2488 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2489 {
2490 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2491 {
2492 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2493 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2494 {
2495 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2496 _HAL_VPU_Release();
2497 return pVPUHalContext->_stVPUStream[i].eStreamId;
2498 }
2499 }
2500 }
2501 #ifdef VDEC3
2502 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2503 {
2504 #if 1 // bound FW task to main/sub stream
2505 i = eStreamType - E_HAL_VPU_N_STREAM;
2506 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2507 {
2508 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2509 _HAL_VPU_Release();
2510 return pVPUHalContext->_stVPUStream[i].eStreamId;
2511 }
2512 #else // dynamic select FW task id
2513 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2514 {
2515 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2516 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2517 {
2518 return pVPUHalContext->_stVPUStream[i].eStreamId;
2519 }
2520 }
2521 #endif
2522 }
2523 #endif
2524
2525 _HAL_VPU_Release();
2526
2527 return E_HAL_VPU_STREAM_NONE;
2528 }
2529
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2530 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2531 {
2532 _HAL_VPU_Entry();
2533
2534 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2535 {
2536 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2537 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2538 }
2539 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2540 {
2541 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2542 }
2543
2544 _HAL_VPU_Release();
2545
2546 return TRUE;
2547 }
2548
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2549 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2550 {
2551 MS_U8 u8Idx = 0;
2552
2553 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2554
2555 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2556 {
2557 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2558 {
2559 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2560 return 0;
2561 }
2562 }
2563 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2564 {
2565 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2566 {
2567 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2568 return 1;
2569 }
2570 }
2571
2572 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2573 {
2574 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2575 break;
2576 }
2577
2578 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2579 {
2580 VPU_MSG_ERR("all vpu free streams are occupied \n");
2581 return 0xFF;
2582 }
2583
2584 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2585 return u8Idx;
2586 }
2587
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2588 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2589 {
2590 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2591
2592 // enable module
2593 _VPU_EX_ClockInv(InitParams->bClockInv);
2594 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2595 HAL_VPU_EX_PowerCtrl(TRUE);
2596
2597 #ifdef CONFIG_MSTAR_CLKM
2598 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2599 #endif
2600
2601 #ifdef CONFIG_MSTAR_SRAMPD
2602 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2603 HVD_Delay_ms(1);
2604 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2605 HVD_Delay_ms(1);
2606 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2607 HVD_Delay_ms(1);
2608 #endif
2609 #if 1 //Create VPU's own mutex
2610 //_HAL_VPU_MutexCreate();
2611 #else
2612 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2613 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2614 #endif
2615
2616 return TRUE;
2617 }
2618
HAL_VPU_EX_DeInit(void)2619 MS_BOOL HAL_VPU_EX_DeInit(void)
2620 {
2621 if (0 != _VPU_EX_GetActiveCodecCnt())
2622 {
2623 VPU_MSG_DBG("do nothing since codec is active.\n");
2624 return TRUE;
2625 }
2626
2627 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2628
2629 #ifdef CONFIG_MSTAR_CLKM
2630 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2631 #else
2632 HAL_VPU_EX_PowerCtrl(FALSE);
2633 #endif
2634
2635 #ifdef CONFIG_MSTAR_SRAMPD
2636 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2637 HVD_Delay_ms(1);
2638 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2639 HVD_Delay_ms(1);
2640 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2641 HVD_Delay_ms(1);
2642 #endif
2643
2644 HAL_VPU_EX_SwRelseMAU();
2645 //_HAL_VPU_MutexDelete();
2646
2647 return TRUE;
2648 }
2649
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2650 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2651 {
2652 if (bEnable)
2653 {
2654 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2655 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2656 pVPUHalContext->_bVPUPowered = TRUE;
2657 }
2658 else
2659 {
2660 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2661 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2662 pVPUHalContext->_bVPUPowered = FALSE;
2663 }
2664 }
2665
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2666 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2667 {
2668 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2669 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2670 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2671 VPU_EX_TimerDelayMS(1);
2672 }
2673
2674 ///-----------------------------------------------------------------------------
2675 /// config AVCH264 CPU
2676 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2677 /// @param u8dlend_en \b IN: endian
2678 /// - 1, little endian
2679 /// - 0, big endian
2680 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2681 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2682 {
2683 MS_BOOL bRet = TRUE;
2684 MS_U32 u32Offset = 0;
2685 MS_U16 tempreg = 0;
2686 MS_U8 u8MiuSel;
2687 //MS_U32 u32TmpStartOffset;
2688
2689 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2690
2691 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2692 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2693 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2694 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2695 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2696 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2697 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2698 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2699 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2700 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2701
2702 #if (HVD_ENABLE_IQMEM)
2703 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2704 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2705 #endif
2706
2707 #if (VPU_FORCE_MIU_MODE)
2708 // Data sram base Unit: byte address
2709 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2710 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2711 // Instruction sram base Unit: byte address
2712 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2713 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2714
2715 #ifndef HAL_FEATURE_MAU
2716 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2717 #endif
2718 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2719
2720 //use force miu mode
2721 if(u8MiuSel == E_CHIP_MIU_0)
2722 {
2723 #ifdef HAL_FEATURE_MAU
2724 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2725 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2726 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2727 #else
2728 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2729 #endif
2730 }
2731 else if(u8MiuSel == E_CHIP_MIU_1)
2732 {
2733 #ifdef HAL_FEATURE_MAU
2734 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2735 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2736 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2737 #else
2738 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2739 #endif
2740 }
2741 else //miu 2
2742 {
2743 #ifdef HAL_FEATURE_MAU
2744 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2745 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2746 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2747 #else
2748 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2749 #endif
2750 }
2751 #else
2752 ///TODO:
2753 #endif
2754
2755
2756 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2757 tempreg |= VPU_REG_IO2_EN;
2758 tempreg |= VPU_REG_QMEM_SPACE_EN;
2759 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2760
2761 return bRet;
2762 }
2763
2764 ///-----------------------------------------------------------------------------
2765 /// Set IQMem data access mode or instruction fetch mode
2766 /// @param u8dlend_en \b IN: endian
2767 /// - 1, switch to data access mode
2768 /// - 0, switch to instruction fetch mode
2769 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2770 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2771 {
2772
2773 if(bEnable){
2774
2775 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2776 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2777
2778 }
2779 else{
2780
2781 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2782
2783 }
2784 }
2785
2786 ///-----------------------------------------------------------------------------
2787 /// H.264 SW reset
2788 /// @return TRUE or FALSE
2789 /// - TRUE, Success
2790 /// - FALSE, Failed
2791 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2792 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2793 {
2794 MS_U16 tempreg = 0, tempreg1 = 0;
2795 MS_U16 idle_cnt;
2796 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2797 tempreg |= VPU_REG_CPU_STALL_EN;
2798 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2799
2800 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2801 // 0xf means VPU is not stalled
2802 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2803 pVPUHalContext->u8ForceRst = 0;
2804 // write R2 RIU registers to select DCU/ICU debug data
2805 // Writing these registers here provides enough time for them to
2806 // take effect.
2807 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2808 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2809 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2810 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2811
2812 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2813 // This step is important because in the next step we want to make
2814 // sure "DCU is not replaying when R2 is stalled".
2815 idle_cnt = 100;
2816 do
2817 {
2818 if (--idle_cnt == 0)
2819 {
2820 printf("VPU_REG_CPU_STALL_EN is not set\n");
2821 break;
2822 }
2823 MsOS_DelayTask(1);
2824 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2825 // check CPU status: DCU should NOT be replaying
2826 // If R2 has been stalled, we can guarantee that if we found DCU is
2827 // NOT replaying, it will NOT replay later even CPU is going to issue
2828 // a load/store instruction.
2829 idle_cnt = 100;
2830 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2831 {
2832 if (--idle_cnt == 0)
2833 {
2834 printf("DCU is replaying\n");
2835 break;
2836 }
2837 MsOS_DelayTask(1);
2838 }
2839 // wait 1ms to prevent race condition between (1) DCU is not
2840 // replaying, and (2) BIU start to doing new job or ICU start to
2841 // fetch new instruction
2842 MsOS_DelayTask(1);
2843
2844 // check BIU should be empty
2845 idle_cnt = 100;
2846 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2847 {
2848 if (--idle_cnt == 0)
2849 {
2850 printf("BIU DCU idle time out~~~~~\n");
2851 break;
2852 }
2853 MsOS_DelayTask(1);
2854 }
2855
2856 // check CPU is not requesting ICU
2857 idle_cnt = 100;
2858 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2859 {
2860 if (--idle_cnt == 0)
2861 {
2862 printf("CPU keeps requesting ICU\n");
2863 break;
2864 }
2865 MsOS_DelayTask(1);
2866 }
2867
2868 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2869 // (2) ISB start to fetch
2870 MsOS_DelayTask(1);
2871
2872 // check ISB should be idle
2873 idle_cnt = 100;
2874 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2875 {
2876 if (--idle_cnt == 0)
2877 {
2878 printf("ISB is busy\n");
2879 break;
2880 }
2881 MsOS_DelayTask(1);
2882 }
2883 }
2884 #ifdef HAL_FEATURE_MAU
2885 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2886 if (bCheckMauIdle)
2887 {
2888 MS_U32 mau_idle_cnt = 100;// ms
2889 while (mau_idle_cnt)
2890 {
2891 if (TRUE == _VPU_EX_MAU_IDLE())
2892 {
2893 break;
2894 }
2895 mau_idle_cnt--;
2896 MsOS_DelayTask(1);
2897 }
2898
2899 if (mau_idle_cnt == 0)
2900 {
2901 printf("MAU idle time out~~~~~\n");
2902 }
2903 }
2904 #endif
2905
2906 // this command set MIU to block R2 (does not ack R2's request)
2907 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2908
2909 #ifdef HAL_FEATURE_MAU
2910 // reset MAU
2911 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2912 tempreg1 |= MAU1_REG_SW_RESET;
2913 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2914 #if defined(UDMA_FPGA_ENVI)
2915 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2916 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2917 #endif
2918 #endif
2919
2920 // reset R2
2921 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2922 // by the same RIU write, the R2 reset signal may reach afifo eralier
2923 // than MIU reset and afifo write pointer will be reset to position 0.
2924 // In this case, afifo consider it is not empty because read/write
2925 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2926 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2927 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2928 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2929 VPU_EX_TimerDelayMS(1);
2930 tempreg &= ~VPU_REG_CPU_R2_EN;
2931 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2932 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2933
2934 VPU_EX_TimerDelayMS(1);
2935
2936 // this command set MIU to accept R2 (can ack R2's request)
2937 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2938
2939 pVPUHalContext->_bVPURsted = FALSE;
2940 return TRUE;
2941 }
2942 /*
2943 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2944 {
2945 MS_U16 tempreg = 0, tempreg1 = 0;
2946 #ifndef HAL_FEATURE_MAU
2947 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2948 tempreg |= VPU_REG_CPU_STALL_EN;
2949 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2950
2951 MS_U32 idle_cnt = 100;// ms
2952 while (idle_cnt)
2953 {
2954 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2955 {
2956 break;
2957 }
2958 idle_cnt--;
2959 MsOS_DelayTask(1);
2960 }
2961
2962 if (idle_cnt == 0)
2963 {
2964 printf("ISB ICU idle time out~~~~~\n");
2965 }
2966
2967 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2968 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2969 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2970 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2971
2972 MS_U32 idle_cnt_1 = 100;// ms
2973 while (idle_cnt_1)
2974 {
2975 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2976 {
2977 break;
2978 }
2979 idle_cnt_1--;
2980 MsOS_DelayTask(1);
2981 }
2982
2983 if (idle_cnt_1 == 0)
2984 {
2985 printf("BIU DCU idle time out~~~~~\n");
2986 }
2987
2988 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2989 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2990 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2991 VPU_EX_TimerDelayMS(1);
2992 tempreg &= ~VPU_REG_CPU_R2_EN;
2993 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2994 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2995
2996 #else
2997 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2998
2999 if (bCheckMauIdle)
3000 {
3001 MS_U32 mau_idle_cnt = 100;// ms
3002 while (mau_idle_cnt)
3003 {
3004 if (TRUE == _VPU_EX_MAU_IDLE())
3005 {
3006 break;
3007 }
3008 mau_idle_cnt--;
3009 MsOS_DelayTask(1);
3010 }
3011
3012 if (mau_idle_cnt == 0)
3013 {
3014 printf("MAU idle time out~~~~~\n");
3015 }
3016 }
3017
3018
3019 HAL_VPU_EX_MIU_RW_Protect(TRUE);
3020
3021 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3022 tempreg1 |= MAU1_REG_SW_RESET;
3023 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3024
3025 #if defined(UDMA_FPGA_ENVI)
3026 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3027 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3028 #endif
3029
3030 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3031 tempreg &= ~VPU_REG_CPU_R2_EN;
3032 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3033 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3034 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3035 #endif
3036 VPU_EX_TimerDelayMS(1);
3037 HAL_VPU_EX_MIU_RW_Protect(FALSE);
3038
3039 pVPUHalContext->_bVPURsted = FALSE;
3040 return TRUE;
3041 }
3042 */
3043 ///-----------------------------------------------------------------------------
3044 /// CPU reset release
3045 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)3046 void HAL_VPU_EX_SwRstRelse(void)
3047 {
3048 MS_U16 tempreg = 0;
3049
3050 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
3051 tempreg &= ~VPU_REG_CPU_STALL_EN;
3052 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
3053
3054 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3055 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3056 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3057 VPU_EX_TimerDelayMS(1);
3058 tempreg |= VPU_REG_CPU_SW_RSTZ;
3059 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3060 VPU_EX_TimerDelayMS(1);
3061 tempreg |= VPU_REG_CPU_R2_EN;
3062 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3063 #ifdef HAL_FEATURE_MAU
3064 MS_U16 tempreg1 = 0;
3065 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3066 tempreg1 &= ~MAU1_REG_SW_RESET;
3067 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3068 #endif
3069 pVPUHalContext->_bVPURsted = TRUE;
3070 }
3071
HAL_VPU_EX_SwRelseMAU(void)3072 void HAL_VPU_EX_SwRelseMAU(void)
3073 {
3074
3075 #ifdef HAL_FEATURE_MAU
3076 MS_U16 tempreg = 0;
3077 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
3078 tempreg &= ~MAU1_REG_SW_RESET;
3079 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
3080 #endif
3081 }
3082
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3083 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3084 {
3085 MS_U32 u32value = 0;
3086
3087 return u32value;
3088 }
3089
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3090 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3091 {
3092 MS_BOOL bRet = TRUE;
3093
3094 return bRet;
3095 }
3096
3097 ///-----------------------------------------------------------------------------
3098 /// Check AVCH264 Ready or not
3099 /// @return TRUE or FALSE
3100 /// - TRUE, MailBox is free
3101 /// - FALSE, MailBox is busy
3102 /// @param u8MBox \b IN: MailBox to check
3103 /// - AVCH264_HI_MBOX0,
3104 /// - AVCH264_HI_MBOX1,
3105 /// - AVCH264_RISC_MBOX0,
3106 /// - AVCH264_RISC_MBOX1,
3107 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)3108 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
3109 {
3110 MS_BOOL bResult = FALSE;
3111
3112 switch (u32type)
3113 {
3114 case VPU_HI_MBOX0:
3115 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3116 break;
3117 case VPU_HI_MBOX1:
3118 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3119 break;
3120 case VPU_RISC_MBOX0:
3121 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3122 break;
3123 case VPU_RISC_MBOX1:
3124 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3125 break;
3126 default:
3127 break;
3128 }
3129 return bResult;
3130 }
3131
3132
3133 ///-----------------------------------------------------------------------------
3134 /// Read message from AVCH264
3135 /// @return TRUE or FALSE
3136 /// - TRUE, success
3137 /// - FALSE, failed
3138 /// @param u8MBox \b IN: MailBox to read
3139 /// - AVCH264_RISC_MBOX0
3140 /// - AVCH264_RISC_MBOX1
3141 /// @param u32Msg \b OUT: message read
3142 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)3143 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
3144 {
3145 MS_BOOL bResult = TRUE;
3146
3147 switch (u32type)
3148 {
3149 case VPU_HI_MBOX0:
3150 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3151 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3152 break;
3153 case VPU_HI_MBOX1:
3154 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3155 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3156 break;
3157 case VPU_RISC_MBOX0:
3158 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3159 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3160 break;
3161 case VPU_RISC_MBOX1:
3162 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3163 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3164 break;
3165 default:
3166 *u32Msg = 0;
3167 bResult = FALSE;
3168 break;
3169 }
3170 return bResult;
3171 }
3172
3173 ///-----------------------------------------------------------------------------
3174 /// Mailbox from AVCH264 clear bit resest
3175 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3176 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3177 {
3178 switch (u32type)
3179 {
3180 case VPU_RISC_MBOX0:
3181 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3182 break;
3183 case VPU_RISC_MBOX1:
3184 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3185 break;
3186 default:
3187 break;
3188 }
3189 }
3190
3191 ///-----------------------------------------------------------------------------
3192 /// Send message to AVCH264
3193 /// @return TRUE or FALSE
3194 /// - TRUE, Success
3195 /// - FALSE, Failed
3196 /// @param u8MBox \b IN: MailBox
3197 /// - AVCH264_HI_MBOX0,
3198 /// - AVCH264_HI_MBOX1,
3199 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3200 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3201 {
3202 MS_BOOL bResult = TRUE;
3203
3204 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3205
3206 switch (u32type)
3207 {
3208 case VPU_HI_MBOX0:
3209 {
3210 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3211 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3212 break;
3213 }
3214 case VPU_HI_MBOX1:
3215 {
3216 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3217 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3218 break;
3219 }
3220 default:
3221 {
3222 bResult = FALSE;
3223 break;
3224 }
3225 }
3226
3227 return bResult;
3228 }
3229
HAL_VPU_EX_GetProgCnt(void)3230 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3231 {
3232
3233 MS_U16 expc_l=0;
3234 MS_U16 expc_h=0;
3235 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3236 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3237 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3238 }
3239
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3240 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3241 {
3242 return _VPU_EX_GetOffsetIdx(u32Id);
3243 }
3244
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3245 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3246 {
3247 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3248
3249 if (u32ShmAddr == 0)
3250 {
3251 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3252 }
3253 else
3254 {
3255 if (u8Offset == 0)
3256 {
3257 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3258 }
3259 else if (u8Offset == 1)
3260 {
3261 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3262 }
3263 }
3264
3265 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3266 return;
3267 }
3268
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3269 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3270 {
3271 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3272
3273 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3274 }
3275
3276 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3277 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3278 {
3279 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3280 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3281 MS_VIRT VsyncBridgeOffset = 0;
3282
3283 if (VPUSHMAddr != 0) // TEE project
3284 {
3285 if ((u8Offset == 0) || (u8Offset == 1))
3286 {
3287 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3288 }
3289 else
3290 {
3291 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3292 }
3293 }
3294 else // normal project
3295 {
3296 if ((u8Offset == 0) || (u8Offset == 1))
3297 {
3298 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3299 }
3300 else
3301 {
3302 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3303 }
3304 }
3305
3306 return VsyncBridgeOffset;
3307 }
3308
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3309 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3310 {
3311 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3312 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3313 MS_VIRT VsyncBridgeExtOffset = 0;
3314
3315 if (VPUSHMAddr != 0) // TEE project
3316 {
3317 if ((u8Offset == 0) || (u8Offset == 1))
3318 {
3319 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3320 }
3321 else
3322 {
3323 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3324 }
3325 }
3326 else // normal project
3327 {
3328 if ((u8Offset == 0) || (u8Offset == 1))
3329 {
3330 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3331 }
3332 else
3333 {
3334 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3335 }
3336 }
3337
3338 return VsyncBridgeExtOffset;
3339 }
3340 #endif
3341
HAL_VPU_EX_IsPowered(void)3342 MS_BOOL HAL_VPU_EX_IsPowered(void)
3343 {
3344 return pVPUHalContext->_bVPUPowered;
3345 }
3346
HAL_VPU_EX_IsRsted(void)3347 MS_BOOL HAL_VPU_EX_IsRsted(void)
3348 {
3349 return pVPUHalContext->_bVPURsted;
3350 }
3351
HAL_VPU_EX_IsEVDR2(void)3352 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3353 {
3354 #ifdef EVDR2
3355 return TRUE;
3356 #else
3357 return FALSE;
3358 #endif
3359 }
3360
HAL_VPU_EX_MVDInUsed(void)3361 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3362 {
3363 //MVD is in used for MVD or HVD_TSP mode.
3364 MS_U8 i;
3365 MS_U8 u8UseCnt = 0;
3366
3367 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3368 {
3369 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3370 #ifdef VDEC3
3371 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3372 #endif
3373 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3374 {
3375 u8UseCnt++;
3376 }
3377 }
3378
3379 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3380
3381 if (u8UseCnt != 0)
3382 {
3383 return TRUE;
3384 }
3385 else
3386 {
3387 return FALSE;
3388 }
3389 }
3390
HAL_VPU_EX_HVDInUsed(void)3391 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3392 {
3393 //HVD is in used for HVD or MVD in sub stream.
3394 MS_U8 i;
3395 MS_U8 u8UseCnt = 0;
3396 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3397 {
3398 if (E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3399 {
3400 u8UseCnt++;
3401 }
3402 }
3403
3404 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3405
3406 if (u8UseCnt != 0)
3407 {
3408 return TRUE;
3409 }
3410 else
3411 {
3412 return FALSE;
3413 }
3414 }
3415
HAL_VPU_EX_Mutex_Lock(void)3416 void HAL_VPU_EX_Mutex_Lock(void)
3417 {
3418 _HAL_VPU_Entry();
3419 }
3420
HAL_VPU_EX_Mutex_UnLock(void)3421 void HAL_VPU_EX_Mutex_UnLock(void)
3422 {
3423 _HAL_VPU_Release();
3424 }
3425
3426 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3427 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3428 {
3429 MS_U8 i;
3430 MS_U8 u8UseCnt = 0;
3431
3432 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3433 {
3434 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3435 {
3436 u8UseCnt++;
3437 }
3438 }
3439
3440 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3441
3442 if (u8UseCnt != 0)
3443 {
3444 return TRUE;
3445 }
3446 else
3447 {
3448 return FALSE;
3449 }
3450 }
3451
3452 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3453 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3454 {
3455 MS_U8 i;
3456 MS_U8 u8UseCnt = 0;
3457
3458 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3459 {
3460 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3461 {
3462 u8UseCnt++;
3463 }
3464 }
3465
3466 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3467
3468 if (u8UseCnt != 0)
3469 {
3470 return TRUE;
3471 }
3472 else
3473 {
3474 return FALSE;
3475 }
3476 }
3477 #endif
3478 #endif
3479
3480 //-----------------------------------------------------------------------------
3481 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3482 /// @brief \b Function \b Description: Set debug level
3483 /// @param -elevel \b IN : debug level
3484 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3485 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3486 {
3487 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3488
3489 switch (eLevel)
3490 {
3491 case E_VPU_EX_UART_LEVEL_ERR:
3492 {
3493 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3494 break;
3495 }
3496 case E_VPU_EX_UART_LEVEL_INFO:
3497 {
3498 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3499 break;
3500 }
3501 case E_VPU_EX_UART_LEVEL_DBG:
3502 {
3503 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3504 break;
3505 }
3506 case E_VPU_EX_UART_LEVEL_TRACE:
3507 {
3508 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3509 break;
3510 }
3511 case E_VPU_EX_UART_LEVEL_FW:
3512 {
3513 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3514 break;
3515 }
3516 default:
3517 {
3518 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3519 break;
3520 }
3521 }
3522 }
3523
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3524 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3525 {
3526 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3527 MS_U32 u32CmdArg = (MS_U32)eVerType;
3528 MS_U32 u32Version = 0xFFFFFFFF;
3529 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3530 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3531 {
3532 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3533 return u32Version;
3534 }
3535
3536 MS_BOOL bRet = false;
3537 MS_U32 u32TimeOut = 0xFFFFFFFF;
3538
3539 while(--u32TimeOut)
3540 {
3541 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3542 {
3543 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3544 if (false == bRet)
3545 {
3546 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3547 return u32Version;
3548 }
3549
3550 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3551 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3552 return u32Version;
3553 }
3554 }
3555
3556 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3557
3558 return u32Version;
3559 }
3560
HAL_VPU_EX_NotSupportDS(void)3561 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3562 {
3563 return FALSE;
3564 }
3565
3566 //-----------------------------------------------------------------------------
3567 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3568 /// @brief \b Function \b Description: Get VPU MIU base address
3569 /// @return - vpu MIU1 base
3570 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3571 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3572 {
3573 return VPU_MIU1BASE_ADDR;
3574 }
3575
3576
HAL_VPU_EX_GetSHMAddr(void)3577 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3578 {
3579 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3580 {
3581 return 0;
3582 }
3583 return pVPUHalContext->u32VPUSHMAddr;
3584 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3585 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3586 {
3587 pVPUHalContext->bEnableVPUSecureMode = enable;
3588 return TRUE;
3589 }
3590
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3591 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3592 {
3593 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3594
3595 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3596 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3597 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3598 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3599 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3600 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3601 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3602 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3603
3604 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3605 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3606 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3607 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3608 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3609 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3610 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3611 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3612 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3613 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3614
3615 return TRUE;
3616 }
3617
3618 //-----------------------------------------------------------------------------
3619 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3620 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3621 /// @return - success/fail
3622 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3623 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3624 {
3625 #define MAX_CAPABILITY_INFO_NUM 8
3626 #define MAX_CODEC_TYPE_NUM 18
3627
3628 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3629 {
3630 //width, height , frmrate, profile, level, version bit rate reserved2
3631 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3632 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3633 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3634 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3635 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3636 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3637 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3638 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3639 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3640 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3641 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3642 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3643 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3644 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3645 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3646 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3647 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3648 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3649 };
3650
3651 if(eCodecType < MAX_CODEC_TYPE_NUM)
3652 {
3653 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3654 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3655 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3656 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3657 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3658 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3659 return TRUE;
3660 }
3661 else
3662 {
3663 return FALSE;
3664 }
3665 }
3666
3667 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3668 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3669 {
3670 (void) u32Id;
3671 BBU_STATE *bbu_state;
3672
3673 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3674 || (eDecType == E_VPU_EX_DECODER_VP8)
3675 #if SUPPORT_G2VP9
3676 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3677 #endif
3678 )
3679 {
3680 // MVD should not call this function.
3681 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3682 return;
3683 }
3684
3685 switch (eDecType)
3686 {
3687 case E_VPU_EX_DECODER_EVD:
3688 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3689 break;
3690 case E_VPU_EX_DECODER_HVD:
3691 case E_VPU_EX_DECODER_RVD:
3692 case E_VPU_EX_DECODER_MVC:
3693 default:
3694 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3695 break;
3696 }
3697
3698 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3699 return;
3700 }
3701
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3702 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3703 {
3704 (void) u32Id;
3705 BBU_STATE *bbu_state;
3706
3707 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3708 || (eDecType == E_VPU_EX_DECODER_VP8)
3709 #if SUPPORT_G2VP9
3710 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3711 #endif
3712 )
3713 {
3714 // MVD should not call this function.
3715 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3716 return TRUE;
3717 }
3718
3719 switch (eDecType)
3720 {
3721 case E_VPU_EX_DECODER_EVD:
3722 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3723 break;
3724 case E_VPU_EX_DECODER_HVD:
3725 case E_VPU_EX_DECODER_RVD:
3726 case E_VPU_EX_DECODER_MVC:
3727 default:
3728 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3729 break;
3730 }
3731
3732 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3733 }
3734
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3735 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3736 {
3737 (void) u32Id;
3738 BBU_STATE *bbu_state;
3739
3740 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3741 || (eDecType == E_VPU_EX_DECODER_VP8)
3742 #if SUPPORT_G2VP9
3743 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3744 #endif
3745 )
3746 {
3747 // MVD should not call this function.
3748 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3749 return;
3750 }
3751
3752 switch (eDecType)
3753 {
3754 case E_VPU_EX_DECODER_EVD:
3755 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3756 break;
3757 case E_VPU_EX_DECODER_HVD:
3758 case E_VPU_EX_DECODER_RVD:
3759 case E_VPU_EX_DECODER_MVC:
3760 default:
3761 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3762 break;
3763 }
3764
3765 if (bbu_state[u32BBUId].u32Used == 0)
3766 {
3767 bbu_state[u32BBUId].u8RegSetting = 0;
3768 }
3769
3770 return;
3771 }
3772
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3773 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3774 {
3775 MS_U32 i, max_bbu_cnt;
3776 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3777
3778 if(pTaskInfo == NULL)
3779 return retBBUId;
3780
3781 BBU_STATE *bbu_state;
3782 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3783 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3784
3785 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3786
3787 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3788
3789 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3790 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3791 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3792
3793 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3794 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3795
3796 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3797 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3798 */
3799 #if 1
3800 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3801 {
3802 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3803 if (bTSP)
3804 {
3805 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3806 {
3807 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3808 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3809 slq_state[u8TaskId].bTSP = TRUE;
3810 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3811 return u8TaskId;
3812 }
3813 }
3814 else
3815 {
3816 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3817 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3818 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3819 {
3820 if (slq_state[i].u32Used != 0)
3821 {
3822 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3823 {
3824 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3825 }
3826 }
3827 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3828 {
3829 avaliable_bbu_idx = i; // recored the first empty bbu
3830 }
3831 }
3832
3833 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3834
3835 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3836 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3837 slq_state[shared_bbu_idx].bTSP = FALSE;
3838 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3839 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3840 return shared_bbu_idx;
3841 }
3842 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3843 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3844 slq_state[u8TaskId].bTSP = FALSE;
3845 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3846
3847 if (bShareBBU == FALSE)
3848 {
3849 slq_state[u8TaskId].bTSP = TRUE;
3850 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3851 }
3852 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3853 return u8TaskId;
3854 }
3855 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3856 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3857 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3858 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3859
3860 if (bShareBBU == FALSE)
3861 {
3862 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3863 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3864 }
3865 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3866 return avaliable_bbu_idx;
3867 }
3868 else {
3869 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3870 }
3871 }
3872 }
3873 #if SUPPORT_G2VP9
3874 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3875 {
3876 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3877 // Don't care the return value, G2_VP9 will not use it.
3878 return 0;
3879 }
3880 #endif
3881 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3882 {
3883 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3884 // Don't care the return value, VP8 will not use it.
3885 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3886 return u8Offset;
3887 //return 0;
3888 }
3889 else
3890 {
3891 switch (pTaskInfo->eDecType)
3892 {
3893 case E_VPU_EX_DECODER_EVD:
3894 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3895 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3896 break;
3897 case E_VPU_EX_DECODER_HVD:
3898 case E_VPU_EX_DECODER_RVD:
3899 case E_VPU_EX_DECODER_MVC:
3900 default:
3901 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3902 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3903 break;
3904 }
3905
3906 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3907 if (bTSP)
3908 {
3909 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3910 {
3911 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3912 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3913 bbu_state[u8TaskId].bTSP = TRUE;
3914 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3915 slq_state[u8TaskId].bTSP = TRUE;
3916 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3917 return u8TaskId;
3918 }
3919 }
3920 else
3921 {
3922 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3923 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3924 for (i = 0; i < max_bbu_cnt; i++)
3925 {
3926 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3927 {
3928 if (bbu_state[i].bTSP == FALSE)
3929 {
3930 shared_bbu_idx = i;
3931 }
3932 }
3933 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3934 {
3935 avaliable_bbu_idx = i;
3936 }
3937 }
3938
3939 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3940
3941 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3942 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3943 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3944 return shared_bbu_idx;
3945 }
3946 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3947 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3948
3949 if (bShareBBU == FALSE)
3950 {
3951 bbu_state[u8TaskId].bTSP = TRUE;
3952 VPRINTF("[NDec] occupy one BBU_ID \n");
3953 }
3954 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3955 return u8TaskId;
3956 }
3957 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3958 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3959
3960 if (bShareBBU == FALSE)
3961 {
3962 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3963 VPRINTF("[NDec] occupy one BBU_ID \n");
3964 }
3965 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3966 return avaliable_bbu_idx;
3967 }
3968 else {
3969 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3970 }
3971 }
3972 }
3973 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3974 MS_U32 j;
3975 MS_BOOL Got = FALSE;
3976 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3977 {
3978 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3979 {
3980 if(slq_state[i].u32Used != 0)
3981 {
3982 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3983 {
3984 retBBUId = i;
3985 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3986 slq_state[retBBUId].bTSP = bTSP;
3987 slq_state[retBBUId].bUsedbyMVD = TRUE;
3988 return retBBUId;
3989 }
3990 }
3991 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3992 {
3993 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3994 {
3995 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3996 {
3997 Got = TRUE;
3998 retBBUId = i;
3999 }
4000 }
4001
4002 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
4003 {
4004 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
4005 {
4006 Got = TRUE;
4007 retBBUId = i;
4008 }
4009 }
4010
4011 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
4012 retBBUId = i;
4013 }
4014 }
4015 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4016 {
4017 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4018 slq_state[retBBUId].bTSP = bTSP;
4019 slq_state[retBBUId].bUsedbyMVD = TRUE;
4020 }
4021 }
4022 #if SUPPORT_G2VP9
4023 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4024 {
4025 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4026 // Don't care the return value, G2_VP9 will not use it.
4027 return 0;
4028 }
4029 #endif
4030 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4031 {
4032 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4033 // Don't care the return value, VP8 will not use it.
4034 return 0;
4035 }
4036 else // HVD/EVD case
4037 {
4038 switch (pTaskInfo->eDecType)
4039 {
4040 case E_VPU_EX_DECODER_EVD:
4041 case E_VPU_EX_DECODER_G2VP9:
4042 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4043 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4044 break;
4045 case E_VPU_EX_DECODER_HVD:
4046 case E_VPU_EX_DECODER_RVD:
4047 case E_VPU_EX_DECODER_MVC:
4048 default:
4049 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4050 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4051 break;
4052 }
4053
4054 for (i = 0; i < max_bbu_cnt; i++)
4055 {
4056 if(bbu_state[i].u32Used != 0)
4057 {
4058 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
4059 {
4060 retBBUId = i;
4061 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4062 bbu_state[retBBUId].bTSP = bTSP;
4063 return retBBUId;
4064 }
4065 }
4066 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
4067 {
4068 if(i < MAX_MVD_SLQ_COUNT)
4069 {
4070 if(!bTSP) //HVD/EVD first MM case
4071 {
4072 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
4073 {
4074 retBBUId = i;
4075 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4076 bbu_state[retBBUId].bTSP = bTSP;
4077 return retBBUId;
4078 }
4079
4080 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
4081 retBBUId = i;
4082 }
4083 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
4084 {
4085 retBBUId = i;
4086 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4087 bbu_state[retBBUId].bTSP = bTSP;
4088 slq_state[retBBUId].bUsedbyMVD = FALSE;
4089 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4090 slq_state[retBBUId].bTSP = bTSP;
4091 return retBBUId;
4092 }
4093 }
4094 }
4095 }
4096 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4097 {
4098 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4099 bbu_state[retBBUId].bTSP = bTSP;
4100 if(bTSP)
4101 {
4102 slq_state[retBBUId].bUsedbyMVD = FALSE;
4103 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4104 slq_state[retBBUId].bTSP = bTSP;
4105 }
4106 }
4107 }
4108 #endif
4109 return retBBUId;
4110 }
4111
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)4112 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
4113 {
4114 MS_U32 max_bbu_cnt;
4115 BBU_STATE *bbu_state;
4116 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
4117
4118 if(pTaskInfo == NULL)
4119 return FALSE;
4120 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4121 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4122
4123 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4124 /* MS_U32 i;
4125 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4126 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4127
4128 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4129 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
4130
4131 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4132 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
4133 */
4134 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4135 {
4136 // TO DO
4137 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4138 {
4139 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4140 slq_state[u32BBUId].bTSP = FALSE;
4141 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4142 return TRUE;
4143 }
4144 }
4145 #if SUPPORT_G2VP9
4146 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4147 {
4148 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4149 return TRUE;
4150 }
4151 #endif
4152 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4153 {
4154 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4155 return TRUE;
4156 }
4157 else
4158 {
4159 switch (pTaskInfo->eDecType)
4160 {
4161 case E_VPU_EX_DECODER_EVD:
4162 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4163 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4164 break;
4165 case E_VPU_EX_DECODER_HVD:
4166 case E_VPU_EX_DECODER_RVD:
4167 case E_VPU_EX_DECODER_MVC:
4168 default:
4169 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4170 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4171 break;
4172 }
4173
4174 if (u32BBUId < max_bbu_cnt)
4175 {
4176 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4177 bbu_state[u32BBUId].bTSP = FALSE;
4178
4179 if (bTSP)
4180 {
4181 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4182 slq_state[u32BBUId].bTSP = FALSE;
4183 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4184 }
4185
4186 #if 1
4187 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4188 #else
4189 if (bbu_state[u32BBUId].u32Used == 0)
4190 {
4191 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4192 }
4193 #endif
4194
4195 return TRUE;
4196 }
4197 }
4198 return FALSE;
4199 }
4200
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4201 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4202 {
4203 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4204
4205 if (CHECK_NULL_PTR(pstVBBU))
4206 return 0;
4207 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4208 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4209 MS_U32 u32Vacancy = 0;
4210
4211 if (u32WrPtr == u32RdPtr)
4212 {
4213 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4214 }
4215 else if (u32WrPtr > u32RdPtr)
4216 {
4217 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4218 }
4219 else
4220 {
4221 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4222 }
4223
4224 return u32Vacancy;
4225 }
4226
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4227 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4228 {
4229 return MAX_VDEC_VBBU_ENTRY_COUNT;
4230 }
4231
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4232 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4233 {
4234 return pVPUHalContext->u32FWCodeAddr;
4235 }
4236
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4237 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4238 {
4239 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4240 #if SUPPORT_G2VP9
4241 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4242 #endif
4243
4244 if (CHECK_NULL_PTR(pstVBBU))
4245 return FALSE;
4246 MsOS_ReadMemory();
4247 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4248
4249 if(NULL == stEntry)
4250 {
4251 return 0;
4252 }
4253
4254 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4255 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4256 {
4257 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4258 }
4259 else
4260 {
4261 #if SUPPORT_G2VP9
4262 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4263 {
4264 if (stEntry->u32Offset == 0)
4265 return 0;
4266 else
4267 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4268 }
4269 else
4270 #endif
4271 {
4272 return stEntry->u32Offset;
4273 }
4274 }
4275 }
4276
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4277 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4278 {
4279 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4280 VDEC_VBBU_Entry *stEntry;
4281 #if SUPPORT_G2VP9
4282 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4283 #endif
4284
4285 MsOS_ReadMemory();
4286 if (CHECK_NULL_PTR(pstVBBU))
4287 return 0;
4288 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4289
4290 if (u32WrPtr == 0)
4291 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4292 else
4293 u32WrPtr--;
4294
4295 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4296
4297 if(NULL == stEntry)
4298 {
4299 return 0;
4300 }
4301
4302 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4303 #if SUPPORT_G2VP9
4304 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4305 {
4306 if (stEntry->u32Offset == 0)
4307 return 0;
4308 else
4309 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4310 }
4311 else
4312 #endif
4313 {
4314 return stEntry->u32Offset + stEntry->u32Length;
4315 }
4316 }
4317
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4318 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4319 {
4320 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4321 #if SUPPORT_G2VP9
4322 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4323 #endif
4324
4325 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4326 return FALSE;
4327 MsOS_ReadMemory();
4328 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4329 MS_U32 u32NewWrPtr;
4330
4331 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4332 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4333 {
4334 u32NewWrPtr = 0;
4335 }
4336
4337 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4338
4339 stEntry->u32Offset = stVpuPkt->u32Offset;
4340
4341 #if SUPPORT_G2VP9
4342 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4343 {
4344 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4345 }
4346 #endif
4347
4348 stEntry->u32Length = stVpuPkt->u32Length;
4349 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4350 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4351 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4352
4353 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4354
4355 pstVBBU->u32WrPtr = u32NewWrPtr;
4356
4357 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4358
4359 MsOS_FlushMemory();
4360
4361 return TRUE;
4362 }
4363
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4364 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4365 {
4366 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4367
4368 if (CHECK_NULL_PTR(pstVBBU))
4369 return FALSE;
4370 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4371 }
4372
4373 ///-----------------------------------------------------------------------------
4374 /// specify the command send to Mail box or DRAM
4375 /// @return TRUE or FALSE
4376 /// - TRUE, Mail box
4377 /// - FALSE, Dram
4378 /// @param u32Cmd \b IN: Command is going to be sned
4379 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4380 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4381 {
4382 MS_BOOL bResult = TRUE;
4383
4384 switch (u32Cmd)
4385 {
4386 // *********** Runtime action Command
4387 /* case E_HVD_CMD_RELEASE_DISPQ:
4388 case E_HVD_CMD_UPDATE_DISPQ:
4389 case E_HVD_CMD_FLUSH_DEC_Q:
4390 case E_HVD_CMD_FLUSH:
4391 case E_HVD_CMD_PLAY:
4392 case E_HVD_CMD_PAUSE:
4393 case E_HVD_CMD_STOP:
4394 case E_HVD_CMD_STEP_DECODE:
4395 case E_HVD_CMD_SKIP_DEC:
4396 case E_HVD_CMD_DISP_I_DIRECT:*/
4397 // *********** Dual-Stream Create Task Command
4398 case E_DUAL_CMD_TASK0_HVD_BBU:
4399 case E_DUAL_CMD_TASK0_HVD_TSP:
4400 case E_DUAL_CMD_TASK0_MVD_SLQ:
4401 case E_DUAL_CMD_TASK0_MVD_TSP:
4402 case E_DUAL_CMD_TASK1_HVD_BBU:
4403 case E_DUAL_CMD_TASK1_HVD_TSP:
4404 case E_DUAL_CMD_MODE:
4405 #ifndef _WIN32
4406 case E_DUAL_CMD_TASK1_MVD_SLQ:
4407 case E_DUAL_CMD_TASK1_MVD_TSP:
4408 #endif
4409 case E_DUAL_CMD_DEL_TASK:
4410 case E_DUAL_CMD_SINGLE_TASK:
4411 case E_DUAL_VERSION:
4412 case E_DUAL_R2_CMD_EXIT:
4413 case E_DUAL_CMD_STC_MODE:
4414 #ifdef VDEC3
4415 case E_DUAL_R2_CMD_FBADDR:
4416 case E_DUAL_R2_CMD_FBSIZE:
4417 // *********** N-Streams
4418 case E_NST_CMD_TASK_HVD_TSP:
4419 case E_NST_CMD_TASK_HVD_BBU:
4420 case E_NST_CMD_TASK_MVD_TSP:
4421 case E_NST_CMD_TASK_MVD_SLQ:
4422 case E_NST_CMD_DEL_TASK:
4423 case E_NST_CMD_COMMON_MASK:
4424 case E_NST_CMD_COMMON_CMD1:
4425 #endif
4426 case E_DUAL_CMD_COMMON:
4427 {
4428 bResult = TRUE;
4429 }
4430 break;
4431 default:
4432 {
4433 bResult = FALSE;
4434 }
4435 break;
4436 }
4437
4438 return bResult;
4439 }
4440
4441 ///-----------------------------------------------------------------------------
4442 /// specify the command send to Mail box or DRAM
4443 /// @return TRUE or FALSE
4444 /// - TRUE, Mail box
4445 /// - FALSE, Dram
4446 /// @param u32Cmd \b IN: Command is going to be sned
4447 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4448 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4449 {
4450 MS_BOOL bResult = TRUE;
4451
4452 switch (u32Cmd)
4453 {
4454 // *********** Runtime action Command
4455 case E_HVD_CMD_RELEASE_DISPQ:
4456 case E_HVD_CMD_UPDATE_DISPQ:
4457 case E_HVD_CMD_FLUSH_DEC_Q:
4458 case E_HVD_CMD_PAUSE:
4459 case E_HVD_CMD_FLUSH:
4460 case E_HVD_CMD_PLAY:
4461 case E_HVD_CMD_STOP:
4462 case E_HVD_CMD_SKIP_DEC:
4463 case E_HVD_CMD_DISP_I_DIRECT:
4464 case E_HVD_CMD_STEP_DECODE:
4465 case E_HVD_CMD_INC_DISPQ_NUM:
4466 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4467 {
4468 bResult = TRUE;
4469 }
4470 break;
4471 default:
4472 {
4473 bResult = FALSE;
4474 }
4475 break;
4476 }
4477
4478 return bResult;
4479 }
4480
4481 ///-----------------------------------------------------------------------------
4482 /// Send message to HVD stream command queue
4483 /// @return TRUE or FALSE
4484 /// - TRUE, Success
4485 /// - FALSE, Failed
4486 /// @param u32DramAddr \b IN: address to be writen
4487 /// @param u32Msg \b IN: data to be writen
4488 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4489 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4490 {
4491 MS_BOOL bResult = TRUE;
4492
4493 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4494
4495 WRITE_LONG(u32DramAddr,u32Msg);
4496
4497 return bResult;
4498 }
4499
4500 ///-----------------------------------------------------------------------------
4501 /// Read task share memory to specify that task command queue is empty or not
4502 /// @return TRUE or FALSE
4503 /// - TRUE, Empty
4504 /// - FALSE, Non empty
4505 /// @param u32Id \b IN: Task information
4506 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4507 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4508 {
4509 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4510 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4511 if (!cmd_q)
4512 {
4513 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4514 return FALSE;
4515 }
4516
4517 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4518 }
4519
4520 ///-----------------------------------------------------------------------------
4521 /// Read task share memory to specify that task command queue is full or not
4522 /// @return TRUE or FALSE
4523 /// - TRUE, Full
4524 /// - FALSE, Non full
4525 /// @param u32Id \b IN: Task information
4526 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4527 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4528 {
4529 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4530 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4531 if (!cmd_q)
4532 {
4533 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4534 return TRUE;
4535 }
4536 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4537
4538 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4539 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4540
4541 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4542 }
4543
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4544 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4545 {
4546 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4547 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4548 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4549
4550 #if HVD_ENABLE_MVC
4551 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4552 {
4553 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4554 }
4555 #endif
4556
4557 if (CHECK_NULL_PTR(cmd_q))
4558 {
4559 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4560 return bResult;
4561 }
4562 MS_VIRT u32CmdQWdPtr;
4563
4564 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4565 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4566
4567 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4568 return E_HVD_COMMAND_QUEUE_FULL;
4569 else
4570 {
4571 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4572 }
4573
4574 switch (u8CmdType)
4575 {
4576 case E_HVD_CMDQ_CMD:
4577 {
4578 u32Msg |= (u8TaskID << 24);
4579 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4580
4581 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4582
4583 if (bResult)
4584 {
4585 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4586
4587 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4588 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4589
4590 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4591 }
4592 break;
4593 }
4594 case E_HVD_CMDQ_ARG:
4595 {
4596 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4597 if (bResult)
4598 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4599 break;
4600 }
4601 default:
4602 {
4603 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4604 break;
4605 }
4606 }
4607
4608 MsOS_FlushMemory();
4609
4610 return bResult;
4611 }
4612
4613 ///-----------------------------------------------------------------------------
4614 /// Read task share memory to specify that task display command queue is empty or not
4615 /// @return TRUE or FALSE
4616 /// - TRUE, Empty
4617 /// - FALSE, Non empty
4618 /// @param u32Id \b IN: Task information
4619 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4620 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4621 {
4622 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4623 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4624 if (!cmd_q)
4625 {
4626 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4627 return FALSE;
4628 }
4629
4630 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4631 }
4632
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4633 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4634 {
4635 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4636 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4637 if (!cmd_q)
4638 {
4639 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4640 return TRUE;
4641 }
4642
4643 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4644
4645 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4646 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4647
4648 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4649 }
4650
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4651 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4652 {
4653 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4654 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4655 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4656
4657 #if HVD_ENABLE_MVC
4658 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4659 {
4660 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4661 }
4662 #endif
4663
4664 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4665 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4666
4667 if (CHECK_NULL_PTR(cmd_q))
4668 {
4669 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4670 return bResult;
4671 }
4672
4673 MS_VIRT u32DISPCMDQWdPtr;
4674
4675 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4676 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4677
4678 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4679 return E_HVD_COMMAND_QUEUE_FULL;
4680 else
4681 {
4682 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4683 }
4684
4685 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4686
4687 switch (u8CmdType)
4688 {
4689 case E_HVD_CMDQ_CMD:
4690 {
4691 u32Msg |= (u8TaskID << 24);
4692 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4693
4694 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4695
4696 if (bResult)
4697 {
4698 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4699
4700 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4701 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4702
4703 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4704 }
4705 break;
4706 }
4707 case E_HVD_CMDQ_ARG:
4708 {
4709 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4710 if (bResult)
4711 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4712 break;
4713 }
4714 default:
4715 {
4716 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4717 break;
4718 }
4719 }
4720
4721 MsOS_FlushMemory();
4722
4723 return bResult;
4724 }
4725
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4726 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4727 {
4728 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4729 MS_U32 u32StAddr;
4730 MS_U8 u8TmpMiuSel;
4731
4732 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4733
4734 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4735
4736 return TRUE;
4737 }
4738 #endif
4739
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4740 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4741 {
4742 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4743
4744 if(u32address >= HAL_MIU1_BASE)
4745 {
4746 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4747 }
4748 else
4749 {
4750 pVPUHalContext->u32DynamicFBAddress = u32address;
4751 }
4752
4753 pVPUHalContext->u32DynamicFBSize = u32Size;
4754 }
4755
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4756 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4757 {
4758 MS_SIZE FrameBufferSize = 0;
4759
4760 switch(eCodecType)
4761 {
4762 case E_VPU_EX_CODEC_TYPE_MPEG2:
4763 case E_VPU_EX_CODEC_TYPE_H263:
4764 case E_VPU_EX_CODEC_TYPE_MPEG4:
4765 case E_VPU_EX_CODEC_TYPE_DIVX311:
4766 case E_VPU_EX_CODEC_TYPE_DIVX412:
4767 case E_VPU_EX_CODEC_TYPE_FLV:
4768 FrameBufferSize = 0x1E00000;
4769 break;
4770 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4771 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4772 FrameBufferSize = 0x6C00000;
4773 break;
4774 case E_VPU_EX_CODEC_TYPE_RV8:
4775 case E_VPU_EX_CODEC_TYPE_RV9:
4776 FrameBufferSize = 0x1B00000;
4777 break;
4778 case E_VPU_EX_CODEC_TYPE_VP8:
4779 FrameBufferSize = 0x1500000;
4780 break;
4781 case E_VPU_EX_CODEC_TYPE_H264:
4782 FrameBufferSize = 0x8200000;
4783 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4784 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4785 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4786 break;
4787 case E_VPU_EX_CODEC_TYPE_AVS:
4788 #if VPU_FIELD_DETECTOR
4789 FrameBufferSize = 0x3600000;
4790 #else
4791 FrameBufferSize = 0x1B00000;
4792 #endif
4793 break;
4794 case E_VPU_EX_CODEC_TYPE_MJPEG:
4795 FrameBufferSize = 0x2800000;
4796 break;
4797 case E_VPU_EX_CODEC_TYPE_MVC:
4798 FrameBufferSize = 0x4200000;
4799 break;
4800 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4801 FrameBufferSize = 0xB000000;
4802 break;
4803 case E_VPU_EX_CODEC_TYPE_HEVC:
4804 #if SUPPORT_MSVP9
4805 case E_VPU_EX_CODEC_TYPE_VP9:
4806 #endif
4807 FrameBufferSize = 0xA000000;
4808 break;
4809 #if !SUPPORT_MSVP9
4810 case E_VPU_EX_CODEC_TYPE_VP9:
4811 FrameBufferSize = 0x7800000;
4812 break;
4813 #endif
4814 default:
4815 FrameBufferSize = 0;
4816 break;
4817 }
4818
4819 return FrameBufferSize;
4820 }
4821
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4822 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4823 {
4824 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4825 }
4826
4827 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4828 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4829 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4830 {
4831 MS_SIZE FrameBufferSize = 0;
4832
4833 if (!offset || !length)
4834 return FALSE;
4835
4836 total_length -= unUseSize;
4837 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4838 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4839
4840 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4841
4842 if(FrameBufferSize == 0)
4843 {
4844 return FALSE;
4845 }
4846 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4847 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4848 if (total_length < FrameBufferSize)
4849 {
4850 *offset = unUseSize;
4851 *length = total_length;
4852 }
4853 else // todo, dual decode case
4854 {
4855 *offset = unUseSize;
4856 *length = FrameBufferSize;
4857 }
4858 return TRUE;
4859 }
4860
4861 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4862 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4863 {
4864 MS_S32 handle;
4865 switch(eClkPortType)
4866 {
4867 case E_VPU_EX_CLKPORT_MVD:
4868 {
4869 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4870 if(bEnable)
4871 {
4872 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4873 }
4874 else
4875 {
4876 Drv_Clkm_Clk_Gate_Disable(handle);
4877 }
4878 break;
4879 }
4880 case E_VPU_EX_CLKPORT_MVD_CORE:
4881 {
4882 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4883 if(bEnable)
4884 {
4885 Drv_Clkm_Set_Clk_Source(handle, "");
4886 }
4887 else
4888 {
4889 Drv_Clkm_Clk_Gate_Disable(handle);
4890 }
4891 break;
4892 }
4893 case E_VPU_EX_CLKPORT_MVD_PAS:
4894 {
4895 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4896 if(bEnable)
4897 {
4898 Drv_Clkm_Set_Clk_Source(handle, "");
4899 }
4900 else
4901 {
4902 Drv_Clkm_Clk_Gate_Disable(handle);
4903 }
4904 break;
4905 }
4906 case E_VPU_EX_CLKPORT_HVD:
4907 {
4908 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4909 if(bEnable)
4910 {
4911 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4912 }
4913 else
4914 {
4915 Drv_Clkm_Clk_Gate_Disable(handle);
4916 }
4917 break;
4918 }
4919 case E_VPU_EX_CLKPORT_HVD_IDB:
4920 {
4921 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4922 if(bEnable)
4923 {
4924 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4925 }
4926 else
4927 {
4928 Drv_Clkm_Clk_Gate_Disable(handle);
4929 }
4930 break;
4931 }
4932 case E_VPU_EX_CLKPORT_HVD_AEC:
4933 {
4934 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4935 if(bEnable)
4936 {
4937 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4938 }
4939 else
4940 {
4941 Drv_Clkm_Clk_Gate_Disable(handle);
4942 }
4943 break;
4944 }
4945 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4946 {
4947 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4948 if(bEnable)
4949 {
4950 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4951 }
4952 else
4953 {
4954 Drv_Clkm_Clk_Gate_Disable(handle);
4955 }
4956 break;
4957 }
4958 case E_VPU_EX_CLKPORT_VP8:
4959 {
4960 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4961 if(bEnable)
4962 {
4963 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4964 }
4965 else
4966 {
4967 Drv_Clkm_Clk_Gate_Disable(handle);
4968 }
4969 break;
4970 }
4971 case E_VPU_EX_CLKPORT_EVD:
4972 {
4973 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4974 if(bEnable)
4975 {
4976 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4977 }
4978 else
4979 {
4980 Drv_Clkm_Clk_Gate_Disable(handle);
4981 }
4982 break;
4983 }
4984 case E_VPU_EX_CLKPORT_EVD_PPU:
4985 {
4986 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4987 if(bEnable)
4988 {
4989 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4990 }
4991 else
4992 {
4993 Drv_Clkm_Clk_Gate_Disable(handle);
4994 }
4995 break;
4996 }
4997 case E_VPU_EX_CLKPORT_EVD_LITE:
4998 {
4999 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
5000 if(bEnable)
5001 {
5002 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
5003 }
5004 else
5005 {
5006 Drv_Clkm_Clk_Gate_Disable(handle);
5007 }
5008 break;
5009 }
5010 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
5011 {
5012 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
5013 if(bEnable)
5014 {
5015 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
5016 }
5017 else
5018 {
5019 Drv_Clkm_Clk_Gate_Disable(handle);
5020 }
5021 break;
5022 }
5023 case E_VPU_EX_CLKPORT_VD_MHEG5:
5024 {
5025 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
5026 if(bEnable)
5027 {
5028 Drv_Clkm_Set_Clk_Source(handle, "");
5029 }
5030 else
5031 {
5032 Drv_Clkm_Clk_Gate_Disable(handle);
5033 }
5034 break;
5035 }
5036 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
5037 {
5038 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
5039 if(bEnable)
5040 {
5041 Drv_Clkm_Set_Clk_Source(handle, "");
5042 }
5043 else
5044 {
5045 Drv_Clkm_Clk_Gate_Disable(handle);
5046 }
5047 break;
5048 }
5049 }
5050 }
5051 #endif //#ifdef CONFIG_MSTAR_CLKM
5052
HAL_VPU_EX_strcmp(const char * string1,const char * string2)5053 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
5054 {
5055 int iRet, i;
5056
5057 i = 0;
5058 while(string1[i] || string2[i])
5059 {
5060 iRet = string1[i] - string2[i];
5061 if(iRet)
5062 {
5063 return iRet;
5064 }
5065 i++;
5066 }
5067 return 0;
5068 }
5069
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)5070 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
5071 {
5072 typedef enum
5073 {
5074 E_CAP_NDEC_FB_MIU_SELECT,
5075 E_CAP_NDEC_NSTREAM_FB_SIZE,
5076 E_CAP_NDEC_NSTREAM_BS_SIZE,
5077 E_CAP_NDEC_SUPPORT_SHAREBBU,
5078 E_CAP_SUPPORT_ALLOCATOR,
5079
5080 } VPU_EX_GetCapabilityCmdId;
5081
5082 typedef struct
5083 {
5084 VPU_EX_GetCapabilityCmdId eCmdId;
5085 MS_U8 u8CmdName[32];
5086
5087 } VPU_EX_GetCapabilityCmd;
5088
5089 static VPU_EX_GetCapabilityCmd stCapCmd[] =
5090 {
5091 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
5092 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
5093 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
5094 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
5095 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
5096 };
5097
5098 MS_U32 bRet = FALSE;
5099 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
5100 MS_U32 u32CmdCnt;
5101
5102 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
5103 {
5104 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
5105 {
5106 bRet = TRUE;
5107 switch(stCapCmd[u32CmdCnt].eCmdId)
5108 {
5109 case E_CAP_NDEC_FB_MIU_SELECT:
5110 {
5111 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5112 *pSupport = FALSE;
5113 }
5114 break;
5115
5116 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
5117 case E_CAP_NDEC_NSTREAM_FB_SIZE:
5118 {
5119 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5120 *pSize = 0;
5121 }
5122 break;
5123
5124 // FIXME: Patch for waiting dynamic bitstream buffer
5125 case E_CAP_NDEC_NSTREAM_BS_SIZE:
5126 {
5127 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5128 *pSize = 0;
5129 }
5130 break;
5131
5132 case E_CAP_NDEC_SUPPORT_SHAREBBU:
5133 {
5134 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
5135 *pbSupportShareBBU = FALSE;
5136 }
5137 break;
5138
5139 case E_CAP_SUPPORT_ALLOCATOR:
5140 {
5141 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5142 *pSupport = FALSE;
5143 }
5144 break;
5145
5146 default:
5147 bRet = FALSE;
5148 break;
5149 }
5150 }
5151 }
5152
5153 return bRet;
5154 }
5155
5156 #else
5157 #include "halVPU_EX.h"
5158 #include "drvMMIO.h"
5159 #include "../../../../vdec_v2/hal/maserati/hvd_ex/regHVD_EX.h"
5160 #include "halCHIP.h"
5161
5162 #if defined(MSOS_TYPE_NUTTX)
5163 extern int lib_lowprintf(const char *fmt, ...);
5164 #define PRINTF lib_lowprintf
5165 #elif defined(MSOS_TYPE_OPTEE)
5166 #define PRINTF printf
5167 #endif
5168
5169 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5170 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5171
5172 MS_U8 u8FW_Binary[] = {
5173 #include "fwVPU.dat"
5174 };
5175
5176 MS_U32 u32HVDRegOSBase;
5177
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5178 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5179 {
5180 //PRINTF("do load code,u32DestAddr %x\n",addr);
5181 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5182 MAsm_CPU_Sync();
5183 MsOS_FlushMemory();
5184
5185 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5186 {
5187 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5188 return FALSE;
5189 }
5190 return TRUE;
5191 }
5192
HAL_VPU_EX_SetLockDownRegister(void * param)5193 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5194 {
5195 #if 1
5196 MS_PHY u32StAddr_main;
5197 MS_PHY u32StAddr_sub;
5198 MS_U32 u32NonPMBankSize = 0;
5199 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5200
5201 if(param == NULL)
5202 {
5203 return FALSE;
5204 }
5205
5206 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5207
5208 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5209
5210 // ES buffer
5211 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5212 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5213
5214
5215 MS_PHY u32StartOffset;
5216 MS_U8 u8MiuSel;
5217
5218 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5219 u32StAddr_main = u32StartOffset;
5220
5221 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5222 u32StAddr_sub = u32StartOffset;
5223
5224 //Lock down register
5225 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5226 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5227
5228 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
5229 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
5230 //~
5231
5232 // Lock Down
5233 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5234 //~
5235 #endif
5236 return TRUE;
5237 }
5238 #endif
5239