xref: /utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/halVPU_EX.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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////////////////////////////////////////////////////////////////////////////////


//-------------------------------------------------------------------------------------------------
//  Include Files
//-------------------------------------------------------------------------------------------------
// Common Definition
#include <string.h>

#if defined(REDLION_LINUX_KERNEL_ENVI)
#include "drvHVD_Common.h"
#else
#include "MsCommon.h"
#endif

#include "MsOS.h"
#include "asmCPU.h"


#ifndef MSOS_TYPE_NUTTX

// Internal Definition
#include "regVPU_EX.h"
#include "halVPU_EX.h"
#include "halCHIP.h"
#include "../../../drv/hvd_ex/drvHVD_def.h"
#include "controller.h"

#include "../hvd_ex/fwHVD_if.h"
#include "../mvd_ex/mvd4_interface.h"
#include "../hvd_ex/halHVD_EX.h"
#if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
#include "ms_decompress.h"
#include "ms_decompress_priv.h"
#endif
#include "../../drv/mbx/apiMBX_St.h"
#include "../../drv/mbx/apiMBX.h"

#if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
#include "drvSERFLASH.h"
#define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag)  MDrv_SERFLASH_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
#endif

//-------------------------------------------------------------------------------------------------
//  Driver Compiler Options
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Local Defines
//-------------------------------------------------------------------------------------------------
#define ENABLE_TEE 0
#define VPU_CTL_INTERFACE_VER   0x00000001  //the interface version of VPU driver

#define VPU_MIU1BASE_ADDR    0x40000000     //Notice: this define must be comfirm with designer
#define MAX_SUPPORT_DECODER_NUM 2
typedef enum
{
    E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
    E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
    E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
} VDEC_REE_TO_TEE_MBX_MSG_TYPE;


typedef enum
{
    E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
    E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
    E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
    E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
    E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
} VDEC_TEE_TO_REE_MBX_ACK_TYPE;

typedef enum
{
    E_VPU_UART_CTRL_DISABLE = BIT(4),
    E_VPU_UART_CTRL_ERR     = BIT(0),
    E_VPU_UART_CTRL_INFO    = BIT(1),
    E_VPU_UART_CTRL_DBG     = BIT(2),
    E_VPU_UART_CTRL_FW      = BIT(3),
    E_VPU_UART_CTRL_MUST    = BIT(4),
    E_VPU_UART_CTRL_TRACE   = BIT(5),
} VPU_EX_UartCtrl;

typedef struct
{
    HAL_VPU_StreamId eStreamId;
    VPU_EX_DecoderType eDecodertype;
} VPU_EX_Stream;


#ifndef ANDROID
#define VPU_PRINT  printf
#define VPU_ERR printf
#else
#include <sys/mman.h>
#include <cutils/ashmem.h>
#include <cutils/log.h>
#ifndef LOGI // android 4.1 rename LOGx to ALOGx
#define VPU_PRINT ALOGI
#else
#define VPU_PRINT LOGI
#endif
#ifndef LOGE // android 4.1 rename LOGx to ALOGx
#define VPU_ERR ALOGE
#else
#define VPU_ERR LOGE
#endif
#endif


#define VPU_MSG_ERR(format, args...)                \
    do                                              \
    {                                               \
        if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR)  \
        {                                           \
            VPU_ERR("[VPU][ERR]%s:", __FUNCTION__);  \
            VPU_ERR(format, ##args);                 \
        }                                           \
    } while (0)

#define VPU_MSG_DBG(format, args...)                \
    do                                              \
    {                                               \
        if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG)  \
        {                                           \
            VPU_ERR("[VPU][DBG]%s:", __FUNCTION__);  \
            VPU_ERR(format, ##args);                 \
        }                                           \
    } while (0)

#define VPU_MSG_INFO(format, args...)               \
    do                                              \
    {                                               \
        if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
        {                                           \
            VPU_ERR("[VPU][INF]%s:", __FUNCTION__);  \
            VPU_ERR(format, ##args);                 \
        }                                           \
    } while (0)

//------------------------------ MIU SETTINGS ----------------------------------
#define _MaskMiuReq_VPU_D_RW(m)     _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
#define _MaskMiuReq_VPU_Q_RW(m)     _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
#define _MaskMiuReq_VPU_I_R(m)      _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))

#define _MaskMiu1Req_VPU_D_RW(m)    _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
#define _MaskMiu1Req_VPU_Q_RW(m)    _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
#define _MaskMiu1Req_VPU_I_R(m)     _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))

#define VPU_D_RW_ON_MIU1            ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
#define VPU_Q_RW_ON_MIU1            ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
#define VPU_I_R_ON_MIU1             ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08

#define _VPU_MIU_SetReqMask(miu_clients, mask)  \
   do {                                         \
       if (miu_clients##_ON_MIU1 == 0)          \
           _MaskMiuReq_##miu_clients(mask);     \
       else                                     \
           _MaskMiu1Req_##miu_clients(mask);    \
   } while(0)

#if ENABLE_VPU_MUTEX_PROTECTION
static MS_S32 s32VPUMutexID = -1;
static const MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };

#define _HAL_VPU_MutexCreate()  \
    if (s32VPUMutexID < 0)      \
    {                           \
        s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
    }

#define _HAL_VPU_MutexDelete()              \
    if (s32VPUMutexID >= 0)                 \
    {                                       \
        MsOS_DeleteMutex(s32VPUMutexID);    \
        s32VPUMutexID = -1;                 \
    }

#define _HAL_VPU_Entry()                                                \
    if (s32VPUMutexID >= 0)                                             \
    {                                                                   \
        if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT))       \
        {                                                               \
            VPU_PRINT("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
        }                                                               \
    }

#define _HAL_VPU_Return(_ret)                   \
    {                                           \
        if (s32VPUMutexID >= 0)                 \
        {                                       \
            MsOS_ReleaseMutex(s32VPUMutexID);   \
        }                                       \
        return _ret;                            \
    }

#define _HAL_VPU_Release()                      \
    {                                           \
        if (s32VPUMutexID >= 0)                 \
        {                                       \
            MsOS_ReleaseMutex(s32VPUMutexID);   \
        }                                       \
    }
#else
#define _HAL_VPU_MutexCreate()
#define _HAL_VPU_MutexDelete()
#define _HAL_VPU_Entry()
#define _HAL_VPU_Return(_ret)       {return _ret;}
#define _HAL_VPU_Release()
#endif

#define VPU_FW_MEM_OFFSET   0x100000UL  // 1M
#define VPU_CMD_TIMEOUT     1000 // 1 sec

//-------------------------------------------------------------------------------------------------
//  Local Structures
//-------------------------------------------------------------------------------------------------
typedef struct _VPU_HWInitFunc
{
    MS_BOOL (*pfMVDHW_Init)(void);
    MS_BOOL (*pfMVDHW_Deinit)(void);
    MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
    MS_BOOL (*pfHVDHW_Deinit)(void);
} VPU_HWInitFunc;

typedef struct
{
    MS_U32  u32ApiHW_Version;   //<Version of current structure>
    MS_U16  u16ApiHW_Length;    //<Length of this structure>

    MS_U8   u8Cap_Support_Decoder_Num;

    MS_BOOL bCap_Support_MPEG2;
    MS_BOOL bCap_Support_H263;
    MS_BOOL bCap_Support_MPEG4;
    MS_BOOL bCap_Support_DIVX311;
    MS_BOOL bCap_Support_DIVX412;
    MS_BOOL bCap_Support_FLV;
    MS_BOOL bCap_Support_VC1ADV;
    MS_BOOL bCap_Support_VC1MAIN;

    MS_BOOL bCap_Support_RV8;
    MS_BOOL bCap_Support_RV9;
    MS_BOOL bCap_Support_H264;
    MS_BOOL bCap_Support_AVS;
    MS_BOOL bCap_Support_AVS_PLUS;
    MS_BOOL bCap_Support_MJPEG;
    MS_BOOL bCap_Support_MVC;
    MS_BOOL bCap_Support_VP8;
    MS_BOOL bCap_Support_VP9;
    MS_BOOL bCap_Support_HEVC;

    /*New HW Cap and Feature add in struct at the end*/
}VDEC_HwCap;

//-------------------------------------------------------------------------------------------------
//  Local Functions Prototype
//-------------------------------------------------------------------------------------------------
static MS_BOOL          _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
static MS_U8            _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
static HVD_User_Cmd     _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);

//-------------------------------------------------------------------------------------------------
//  Global Variables
//-------------------------------------------------------------------------------------------------
extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
extern MS_BOOL HAL_MVD_InitHW(void);
extern MS_BOOL HAL_MVD_DeinitHW(void);
extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
extern MS_BOOL HAL_HVD_EX_DeinitHW(void);
extern void    HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);

#if defined (__aeon__)
static MS_U32 u32VPURegOSBase = 0xA0000000;
#else
static MS_U32 u32VPURegOSBase = 0xBF200000;
#endif

//-------------------------------------------------------------------------------------------------
//  Local Variables
//-------------------------------------------------------------------------------------------------
#if 0

static MS_BOOL _bVPUPowered = FALSE;
static MS_BOOL _bVPURsted = FALSE;
static MS_BOOL _bVPUSingleMode = FALSE;
static VPU_EX_DecModCfg _stVPUDecMode;

static MS_U8 u8TaskCnt = 0;

static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);

//Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
static VPU_EX_Stream _stVPUStream[] =
{
    {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
    {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
};
static VPU_HWInitFunc stHWInitFunc =
{
    &HAL_MVD_InitHW,
    &HAL_MVD_DeinitHW,
    &HAL_HVD_EX_InitHW,
    &HAL_HVD_EX_DeinitHW,
};

#endif

#if VPU_ENABLE_EMBEDDED_FW_BINARY
static const MS_U8 u8HVD_FW_Binary[] = {
    #include "fwVPU.dat"
};

#if HVD_ENABLE_RV_FEATURE
static const MS_U8 u8HVD_VLC_Binary[] = {
    #include "fwVPU_VLC.dat"
};
#endif
#endif

typedef struct
{
    MS_BOOL _bVPUPowered;
    MS_BOOL _bVPURsted;
    MS_BOOL _bVPUSingleMode;
    VPU_EX_DecModCfg _stVPUDecMode;
    MS_U8 u8TaskCnt;
    //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
    VPU_EX_Stream _stVPUStream[2];

    VPU_HWInitFunc stHWInitFunc;

    MS_BOOL bVpuExReloadFW;
    MS_BOOL bVpuExLoadFWRlt;
    MS_U32  u32VPUSHMAddr;    //PA
    MS_BOOL bEnableVPUSecureMode;

    MS_U32  u32FWShareInfoAddr[4];
} VPU_Hal_CTX;

//global variables
VPU_Hal_CTX* pVPUHalContext = NULL;
VPU_Hal_CTX gVPUHalContext;
MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
#if ENABLE_TEE
MS_BOOL bVPUMbxInitFlag = 0;
MS_U8 u8VPUMbxMsgClass = 0;
MBX_Msg VPUReeToTeeMbxMsg;
MBX_Msg VPUTeeToReeMbxMsg;
#endif
//-------------------------------------------------------------------------------------------------
//  Debug Functions
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Local Functions
//-------------------------------------------------------------------------------------------------

static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
{
#if HVD_ENABLE_RV_FEATURE
    if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
    {
#if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
        VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
            pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);

        if (pVlcCfg->u32BinSize)
        {
            SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;

            if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32FrameBufAddr))
            {
                cpyflag = E_SPIDMA_DEV_MIU1;
            }
            else
            {
                cpyflag = E_SPIDMA_DEV_MIU0;
            }

            if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
            {
                VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
                     pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);

                return FALSE;
            }
        }
        else
        {
            VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
            return FALSE;
        }
#else
        VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
        return FALSE;
#endif
    }
    else
    {
        if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
        {
            if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
            {
                VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
                            pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);

#if HVD_ENABLE_BDMA_2_BITSTREAMBUF
                BDMA_Result bdmaRlt;
                MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;

                u32DstAdd   = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
                u32SrcAdd   = pVlcCfg->u32BinAddr;
                u32tabsize  = pVlcCfg->u32BinSize;
                //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
                MsOS_FlushMemory();
                bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);

                if (E_BDMA_OK != bdmaRlt)
                {
                    VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
                }
#else
                HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
#endif
            }
            else
            {
                VPU_MSG_ERR
                    ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
                return FALSE;
            }
        }
        else
        {
#if VPU_ENABLE_EMBEDDED_FW_BINARY
#ifdef HVD_CACHE_TO_UNCACHE_CONVERT
            MS_U8 *pu8HVD_VLC_Binary;

            pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);

            VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
                        pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
                        (MS_U32) sizeof(u8HVD_VLC_Binary));

            HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
                       (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
#else
            VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
                        MsOS_VA2PA(pVlcCfg->u32DstAddr), (MS_U32) u8HVD_VLC_Binary,
                        (MS_U32) sizeof(u8HVD_VLC_Binary));

            HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_U32) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
#endif
#else
            VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
            return FALSE;
#endif
        }
    }
#endif

    return TRUE;
}

//Notice: this function must be consistent with _stVPUStream[]
static MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
{
    MS_U8 u8OffsetIdx = 0;
    MS_U8 u8VSidBaseMask = 0xF0;
    HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);

    switch (eVSidBase)
    {
        case E_HAL_VPU_MAIN_STREAM_BASE:
        {
            u8OffsetIdx = 0;
            break;
        }
        case E_HAL_VPU_SUB_STREAM_BASE:
        {
            u8OffsetIdx = 1;
            break;
        }
        case E_HAL_VPU_MVC_STREAM_BASE:
        {
            u8OffsetIdx = 0;
            break;
        }
        default:
        {
            u8OffsetIdx = 0;
            break;
        }
    }

    /*
    VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
        u32Id, eVSidBase, u8OffsetIdx);
        */
    return u8OffsetIdx;
}

static void _VPU_EX_Context_Init(void)
{
    pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
    pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
    pVPUHalContext->bVpuExReloadFW = TRUE;

    pVPUHalContext->u32FWShareInfoAddr[0] = 0xFFFFFFFF;
    pVPUHalContext->u32FWShareInfoAddr[1] = 0xFFFFFFFF;
    pVPUHalContext->u32FWShareInfoAddr[2] = 0xFFFFFFFF;
    pVPUHalContext->u32FWShareInfoAddr[3] = 0xFFFFFFFF;
}


static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
{
    HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
    MS_U8 u8OffsetIdx = 0;

    if (NULL == pTaskInfo)
    {
        return eCmd;
    }

    u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);

    VPU_MSG_INFO("input TaskInfo u32Id=0x%08lx eVpuId=0x%x src=0x%x dec=0x%x\n",
         pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);

    if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
    {
        if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
        {
            eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
        }
        else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
        {
            eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
        }
    }
    else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
    {
        if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
        {
            eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
        }
        else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
        {
            eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
        }
    }

    VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
    return eCmd;
}

static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
{
    if (!pTaskInfo)
    {
        VPU_MSG_ERR("null input\n");
        return FALSE;
    }

    //Check if we need to init MVD HW
    if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
        (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
    {
        //Init HW
        if (FALSE == HAL_VPU_EX_MVDInUsed())
        {
            if (TRUE != HAL_MVD_InitHW())
            {
                VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
                return FALSE;
            }
        }
        else
        {
            VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
        }
    }

    //MVD use sub mvop
    if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
        (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId) &&
        (E_VPU_DEC_MODE_DUAL_INDIE ==pVPUHalContext->_stVPUDecMode.u8DecMod))
    {
        VPU_MSG_ERR("Force turn on HVD\n");
        if(!HAL_VPU_EX_HVDInUsed())
        {
            if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
            {
                 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
                 return FALSE;
            }
        }
        else
        {
            VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
        }
    }

    //Check if we need to init HVD HW
    if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
    {
        if (!HAL_VPU_EX_MVDInUsed())
        {
            if (!HAL_MVD_InitHW())
            {
                VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
                return FALSE;
            }
        }

        if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
        {
            VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
            return FALSE;
        }
    }

    return TRUE;
}

static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
{
    switch (u32type)
    {
        case VPU_CLOCK_240MHZ:
            return 240000000UL;
        case VPU_CLOCK_216MHZ:
            return 216000000UL;
        case VPU_CLOCK_192MHZ:
            return 192000000UL;
        case VPU_CLOCK_320MHZ:
            return 320000000UL;
        case VPU_CLOCK_288MHZ:
            return 288000000UL;
        default:
            return 240000000UL;
    }
}

#if defined(MSOS_TYPE_LINUX)
//For REE
MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
{

#if ENABLE_TEE
    MS_U8 ClassNum = 0;
    MBX_Result result;

    if (bVPUMbxInitFlag == TRUE)
    {
        return TRUE;
    }

    if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
    {
        VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
        return FALSE;
    }
    else
    {
        MApi_MBX_Enable(TRUE);
    }

    if (E_MBX_SUCCESS != MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum))
    {
        VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail\n");
        return FALSE;
    }

    result = MApi_MBX_RegisterMSG(ClassNum, 10);

    if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
    {
        VPU_MSG_ERR("%s fail\n",__FUNCTION__);
        return FALSE;
    }
    else
    {
        bVPUMbxInitFlag = TRUE;
        u8VPUMbxMsgClass = ClassNum;
        return TRUE;
    }
#else
    return FALSE;
#endif
}
#if ENABLE_TEE
VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
{
    MBX_Result result;
    MS_U8 u8Index;

    if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
    {
        return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
    }

    if (bVPUMbxInitFlag == FALSE)
    {
        return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
    }

    VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
    VPUReeToTeeMbxMsg.u8Ctrl = 0;
    VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
    VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
    VPUReeToTeeMbxMsg.u8Index = msg_type;

    result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
    if (E_MBX_SUCCESS != result)
    {
        return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
    }

    // Receive Reply ACK from TEE side.
    memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));

    VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;

#if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
    if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
    {
        VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
        return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
    }
    else
#else
    do
    {
        result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
    } while(E_MBX_SUCCESS != result);
#endif
    {
        u8Index = VPUTeeToReeMbxMsg.u8Index;
        VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);

        if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
        {
            return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
        }
    }

    return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
}
#endif


MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void)
{
#if ENABLE_TEE
    if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
    {
        VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
        return FALSE;
    }
    else
    {
        MS_U32 u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
                                 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
                                 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
                                 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
        MS_U32 u32VPUSHMsize =   (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
                                 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
                                 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
                                 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);

        VPU_MSG_INFO("u32VPUSHMoffset %x,u32VPUSHMsize %x,miu %d\n",(unsigned int)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
        if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
        {
            pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset+HAL_MIU1_BASE;
        }
        else
        {
            pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
        }
    }
    return TRUE;
#else
    return FALSE;
#endif
}

#endif

MS_BOOL HAL_VPU_EX_GetFWReload(void)
{
    return pVPUHalContext->bVpuExReloadFW;
}

static MS_BOOL _VPU_EX_IsNeedDecompress(MS_U32 u32SrcAddr)
{
    if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
        && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
        && *((MS_U8*)(u32SrcAddr+4))=='2' && *((MS_U8*)(u32SrcAddr+5))=='0'
        && *((MS_U8*)(u32SrcAddr+0x88))=='V' && *((MS_U8*)(u32SrcAddr+0x89))=='D'
        && *((MS_U8*)(u32SrcAddr+0x8a))=='E' && *((MS_U8*)(u32SrcAddr+0x8b))=='C'
        && *((MS_U8*)(u32SrcAddr+0x8c))=='2' && *((MS_U8*)(u32SrcAddr+0x8d))=='0'
        )
    {
        return FALSE;
    }
    else
    {
        return TRUE;
    }
}

static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
{
    MS_U32 u32fwPA = NULL;  //physical address
    VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_240MHZ;

    if (TRUE == HAL_VPU_EX_IsPowered())
    {
        VPU_MSG_DBG("IsPowered\n");
        return TRUE;
    }
    else
    {
        //VPU hold
        HAL_VPU_EX_SwRst(FALSE);

        //VPU clock on
        VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
        VPUInitParams.bInMIU1 = VPU_I_R_ON_MIU1;

        HAL_VPU_EX_Init(&VPUInitParams);
    }

    VPU_EX_FWCodeCfg *pFWCodeCfg   = NULL;
    VPU_EX_TaskInfo  *pTaskInfo    = NULL;
    VPU_EX_VLCTblCfg *pVlcCfg      = NULL;

    if (pInitPara)
    {
        pFWCodeCfg  = pInitPara->pFWCodeCfg;
        pTaskInfo   = pInitPara->pTaskInfo;
        pVlcCfg     = pInitPara->pVLCCfg;
    }
    else
    {
        VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
        return FALSE;
    }

    u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
#if ENABLE_TEE
#if defined(MSOS_TYPE_LINUX)
    if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
    {
        VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");

        if (FALSE == HAL_VPU_EX_GetFWReload())
        {
            if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
            {
                VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
                if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
                {
                    VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
                    return FALSE;
                }
                pVPUHalContext->bVpuExLoadFWRlt = TRUE;
            }
            else
            {
                //Check f/w prefix "VDEC20"
                if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
                {
                    VPU_MSG_ERR("Wrong prefix: reload fw!\n");
                    if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
                    {
                        VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
                        pVPUHalContext->bVpuExLoadFWRlt = FALSE;
                        return FALSE;
                    }
                }
                else
                {
                    VPU_MSG_INFO("Skip loading fw this time!!!\n");
                }
            }
        }
        else
        {
            if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
            {
                VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
                pVPUHalContext->bVpuExLoadFWRlt = FALSE;
                return FALSE;
            }
            pVPUHalContext->bVpuExLoadFWRlt = TRUE;
        }
    }
    else
#endif
#endif
    {
        VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");

        if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
        {
            VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
            return FALSE;
        }
    }

    if (pVlcCfg)
    {
        if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
        {
            VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
            return FALSE;
        }
    }

    if (!HAL_VPU_EX_CPUSetting(u32fwPA))
    {
        VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
        return FALSE;
    }

    //Init HW
    if (FALSE == _VPU_EX_InitHW(pTaskInfo))
    {
        VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
        //_MVD_INIT_FAIL_RET();
        return FALSE;
    }
    else
    {
        VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
    }

    //set vpu clock to FW
    struct _ctl_info *ctl_ptr = (struct _ctl_info *)
                    MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);

    ctl_ptr->statue = CTL_STU_NONE;
    //notify controller the interface version of VPU driver.
    ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
    ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
    MsOS_FlushMemory();
    VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);

    //Release VPU: For dual decoder, we only release VPU if it is not released yet.
    if (TRUE == HAL_VPU_EX_IsRsted())
    {
        VPU_MSG_DBG("VPU_IsRsted\n");
        return TRUE;
    }
    else
    {
        HAL_VPU_EX_SwRstRelse();
    }

    return TRUE;
}

static MS_BOOL _VPU_EX_DeinitHW(void)
{
    MS_BOOL bRet = FALSE;

    if (FALSE == HAL_VPU_EX_MVDInUsed())
    {
        bRet = HAL_MVD_DeinitHW();
    }

    if (FALSE == HAL_VPU_EX_HVDInUsed())
    {
        bRet = HAL_HVD_EX_DeinitHW();
    }

    return bRet;
}

static MS_BOOL _VPU_EX_DeinitAll(void)
{
    HAL_VPU_EX_SwRst(TRUE);
    _VPU_EX_DeinitHW();
    HAL_VPU_EX_DeInit();

    return TRUE;
}

static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
{
    MS_U32 i;
    MS_U8  u8ActiveCnt = 0;
    for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
    {
        if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype)
        {
            u8ActiveCnt++;
        }
    }
    if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
    {
        VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
    }
    VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
    return u8ActiveCnt;
}
static void _VPU_EX_ClockInv(MS_BOOL bEnable)
{
    if (TRUE)
    {
        _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
    }
    else
    {
        _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
    }
}

static void _VPU_EX_ClockSpeed(MS_U32 u32type)
{
    switch (u32type)
    {
        case VPU_CLOCK_240MHZ:
        case VPU_CLOCK_216MHZ:
        case VPU_CLOCK_192MHZ:
        case VPU_CLOCK_320MHZ:
        case VPU_CLOCK_288MHZ:
            _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
            break;
        default:
            _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_240MHZ, TOP_CKG_VPU_CLK_MASK);
            break;
    }
}

static MS_BOOL _VPU_EX_MAU_IDLE(void)
{
    if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
        && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
    {
        return TRUE;
    }
    return FALSE;
}


#if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
static MS_BOOL _VPU_EX_DecompressBin(MS_U32 u32SrcAddr, MS_U32 u32SrcSize, MS_U32 u32DestAddr, MS_U32 u32SlidingAddr)
{
    if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
    {
        ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
        ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
        ms_VDECDecompressDeInit();
        return TRUE;
    }
    else
    {
        return FALSE;
    }
}
#endif

MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
{
    MS_BOOL bRet = TRUE;
    pVPUHalContext->_bVPUSingleMode = bEnable;
    return bRet;
}

MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
{
    MS_BOOL bRet = TRUE;
    MS_U8 i=0;
    if (pstCfg != NULL)
    {
        pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
        pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
        for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
        {
            pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
        }
        pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
        pVPUHalContext->_stVPUDecMode.u32Arg    = pstCfg->u32Arg;
    }
    else
    {
        bRet = FALSE;
    }
    return bRet;
}

//static MS_BOOL bVpuExReloadFW = TRUE;
//static MS_BOOL bVpuExLoadFWRlt = FALSE;
MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
{
    pVPUHalContext->bVpuExReloadFW = bReload;
    //VPU_PRINT("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
    return TRUE;
}


//-------------------------------------------------------------------------------------------------
//  Global Functions
//-------------------------------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
{
    VPU_EX_TaskInfo *pTaskInfo  = pInitPara->pTaskInfo;
    MS_U8 u8Offset              = _VPU_EX_GetOffsetIdx(u32Id);
    HVD_User_Cmd eCmd           = E_HVD_CMD_INVALID_CMD;
    VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
    MS_U32 u32Arg = 0xFFFFFFFF;
    MS_U32 u32Timeout = 0;
    HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
    MS_U32 u32CmdArg = 0;
    struct _ctl_info *ctl_ptr = (struct _ctl_info *)
                    MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);

    _HAL_VPU_Entry();
    //Check FW buffer size
    if (1 == u8Offset)
    {
        MS_U32 u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
        MS_U32 u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;

        if (u32CurFWBuffSize < u32MinFWBuffSize)
        {
            VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", u32CurFWBuffSize, u32MinFWBuffSize);
            _HAL_VPU_Release();
            return FALSE;
        }
    }

    if (0 == pVPUHalContext->u8TaskCnt)
    {
        //No task is created, need to load f/w, etc.
        VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);

        if (!_VPU_EX_InitAll(pInitPara))
        {
            VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
            _HAL_VPU_Release();
            return FALSE;
        }

        //Check if controller finish initialization: clear mailbox, etc.
        //Need to check it before sending any controller commands!
        u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
        while (CTL_STU_NONE == ctl_ptr->statue)
        {
            if (HVD_GetSysTime_ms() > u32Timeout)
            {
                VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
                VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
                     ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
                MS_U32 t=0;
                for (t=0; t<30; t++)
                {
                    VPU_MSG_DBG("_pc=0x%lx\n", HAL_VPU_EX_GetProgCnt());
                }
                _HAL_VPU_Release();
                return FALSE;
            }

            MsOS_ReadMemory();
        }

        VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
             ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);

    }
    else
    {
        if (pVPUHalContext->_bVPUSingleMode)
        {
            //Show error message
            VPU_PRINT("This task will use dram instead of sram!!!\n");
            VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
        }

        if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
        {
            VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
            _HAL_VPU_Release();
            return FALSE;
        }
        if (pInitPara->pVLCCfg)
        {
            if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
            {
                VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
                _HAL_VPU_Release();
                return FALSE;
            }
        }
    }

    #if 1  // For TEE
    if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
    {
        MS_U32 u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);

        if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFF)
        {
            ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFF;
        }
        else
        {
            ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
        }

        MsOS_FlushMemory();
        VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);

        ///printf("DRV side,      share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
        ///printf("FW side,  task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
    }
    #endif

    if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
    {
        //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
        //arg=1 to get better performance for single task
        u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
        VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%lx\n", u32CmdArg);
        eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
        if (E_HVD_RETURN_SUCCESS != eCtrlRet)
        {
            VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
        }
    }
    else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
    {
        if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
        {
            switch (pVPUHalContext->_stVPUDecMode.u32Arg)
            {
                case E_VPU_CMD_MODE_KR3D_INTERLACE:
                    u32CmdArg = CTL_MODE_3DTV;
                    break;
                case E_VPU_CMD_MODE_KR3D_FORCE_P:
                    u32CmdArg = CTL_MODE_3DTV_PROG;
                    break;
                case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
                    u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
                    break;
                case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
                    u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
                    break;
                default:
                    u32CmdArg = CTL_MODE_3DTV;
                    VPU_MSG_INFO("%lx not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
                    break;
            }
        }
        else
        {
            u32CmdArg = CTL_MODE_3DWMV;
        }
        VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%lx\n", u32CmdArg);
        eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
        if (E_HVD_RETURN_SUCCESS != eCtrlRet)
        {
            VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
        }
    }
    else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
    {
        if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
        {
            u32CmdArg = CTL_MODE_ONE_STC;
        }
        else
        {
            u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
        }
        VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%lx\n", u32CmdArg);
        eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
        if (E_HVD_RETURN_SUCCESS != eCtrlRet)
        {
            VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
        }
    }
    // Set heap size for current task
    ctl_ptr->heap_size[u8Offset] = pInitPara->pTaskInfo->u32HeapSize;
    MsOS_FlushMemory();

    eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
#if defined(SUPPORT_NEW_MEM_LAYOUT)
    if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
        u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
    else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
        u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
    else
    {
        VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
        _HAL_VPU_Release();
        return FALSE;
    }
#else
    u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
#endif

    HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);

    MsOS_ReadMemory();
    VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
         ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);

    u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
    while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
    {
        if (HVD_GetSysTime_ms() > u32Timeout)
        {
            VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
            MS_U32 t=0;
            for (t=0; t<30; t++)
            {
                VPU_MSG_DBG("_pc=0x%lx\n", HAL_VPU_EX_GetProgCnt());
            }

            pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
            VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
            _HAL_VPU_Release();
            return FALSE;
        }

        MsOS_ReadMemory();
    }

    VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
         ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);


    if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
    {
        HAL_HVD_EX_SetBufferAddr(u32Id);
    }

    if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
    {
        eDecType = E_VPU_EX_DECODER_MVD;
    }
    else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
    {
        eDecType = E_VPU_EX_DECODER_HVD;
    }
    else
    {
        VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
        _HAL_VPU_Release();
        return FALSE;
    }

    if (pTaskInfo->eDecType != eDecType)
    {
        VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
            pTaskInfo->eDecType, eDecType);
    }
    goto _SAVE_DEC_TYPE;

_SAVE_DEC_TYPE:
    if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
    {
        pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
    }
    else
    {
        VPU_MSG_ERR("Cannot save eDecType!!\n");
    }

    (pVPUHalContext->u8TaskCnt)++;
    _HAL_VPU_Release();
    return TRUE;
}

MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
{
    HVD_Return eRet;
    HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
    MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
    MS_U32 u32Timeout       = HVD_GetSysTime_ms() + 3000;

    _HAL_VPU_Entry();
    VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);

    eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
    if(eRet != E_HVD_RETURN_SUCCESS)
    {
        VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
    }

    {
        struct _ctl_info *ctl_ptr = (struct _ctl_info *)
            MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
        u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;

        MsOS_ReadMemory();

        VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
            ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);

        while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
        {
            if (HVD_GetSysTime_ms() > u32Timeout)
            {
                VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
                pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
                VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");

                if(pVPUHalContext->u8TaskCnt == 1)
                {
                    VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
                    break;
                }
                else if(pVPUHalContext->u8TaskCnt == 2)
                {
                    VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
                    _HAL_VPU_Release();
                    return FALSE;
                }
                else
                {
                    VPU_MSG_ERR("Task number is not correct\n");
                    _HAL_VPU_Release();
                    return FALSE;
                }
            }

            MsOS_ReadMemory();
        }

        VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
            ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
    }

    pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
    if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
    {
        pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_MAIN_STREAM0;
    }

    if (pVPUHalContext->u8TaskCnt)
    {
        (pVPUHalContext->u8TaskCnt)--;
    }
    else
    {
        VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
    }

    if (0 == pVPUHalContext->u8TaskCnt)
    {
        VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
        _VPU_EX_DeinitAll();
        HAL_VPU_EX_SetSingleDecodeMode(FALSE);
        pVPUHalContext->u32VPUSHMAddr = 0;
        pVPUHalContext->u32FWShareInfoAddr[0] = 0xFFFFFFFF;
        pVPUHalContext->u32FWShareInfoAddr[1] = 0xFFFFFFFF;
        pVPUHalContext->u32FWShareInfoAddr[2] = 0xFFFFFFFF;
        pVPUHalContext->u32FWShareInfoAddr[3] = 0xFFFFFFFF;
    }
    else
    {
        pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFF;
        _VPU_EX_DeinitHW();
    }

    _HAL_VPU_Release();
    return TRUE;
}

MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
{
    MS_U32 u32DestAddr  = pFWCodeCfg->u32DstAddr;
    MS_U32 u32BinAddr   = pFWCodeCfg->u32BinAddr;
    MS_U32 u32Size      = pFWCodeCfg->u32BinSize;
#if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
    MS_U32 u32DestSize  = pFWCodeCfg->u32DstSize;
#endif

    if (FALSE == HAL_VPU_EX_GetFWReload())
    {
        //VPU_PRINT("%s bFWReload FALSE!!!\n", __FUNCTION__);
        if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
        {
            VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
        }
        else
        {
            //Check f/w prefix "VDEC20"
            if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
            {
                VPU_MSG_ERR("Wrong prefix: reload fw!\n");
            }
            else
            {
                VPU_MSG_INFO("Skip loading fw this time!!!\n");
                return TRUE;
            }
        }
    }

    if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
    {
#if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
        if (u32Size != 0)
        {
            SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;

            if (HAL_MIU1_BASE <= MsOS_VA2PA(u32DestAddr))
            {
                cpyflag = E_SPIDMA_DEV_MIU1;
            }
            else
            {
                cpyflag = E_SPIDMA_DEV_MIU0;
            }

            if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
            {
                goto _load_code_fail;
            }
        }
        else
        {
            goto _load_code_fail;
        }
#else
        goto _load_code_fail;
#endif
    }
    else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
    {
        if (u32BinAddr != 0 && u32Size != 0)
        {
#if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
            if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
            {
                if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
                {
                    VPU_MSG_INFO("Decompress ok!!!\n");
                }
                else
                {
                    VPU_MSG_INFO("Decompress fail!!!\n");
                }
            }
            else
#endif
            {
                HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
            }
        }
        else
        {
            goto _load_code_fail;
        }
    }
    else
    {
#if VPU_ENABLE_EMBEDDED_FW_BINARY
        VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%ld\n",
                    u32DestAddr, ((MS_U32) u8HVD_FW_Binary),
                    (MS_U32) sizeof(u8HVD_FW_Binary));

#if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
        if(_VPU_EX_DecompressBin((MS_U32)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
        {
            if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
            {
                VPU_MSG_INFO("Decompress ok!!!\n");
            }
            else
            {
                VPU_MSG_INFO("Decompress fail!!!\n");
            }
        }
        else
#endif
        {
            HVD_memcpy(u32DestAddr, (MS_U32)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
        }
#else
        goto _load_code_fail;
#endif
    }

    MAsm_CPU_Sync();
    MsOS_FlushMemory();

    if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
    {
        VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
        goto _load_code_fail;
    }

    pVPUHalContext->bVpuExLoadFWRlt = TRUE;
    return TRUE;

_load_code_fail:
    pVPUHalContext->bVpuExLoadFWRlt = FALSE;
    return FALSE;
}

void HAL_VPU_EX_InitRegBase(MS_U32 u32RegBase)
{
    u32VPURegOSBase = u32RegBase;
}

MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
{
#if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))

    MS_U32 u32ShmId;
    MS_U32 u32Addr;
    MS_U32 u32BufSize;


    if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
                                          sizeof(VPU_Hal_CTX),
                                          &u32ShmId,
                                          &u32Addr,
                                          &u32BufSize,
                                          MSOS_SHM_QUERY))
    {
        if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
                                             sizeof(VPU_Hal_CTX),
                                             &u32ShmId,
                                             &u32Addr,
                                             &u32BufSize,
                                             MSOS_SHM_CREATE))
        {
            VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
            if(pVPUHalContext == NULL)
            {
                pVPUHalContext = &gVPUHalContext;
                memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
                _VPU_EX_Context_Init();
                VPU_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
            }
            else
            {
                VPU_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
            }
            //return FALSE;
        }
        else
        {
            memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
            pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
            _VPU_EX_Context_Init();
        }
    }
    else
    {
        pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
    }
#else
    if(pVPUHalContext == NULL)
    {
        pVPUHalContext = &gVPUHalContext;
        memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
        _VPU_EX_Context_Init();
    }
#endif

    return TRUE;

}

HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
{
    MS_U32 i = 0;

    if(eStreamType == E_HAL_VPU_SUB_STREAM)
    {
        return E_HAL_VPU_STREAM_NONE;
    }

    _HAL_VPU_MutexCreate();

    if (E_HAL_VPU_MVC_STREAM == eStreamType)
    {
        if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
        {
            pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
            return pVPUHalContext->_stVPUStream[0].eStreamId;       /// Need to check
        }
    }
    else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
    {
        for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
        {
            if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
                && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
            {
                return pVPUHalContext->_stVPUStream[i].eStreamId;
            }
        }
    }
    else if (E_HAL_VPU_SUB_STREAM == eStreamType)
    {
        for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
        {
            if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
                && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
            {
                return pVPUHalContext->_stVPUStream[i].eStreamId;
            }
        }
    }

    return E_HAL_VPU_STREAM_NONE;
}

MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
{
    VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);

    // enable module
    _VPU_EX_ClockInv(InitParams->bClockInv);
    _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
    HAL_VPU_EX_PowerCtrl(TRUE);

#if 1                           //Create VPU's own mutex
    //_HAL_VPU_MutexCreate();
#else
    pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
    pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
#endif

    return TRUE;
}

MS_BOOL HAL_VPU_EX_DeInit(void)
{
    if (0 != _VPU_EX_GetActiveCodecCnt())
    {
        VPU_MSG_DBG("do nothing since codec is active.\n");
        return TRUE;
    }

    memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));

    HAL_VPU_EX_PowerCtrl(FALSE);
    HAL_VPU_EX_SwRelseMAU();
    //_HAL_VPU_MutexDelete();

    return TRUE;
}

void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
{
    if (bEnable)
    {
        _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
        pVPUHalContext->_bVPUPowered = TRUE;
    }
    else
    {
        _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
        pVPUHalContext->_bVPUPowered = FALSE;
    }
}

void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
{
    _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
    _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
    _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
    VPU_EX_TimerDelayMS(1);
}

///-----------------------------------------------------------------------------
/// config AVCH264 CPU
/// @param u32StAddr \b IN: CPU binary code base address in DRAM.
/// @param u8dlend_en \b IN: endian
///     - 1, little endian
///     - 0, big endian
///-----------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32StAddr)
{
    MS_BOOL bRet = TRUE;
    MS_U32 u32Offset = 0;
    MS_U16 tempreg = 0;

    u32Offset = (u32StAddr >= HAL_MIU1_BASE) ? (u32StAddr-HAL_MIU1_BASE) : u32StAddr ;
    _VPU_Write2Byte(VPU_REG_SPI_BASE,  0xC000);
    _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
    _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
    _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L,  0xc000);
    _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H,  0xffff);
    _VPU_Write2Byte(VPU_REG_IO2_BASE,  0x8000);
    _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L,  0x0000);
    _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0x2000);






    #if (VPU_ENABLE_MOBF_TEST)
    MS_U32 u32BSAddr = 0x61C00000;
    MS_U32 u32BSSize = 0x400000;
    MS_U8 u8MobfRidx=0x0;
    MS_U8 u8MobfWidx=0x1;
    MS_U32 u32BsVpuAddr;

    if(u32BSAddr >= HAL_MIU1_BASE)
    {
        u32BsVpuAddr= (u32BSAddr - HAL_MIU1_BASE) + VPU_MIU1BASE_ADDR;
    }
    else
    {
        u32BsVpuAddr= u32BSAddr;
    }
    MS_U32 u32BSStartDiv8 = (u32BsVpuAddr >> 3)&0x1fffffff;
    MS_U32 u32BSEndDiv8 = ((u32BsVpuAddr+u32BSSize) >> 3)&0x1fffffff;

    //set MOBF region 0 to bistream buffer
    _VPU_Write2Byte(MAU1_REG_REGION_MASK0_L, (MS_U16)0xffff);
    _VPU_Write2Byte(MAU1_REG_REGION_MASK0_H, (MS_U16)0xffff);
    _VPU_Write2Byte(MAU1_REG_REGION_START0_L, (MS_U16)(u32BSStartDiv8 & 0xffff));
    _VPU_Write2Byte(MAU1_REG_REGION_START0_H, (MS_U16)((u32BSStartDiv8 >> 16) & 0xffff));
    _VPU_Write2Byte(MAU1_REG_REGION_END0_L, (MS_U16)(u32BSEndDiv8 & 0xffff));
    _VPU_Write2Byte(MAU1_REG_REGION_END0_H, (MS_U16)((u32BSEndDiv8 >> 16) & 0xffff));
    _VPU_Write2Byte(MAU1_REG_REGION_EN, (MS_U16)0x0001);


    _VPU_Write2Byte(MAU1_REG_MIU_RW_TAG1, (((MS_U16)u8MobfWidx)<<8)|((MS_U16)u8MobfRidx));
    #endif

    if(u32StAddr >= HAL_MIU1_BASE)
    {
        // Data sram base Unit: byte address
        _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset  & 0x0000ffff)) ;
        _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
        // Instruction sram base Unit: byte address
        _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
        _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));

        _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
    }
    else
    {
        // Data sram base Unit: byte address
        _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
        _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
        // Instruction sram base Unit: byte address
        _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
        _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));

        _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
    }

    tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
    tempreg |= VPU_REG_IO2_EN;
    tempreg |= VPU_REG_QMEM_SPACE_EN;
    _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);

    return bRet;
}

///-----------------------------------------------------------------------------
/// Set IQMem data access mode or instruction fetch mode
/// @param u8dlend_en \b IN: endian
///     - 1, switch to data access mode
///     - 0, switch to instruction fetch mode
///-----------------------------------------------------------------------------
void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
{

    if(bEnable){

        _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
        _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);

    }
    else{

        _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);

    }
}

///-----------------------------------------------------------------------------
/// H.264 SW reset
/// @return TRUE or FALSE
///     - TRUE, Success
///     - FALSE, Failed
///-----------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
{
    MS_U16 tempreg = 0, tempreg1 = 0;

    //From T4, need to check MAU idle before reset VPU
    if (bCheckMauIdle)
    {
        MS_U32 mau_idle_cnt = 100;// ms
        while (mau_idle_cnt)
        {
            if (TRUE == _VPU_EX_MAU_IDLE())
            {
                break;
            }
            mau_idle_cnt--;
            MsOS_DelayTask(1);
        }

        if (mau_idle_cnt == 0)
        {
            VPU_PRINT("MAU idle time out~~~~~\n");
        }
    }


    HAL_VPU_EX_MIU_RW_Protect(TRUE);

    tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
    tempreg1 |= MAU1_REG_SW_RESET;
    _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);

#if defined(UDMA_FPGA_ENVI)
    tempreg = _VPU_Read2Byte(VPU_REG_RESET);
   _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
#endif

    tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
    tempreg &= ~VPU_REG_CPU_R2_EN;
    tempreg &= ~VPU_REG_CPU_SW_RSTZ;
    tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
    _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);

    VPU_EX_TimerDelayMS(1);
    HAL_VPU_EX_MIU_RW_Protect(FALSE);

    pVPUHalContext->_bVPURsted = FALSE;
    return TRUE;
}

///-----------------------------------------------------------------------------
/// CPU reset release
///-----------------------------------------------------------------------------
void HAL_VPU_EX_SwRstRelse(void)
{
    MS_U16 tempreg = 0, tempreg1 = 0;

    tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
    tempreg |= VPU_REG_CPU_R2_EN;
    tempreg |= VPU_REG_CPU_SW_RSTZ;
    tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
    _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);

    tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
    tempreg1 &= ~MAU1_REG_SW_RESET;
    _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);

    pVPUHalContext->_bVPURsted = TRUE;
}

void HAL_VPU_EX_SwRelseMAU(void)
{
    MS_U16 tempreg = 0;

    tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
    tempreg &= ~MAU1_REG_SW_RESET;
    _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
}

MS_U32 HAL_VPU_EX_MemRead(MS_U32 u32Addr)
{
    MS_U32 u32value = 0;

    return u32value;
}

MS_BOOL HAL_VPU_EX_MemWrite(MS_U32 u32Addr, MS_U32 u32value)
{
    MS_BOOL bRet = TRUE;

    return bRet;
}

///-----------------------------------------------------------------------------
/// Check AVCH264 Ready or not
/// @return TRUE or FALSE
///     - TRUE, MailBox is free
///     - FALSE, MailBox is busy
/// @param u8MBox \b IN: MailBox to check
///     - AVCH264_HI_MBOX0,
///     - AVCH264_HI_MBOX1,
///     - AVCH264_RISC_MBOX0,
///     - AVCH264_RISC_MBOX1,
///-----------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
{
    MS_BOOL bResult = FALSE;

    switch (u32type)
    {
        case VPU_HI_MBOX0:
            bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
            break;
        case VPU_HI_MBOX1:
            bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
            break;
        case VPU_RISC_MBOX0:
            bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
            break;
        case VPU_RISC_MBOX1:
            bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
            break;
        default:
            break;
    }
    return bResult;
}


///-----------------------------------------------------------------------------
/// Read message from AVCH264
/// @return TRUE or FALSE
///     - TRUE, success
///     - FALSE, failed
/// @param u8MBox \b IN: MailBox to read
///     - AVCH264_RISC_MBOX0
///     - AVCH264_RISC_MBOX1
/// @param u32Msg \b OUT: message read
///-----------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
{
    MS_BOOL bResult = TRUE;

    switch (u32type)
    {
        case VPU_HI_MBOX0:
            *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
                ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
            break;
        case VPU_HI_MBOX1:
            *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
                ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
            break;
        case VPU_RISC_MBOX0:
            *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
                ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
            break;
        case VPU_RISC_MBOX1:
            *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
                ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
            break;
        default:
            *u32Msg = 0;
            bResult = FALSE;
            break;
    }
    return bResult;
}

///-----------------------------------------------------------------------------
/// Mailbox from AVCH264 clear bit resest
///-----------------------------------------------------------------------------
void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
{
    switch (u32type)
    {
        case VPU_RISC_MBOX0:
            _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
            break;
        case VPU_RISC_MBOX1:
            _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
            break;
        default:
            break;
    }
}

///-----------------------------------------------------------------------------
/// Send message to AVCH264
/// @return TRUE or FALSE
///     - TRUE, Success
///     - FALSE, Failed
/// @param u8MBox \b IN: MailBox
///     - AVCH264_HI_MBOX0,
///     - AVCH264_HI_MBOX1,
///-----------------------------------------------------------------------------
MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
{
    MS_BOOL bResult = TRUE;

    VPU_MSG_DBG("type=%lu, msg=0x%lx\n", u32type, u32Msg);

    switch (u32type)
    {
        case VPU_HI_MBOX0:
        {
            _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
            _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
            break;
        }
        case VPU_HI_MBOX1:
        {
            _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
            _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
            break;
        }
        default:
        {
            bResult = FALSE;
            break;
        }
    }

    return bResult;
}

MS_U32 HAL_VPU_EX_GetProgCnt(void)
{

    MS_U16 expc_l=0;
    MS_U16 expc_h=0;
    expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
    expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
    return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
}

MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
{
    return _VPU_EX_GetOffsetIdx(u32Id);
}

void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_U32 u32ShmAddr)
{
    MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);

    if (u32ShmAddr == 0)
    {
        pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFF;
    }
    else
    {
        if (u8Offset == 0)
        {
            pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
        }
        else if (u8Offset == 1)
        {
            pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
        }
    }

    VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
    return;
}

MS_U32 HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
{
    MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);

    return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
}


MS_BOOL HAL_VPU_EX_IsPowered(void)
{
    return pVPUHalContext->_bVPUPowered;
}

MS_BOOL HAL_VPU_EX_IsRsted(void)
{
    return pVPUHalContext->_bVPURsted;
}

MS_BOOL HAL_VPU_EX_MVDInUsed(void)
{
    //MVD is in used for MVD or HVD_TSP mode.
    MS_U8 i;
    MS_U8 u8UseCnt = 0;

    for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
    {
        if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
            (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
        {
            u8UseCnt++;
        }
    }

    VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);

    if (u8UseCnt != 0)
    {
        return TRUE;
    }
    else
    {
        return FALSE;
    }
}

MS_BOOL HAL_VPU_EX_HVDInUsed(void)
{
    //HVD is in used for HVD or MVD in sub stream.
    MS_U8 i;
    MS_U8 u8UseCnt = 0;

    for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
    {
        if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype) ||
            ((E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) && (E_HAL_VPU_SUB_STREAM0 == pVPUHalContext->_stVPUStream[i].eStreamId)))
        {
            u8UseCnt++;
        }
    }

    VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);

    if (u8UseCnt != 0)
    {
        return TRUE;
    }
    else
    {
        return FALSE;
    }
}

//-----------------------------------------------------------------------------
/// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
/// @brief \b Function \b Description:  Set debug level
/// @param -elevel \b IN : debug level
//-----------------------------------------------------------------------------
void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
{
    VPU_PRINT("%s eLevel=0x%x\n", __FUNCTION__, eLevel);

    switch (eLevel)
    {
        case E_VPU_EX_UART_LEVEL_ERR:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
            break;
        }
        case E_VPU_EX_UART_LEVEL_INFO:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
            break;
        }
        case E_VPU_EX_UART_LEVEL_DBG:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
            break;
        }
        case E_VPU_EX_UART_LEVEL_TRACE:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
            break;
        }
        case E_VPU_EX_UART_LEVEL_FW:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
            break;
        }
        default:
        {
            u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
            break;
        }
    }
}

MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
{
    HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
    MS_U32 u32CmdArg = (MS_U32)eVerType;
    MS_U32 u32Version = 0xFFFFFFFF;
    eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
    if (E_HVD_RETURN_SUCCESS != eCtrlRet)
    {
        VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
        return u32Version;
    }

    MS_BOOL bRet = false;
    MS_U32 u32TimeOut = 0xFFFFFFFF;

    while(--u32TimeOut)
    {
        if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
        {
            bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
            if (false == bRet)
            {
                VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
                return u32Version;
            }

            _VPU_WriteWordMask(  VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR  , VPU_REG_RISC_MBOX0_CLR);
            VPU_MSG_DBG("E_DUAL_VERSION arg=%lx u32Version = 0x%lx\n", u32CmdArg, u32Version);
            return u32Version;
        }
    }

    VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);

    return u32Version;
}

MS_BOOL HAL_VPU_EX_NotSupportDS(void)
{
    return FALSE;
}

//-----------------------------------------------------------------------------
/// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
/// @brief \b Function \b Description:  Get VPU MIU base address
/// @return - vpu MIU1 base
//-----------------------------------------------------------------------------
MS_U32 HAL_VPU_EX_MIU1BASE(void)
{
    return VPU_MIU1BASE_ADDR;
}

MS_U32 HAL_VPU_EX_GetSHMAddr(void)
{
    if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
    {
        return 0;
    }
    return pVPUHalContext->u32VPUSHMAddr;
}
MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
{
    pVPUHalContext->bEnableVPUSecureMode = enable;
    return TRUE;
}

MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
{
    ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;

    ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;

    ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
    ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;

    return TRUE;
}

#else
#include "halVPU_EX.h"
#include "drvMMIO.h"
#include "../hvd_ex/regHVD_EX.h"

extern int lib_lowprintf(const char *fmt, ...);
#define PRINTF lib_lowprintf
#define HVD_LWORD(x)    (MS_U16)((x)&0xffff)
#define HVD_HWORD(x)    (MS_U16)(((x)>>16)&0xffff)

MS_U8 u8FW_Binary[] = {
    #include "fwVPU.dat"
};

MS_U32 u32HVDRegOSBase;

MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_U32 addr)
{
    //PRINTF("do load code,u32DestAddr %x\n",addr);
    memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
    MAsm_CPU_Sync();
    MsOS_FlushMemory();

    if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
    {
        PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
        return FALSE;
    }
    return TRUE;
}

MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
{
#if 1
    MS_U32 u32StAddr_main;
    MS_U32 u32StAddr_sub;
    MS_U32 u32NonPMBankSize = 0;
    VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;

    if(param == NULL)
    {
        return FALSE;
    }

    register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;

    MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);

    // ES buffer
    u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
    u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;

    if (u32StAddr_main >= register_lockdown->MIU1_BaseAddr)
    {
        u32StAddr_main -= register_lockdown->MIU1_BaseAddr;
    }

    if (u32StAddr_sub >= register_lockdown->MIU1_BaseAddr)
    {
        u32StAddr_sub -= register_lockdown->MIU1_BaseAddr;
    }

    //Lock down register
    _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
    _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));

    _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
    _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
    //~

    // Lock Down
    //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
    //~
#endif
    return TRUE;
}

#endif