1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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15 //
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #elif defined( MSOS_TYPE_ECOS)
150 #define VPRINTF diag_printf
151 #else
152 #ifndef ANDROID
153 #define VPRINTF printf
154 #else
155 #include <sys/mman.h>
156 #include <cutils/ashmem.h>
157 #include <cutils/log.h>
158 #define VPRINTF ALOGD
159 #endif
160 #endif
161
162 #ifdef CONFIG_MSTAR_CLKM
163 #include "drvCLKM.h"
164 #endif
165 //-------------------------------------------------------------------------------------------------
166 // Driver Compiler Options
167 //-------------------------------------------------------------------------------------------------
168
169
170 //-------------------------------------------------------------------------------------------------
171 // Local Defines
172 //-------------------------------------------------------------------------------------------------
173 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
174
175 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
176 #ifdef VDEC3
177 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
178 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
179 #define MAX_MVD_SLQ_COUNT 2
180 #define MAX_SUPPORT_DECODER_NUM 16
181 #else
182 #define MAX_SUPPORT_DECODER_NUM 2
183 #endif
184 typedef enum
185 {
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
187 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
188 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
189 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
190
191
192 typedef enum
193 {
194 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
197 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
198 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
199 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
200
201 typedef enum
202 {
203 E_VPU_UART_CTRL_DISABLE = BIT(4),
204 E_VPU_UART_CTRL_ERR = BIT(0),
205 E_VPU_UART_CTRL_INFO = BIT(1),
206 E_VPU_UART_CTRL_DBG = BIT(2),
207 E_VPU_UART_CTRL_FW = BIT(3),
208 E_VPU_UART_CTRL_MUST = BIT(4),
209 E_VPU_UART_CTRL_TRACE = BIT(5),
210 } VPU_EX_UartCtrl;
211
212 typedef struct
213 {
214 HAL_VPU_StreamId eStreamId;
215 VPU_EX_DecoderType eDecodertype;
216 } VPU_EX_Stream;
217
218 typedef struct
219 {
220 MS_BOOL bSTCSetMode;
221 MS_U32 u32STCIndex;
222 } VPU_EX_STC;
223
224 #define VPU_MSG_ERR(format, args...) \
225 do \
226 { \
227 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
228 { \
229 VPRINTF("[VPU][ERR]%s:", __FUNCTION__); \
230 VPRINTF(format, ##args); \
231 } \
232 } while (0)
233
234 #define VPU_MSG_DBG(format, args...) \
235 do \
236 { \
237 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
238 { \
239 VPRINTF("[VPU][DBG]%s:", __FUNCTION__); \
240 VPRINTF(format, ##args); \
241 } \
242 } while (0)
243
244 #define VPU_MSG_INFO(format, args...) \
245 do \
246 { \
247 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
248 { \
249 VPRINTF("[VPU][INF]%s:", __FUNCTION__); \
250 VPRINTF(format, ##args); \
251 } \
252 } while (0)
253
254 //------------------------------ MIU SETTINGS ----------------------------------
255 //#ifdef EVDR2
256 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
257 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
258 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(3))
259
260 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
261 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
262 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(3))
263
264
265
266 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
267 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
268 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) ) //g03
269 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
270 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
271 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == BIT(3)) ) //g03
272
273 //#endif
274
275
276
277 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
278 do \
279 { \
280 if (miu_clients##_ON_MIU0 == 1) \
281 { \
282 _MaskMiuReq_##miu_clients(mask); \
283 } \
284 else \
285 { \
286 if (miu_clients##_ON_MIU1 == 1) \
287 { \
288 _MaskMiu1Req_##miu_clients(mask); \
289 } \
290 \
291 } \
292 } while(0)
293
294
295
296
297 #if ENABLE_VPU_MUTEX_PROTECTION
298 MS_S32 s32VPUMutexID = -1;
299 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
300
301 #define _HAL_VPU_MutexCreate() \
302 if (s32VPUMutexID < 0) \
303 { \
304 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
305 }
306
307 #define _HAL_VPU_MutexDelete() \
308 if (s32VPUMutexID >= 0) \
309 { \
310 MsOS_DeleteMutex(s32VPUMutexID); \
311 s32VPUMutexID = -1; \
312 }
313
314 #define _HAL_VPU_Entry() \
315 if (s32VPUMutexID >= 0) \
316 { \
317 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
318 { \
319 VPRINTF("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
320 } \
321 }
322
323 #define _HAL_VPU_Return(_ret) \
324 { \
325 if (s32VPUMutexID >= 0) \
326 { \
327 MsOS_ReleaseMutex(s32VPUMutexID); \
328 } \
329 return _ret; \
330 }
331
332 #define _HAL_VPU_Release() \
333 { \
334 if (s32VPUMutexID >= 0) \
335 { \
336 MsOS_ReleaseMutex(s32VPUMutexID); \
337 } \
338 }
339 #else
340 #define _HAL_VPU_MutexCreate()
341 #define _HAL_VPU_MutexDelete()
342 #define _HAL_VPU_Entry()
343 #define _HAL_VPU_Return(_ret) {return _ret;}
344 #define _HAL_VPU_Release()
345 #endif
346
347 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
348 #define VPU_CMD_TIMEOUT 1000 // 1 sec
349
350 //-------------------------------------------------------------------------------------------------
351 // Local Structures
352 //-------------------------------------------------------------------------------------------------
353 typedef struct _VPU_HWInitFunc
354 {
355 MS_BOOL (*pfMVDHW_Init)(void);
356 MS_BOOL (*pfMVDHW_Deinit)(void);
357 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
358 MS_BOOL (*pfHVDHW_Deinit)(void);
359 } VPU_HWInitFunc;
360
361 typedef struct
362 {
363 MS_U32 u32ApiHW_Version; //<Version of current structure>
364 MS_U16 u16ApiHW_Length; //<Length of this structure>
365
366 MS_U8 u8Cap_Support_Decoder_Num;
367
368 MS_BOOL bCap_Support_MPEG2;
369 MS_BOOL bCap_Support_H263;
370 MS_BOOL bCap_Support_MPEG4;
371 MS_BOOL bCap_Support_DIVX311;
372 MS_BOOL bCap_Support_DIVX412;
373 MS_BOOL bCap_Support_FLV;
374 MS_BOOL bCap_Support_VC1ADV;
375 MS_BOOL bCap_Support_VC1MAIN;
376
377 MS_BOOL bCap_Support_RV8;
378 MS_BOOL bCap_Support_RV9;
379 MS_BOOL bCap_Support_H264;
380 MS_BOOL bCap_Support_AVS;
381 MS_BOOL bCap_Support_AVS_PLUS;
382 MS_BOOL bCap_Support_MJPEG;
383 MS_BOOL bCap_Support_MVC;
384 MS_BOOL bCap_Support_VP8;
385 MS_BOOL bCap_Support_VP9;
386 MS_BOOL bCap_Support_HEVC;
387
388 /*New HW Cap and Feature add in struct at the end*/
389 }VDEC_HwCap;
390
391 //-------------------------------------------------------------------------------------------------
392 // Local Functions Prototype
393 //-------------------------------------------------------------------------------------------------
394 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
395 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
396 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
397
398 //-------------------------------------------------------------------------------------------------
399 // Global Variables
400 //-------------------------------------------------------------------------------------------------
401 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
402 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
403 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
404 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
405 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
406 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
407 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
408 #if SUPPORT_G2VP9 && defined(VDEC3)
409 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
410 #endif
411 #if defined (__aeon__)
412 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
413 #else
414 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
415 #endif
416
417 //-------------------------------------------------------------------------------------------------
418 // Local Variables
419 //-------------------------------------------------------------------------------------------------
420 #if 0
421
422 static MS_BOOL _bVPUPowered = FALSE;
423 static MS_BOOL _bVPURsted = FALSE;
424 static MS_BOOL _bVPUSingleMode = FALSE;
425 static VPU_EX_DecModCfg _stVPUDecMode;
426
427 static MS_U8 u8TaskCnt = 0;
428
429 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
430
431 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
432 static VPU_EX_Stream _stVPUStream[] =
433 {
434 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
435 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
436 };
437 static VPU_HWInitFunc stHWInitFunc =
438 {
439 &HAL_MVD_InitHW,
440 &HAL_MVD_DeinitHW,
441 &HAL_HVD_EX_InitHW,
442 &HAL_HVD_EX_DeinitHW,
443 };
444
445 #endif
446
447 #if VPU_ENABLE_EMBEDDED_FW_BINARY
448 static const MS_U8 u8HVD_FW_Binary[] = {
449 #include "fwVPU.dat"
450 };
451
452 #if HVD_ENABLE_RV_FEATURE
453 static const MS_U8 u8HVD_VLC_Binary[] = {
454 #include "fwVPU_VLC.dat"
455 };
456 #endif
457 #endif
458
459
460 #ifdef VDEC3
461 typedef struct
462 {
463 MS_BOOL bTSP;
464 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
465 MS_U32 u32Used;
466 } BBU_STATE;
467
468 typedef struct
469 {
470 MS_BOOL bTSP;
471 MS_BOOL bUsedbyMVD;
472 MS_U32 u32Used;
473 } SLQ_STATE;
474 #endif
475
476 typedef struct
477 {
478 MS_BOOL _bVPUPowered;
479 MS_BOOL _bVPURsted;
480 MS_BOOL _bVPUSingleMode;
481 VPU_EX_DecModCfg _stVPUDecMode;
482 MS_U8 u8TaskCnt;
483 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
484 #ifdef VDEC3
485 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
486 #else
487 VPU_EX_Stream _stVPUStream[2];
488 #endif
489
490 VPU_HWInitFunc stHWInitFunc;
491
492 MS_BOOL bVpuExReloadFW;
493 MS_BOOL bVpuExLoadFWRlt;
494 MS_VIRT u32VPUSHMAddr; //PA
495 MS_BOOL bEnableVPUSecureMode;
496
497 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
498 MS_BOOL bEnableDymanicFBMode;
499 MS_PHY u32DynamicFBAddress;
500 MS_U32 u32DynamicFBSize;
501 #ifdef VDEC3
502 MS_VIRT u32FWCodeAddr;
503 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
504
505 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
506 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
507 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
508
509 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
510 #endif
511 MS_U8 u8ForceRst;
512 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
513 } VPU_Hal_CTX;
514
515 //global variables
516 VPU_Hal_CTX* pVPUHalContext = NULL;
517 VPU_Hal_CTX gVPUHalContext;
518 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
519 MS_BOOL bVPUMbxInitFlag = 0;
520 MS_U8 u8VPUMbxMsgClass = 0;
521 MBX_Msg VPUReeToTeeMbxMsg;
522 MBX_Msg VPUTeeToReeMbxMsg;
523
524 //-------------------------------------------------------------------------------------------------
525 // Debug Functions
526 //-------------------------------------------------------------------------------------------------
527
528
529 //-------------------------------------------------------------------------------------------------
530 // Local Functions
531 //-------------------------------------------------------------------------------------------------
532
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)533 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
534 {
535 #if HVD_ENABLE_RV_FEATURE
536 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
537 {
538 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
539 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
540 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
541
542 if (pVlcCfg->u32BinSize)
543 {
544 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
545
546 MS_U32 u32Start;
547 MS_U32 u32StartOffset;
548 MS_U8 u8MiuSel;
549
550 // Get MIU selection and offset from physical address = 0x30000000
551 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
552
553
554 if(u8MiuSel == E_CHIP_MIU_0)
555 cpyflag = E_SPIDMA_DEV_MIU0;
556 else if(u8MiuSel == E_CHIP_MIU_1)
557 cpyflag = E_SPIDMA_DEV_MIU1;
558 else if(u8MiuSel == E_CHIP_MIU_2)
559 cpyflag = E_SPIDMA_DEV_MIU2;
560
561 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
562 {
563 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
564 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
565
566 return FALSE;
567 }
568 }
569 else
570 {
571 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
572 return FALSE;
573 }
574 #else
575 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
576 return FALSE;
577 #endif
578 }
579 else
580 {
581 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
582 {
583 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
584 {
585 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
586 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
587
588 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
589 BDMA_Result bdmaRlt;
590 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
591
592 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
593 u32SrcAdd = pVlcCfg->u32BinAddr;
594 u32tabsize = pVlcCfg->u32BinSize;
595 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
596 MsOS_FlushMemory();
597 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
598
599 if (E_BDMA_OK != bdmaRlt)
600 {
601 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
602 }
603 #else
604 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
605 #endif
606 }
607 else
608 {
609 VPU_MSG_ERR
610 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
611 return FALSE;
612 }
613 }
614 else
615 {
616 #if VPU_ENABLE_EMBEDDED_FW_BINARY
617 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
618 MS_U8 *pu8HVD_VLC_Binary;
619
620 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
621
622 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
623 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
624 (MS_U32) sizeof(u8HVD_VLC_Binary));
625
626 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
627 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
628 #else
629 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
630 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
631 (MS_U32) sizeof(u8HVD_VLC_Binary));
632
633 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
634 #endif
635 #else
636 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
637 return FALSE;
638 #endif
639 }
640 }
641 #endif
642
643 return TRUE;
644 }
645
646 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)647 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
648 {
649 MS_U8 u8OffsetIdx = 0;
650 MS_U8 u8VSidBaseMask = 0xF0;
651 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
652
653 switch (eVSidBase)
654 {
655 case E_HAL_VPU_MAIN_STREAM_BASE:
656 {
657 u8OffsetIdx = 0;
658 break;
659 }
660 case E_HAL_VPU_SUB_STREAM_BASE:
661 {
662 u8OffsetIdx = 1;
663 break;
664 }
665 case E_HAL_VPU_MVC_STREAM_BASE:
666 {
667 u8OffsetIdx = 0;
668 break;
669 }
670 #ifdef VDEC3
671 case E_HAL_VPU_N_STREAM_BASE:
672 {
673 u8OffsetIdx = u32Id & 0x0F;
674 break;
675 }
676 #endif
677 default:
678 {
679 u8OffsetIdx = 0;
680 break;
681 }
682 }
683
684 /*
685 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
686 u32Id, eVSidBase, u8OffsetIdx);
687 */
688 return u8OffsetIdx;
689 }
690
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)691 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
692 {
693 return _VPU_EX_GetOffsetIdx(u32Id);
694 }
695
_VPU_EX_Context_Init(void)696 static void _VPU_EX_Context_Init(void)
697 {
698 #ifdef VDEC3
699 MS_U8 i;
700
701 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
702 {
703 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
704 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
705 }
706
707 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
708 {
709 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
710 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
711 }
712
713 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
714 {
715 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
716 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
717 }
718
719 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
720 {
721 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
722 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
723 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
724 }
725 #else
726 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
727 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
728 #endif
729 pVPUHalContext->bVpuExReloadFW = TRUE;
730 pVPUHalContext->u8ForceRst = 0;
731 }
732
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)733 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
734 {
735 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
736 MS_U8 u8OffsetIdx = 0;
737
738 if (NULL == pTaskInfo)
739 {
740 return eCmd;
741 }
742
743 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
744
745 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
746 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
747
748 #ifdef VDEC3
749 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
750 {
751 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
752 {
753 eCmd = E_NST_CMD_TASK_MVD_TSP;
754 }
755 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
756 {
757 eCmd = E_NST_CMD_TASK_MVD_SLQ;
758 }
759 }
760 #else
761 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
762 {
763 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
764 {
765 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
766 }
767 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
768 {
769 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
770 }
771 }
772 #endif
773 #ifdef VDEC3
774 #if SUPPORT_G2VP9
775 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
776 #else
777 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
778 #endif
779 {
780 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
781 {
782 eCmd = E_NST_CMD_TASK_HVD_TSP;
783 }
784 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
785 {
786 eCmd = E_NST_CMD_TASK_HVD_BBU;
787 }
788 }
789 #else
790 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
791 {
792 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
793 {
794 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
795 }
796 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
797 {
798 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
799 }
800 }
801 #endif
802
803 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
804 return eCmd;
805 }
806
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)807 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
808 {
809 if (!pTaskInfo)
810 {
811 VPU_MSG_ERR("null input\n");
812 return FALSE;
813 }
814
815 //Check if we need to init MVD HW
816 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
817 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
818 {
819 //Init HW
820 if (FALSE == HAL_VPU_EX_MVDInUsed())
821 {
822 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
823 {
824 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
825 return FALSE;
826 }
827 }
828 else
829 {
830 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
831 }
832 }
833
834 #if 0 // k6 is wbmvop, no need to open hvd clock for sub diu interface
835 //MVD use sub mvop
836 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
837 #ifdef VDEC3
838 (pTaskInfo->u8HalId == 1) )
839 #else
840 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
841 #endif
842 {
843 VPU_MSG_ERR("Force turn on HVD\n");
844 if(!HAL_VPU_EX_HVDInUsed())
845 {
846 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
847 {
848 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
849 {
850 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
851 return FALSE;
852 }
853 }
854 else
855 {
856 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
857 #ifdef CONFIG_MSTAR_CLKM
858 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
859 #else
860 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
861 #endif
862 }
863 }
864 else
865 {
866 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
867 }
868 }
869 #endif
870
871 //Check if we need to init HVD HW
872 #ifdef VDEC3
873 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
874 #else
875 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
876 #endif
877 {
878 if (!HAL_VPU_EX_MVDInUsed())
879 {
880 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
881 {
882 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
883 return FALSE;
884 }
885 }
886
887 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
888 {
889 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
890 return FALSE;
891 }
892 #if SUPPORT_MSVP9
893 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
894 {
895 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
896 }
897 #endif
898 }
899
900 #if SUPPORT_G2VP9 && defined(VDEC3)
901 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
902 {
903 if (!HAL_VPU_EX_MVDInUsed())
904 {
905 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
906 {
907 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
908 return FALSE;
909 }
910 }
911 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
912 {
913 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
914 return FALSE;
915 }
916 }
917 #endif
918
919 return TRUE;
920 }
921
_VPU_EX_InClock(MS_U32 u32type)922 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
923 {
924 switch (u32type)
925 {
926 case VPU_CLOCK_240MHZ:
927 return 240000000UL;
928 case VPU_CLOCK_216MHZ:
929 return 216000000UL;
930 case VPU_CLOCK_192MHZ:
931 return 192000000UL;
932 case VPU_CLOCK_172MHZ:
933 return 172000000UL;
934 default:
935 return 240000000UL;
936 }
937 }
938
939
940 //#if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
941 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)942 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
943 {
944 //#ifndef MSOS_TYPE_LINUX_KERNEL
945 #if 1
946 MS_U8 ClassNum = 0;
947 MBX_Result result;
948
949 #if 0
950 if (bVPUMbxInitFlag == TRUE)
951 {
952 return TRUE;
953 }
954 #endif
955
956 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
957 {
958 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
959 return FALSE;
960 }
961 else
962 {
963 MApi_MBX_Enable(TRUE);
964 }
965
966 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
967
968 if (E_MBX_SUCCESS != result)
969 {
970 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
971 return FALSE;
972 }
973
974 result = MApi_MBX_RegisterMSG(ClassNum, 10);
975
976 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
977 {
978 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
979 return FALSE;
980 }
981 else
982 {
983 bVPUMbxInitFlag = TRUE;
984 u8VPUMbxMsgClass = ClassNum;
985 return TRUE;
986 }
987 #else
988 return FALSE;
989 #endif
990 }
991
992 //#ifdef MBX_2K
993 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)994 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
995 {
996 MBX_Result result;
997 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
998
999 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1000 {
1001 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1002 }
1003
1004 if (bVPUMbxInitFlag == FALSE)
1005 {
1006 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1007 }
1008
1009 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1010 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1011 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1012 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1013 VPUReeToTeeMbxMsg.u8Index = msg_type;
1014
1015 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1016 if (E_MBX_SUCCESS != result)
1017 {
1018 VPRINTF("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1019 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1020 }
1021
1022 // Receive Reply ACK from TEE side.
1023 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1024
1025 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1026
1027 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1028 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1029 {
1030 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1031 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1032 }
1033 else
1034 #else
1035 do
1036 {
1037 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1038 } while(E_MBX_SUCCESS != result);
1039 #endif
1040 {
1041 u8Index = VPUTeeToReeMbxMsg.u8Index;
1042 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1043
1044 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1045 {
1046 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1047 }
1048 }
1049
1050 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1051 }
1052 #endif
1053
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1054 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1055 {
1056 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1057 {
1058 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1059 {
1060 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1061 return FALSE;
1062 }
1063 else
1064 {
1065 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1066 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1067 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1068 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1069 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1070 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1071 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1072 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1073
1074 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1075
1076
1077 MS_U32 u32Start;
1078
1079 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1080 {
1081 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1082 pVPUHalContext->u32VPUSHMAddr = u32Start;
1083 }
1084 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1085 {
1086 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1087 pVPUHalContext->u32VPUSHMAddr = u32Start;
1088
1089 }
1090 else // == 0
1091 {
1092 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1093 }
1094 }
1095 }
1096 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1097 {
1098 MS_U32 u32Offset;
1099 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1100 {
1101 u32Offset = u32SHMAddr-u32MIU1Addr;
1102 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1103 }
1104 else
1105 {
1106 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1107 }
1108 }
1109 return TRUE;
1110 }
1111
1112
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1113 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1114 {
1115 bVPUMbxInitFlag = TRUE;
1116 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1117 return TRUE;
1118 }
1119
HAL_VPU_EX_ForceSwRst(void)1120 void HAL_VPU_EX_ForceSwRst(void)
1121 {
1122 pVPUHalContext->u8ForceRst = 1;
1123 }
1124
1125 //#endif
1126
HAL_VPU_EX_GetFWReload(void)1127 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1128 {
1129 return pVPUHalContext->bVpuExReloadFW;
1130 }
1131
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1132 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1133 {
1134 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1135 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1136 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1137 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1138 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1139 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1140 )
1141 {
1142 return FALSE;
1143 }
1144 else
1145 {
1146 return TRUE;
1147 }
1148 }
1149
_VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg * pFWCodeCfg)1150 static MS_BOOL _VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg *pFWCodeCfg)
1151 {
1152
1153
1154 #if 1 // bypass mode for debug
1155
1156 // allow non-secure read access
1157 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1158 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1159
1160 // allow non-secure write access
1161 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1162 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1163
1164 #else
1165 MS_PHY u32fwPAStart = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1166 MS_PHY u32fwPAEnd = u32fwPAStart + pFWCodeCfg->u32DstSize;
1167 MS_PHY u32WriteReplaceAddr = u32fwPAStart + CTL_INFO_ADDR;
1168
1169 // 128 bits align
1170 if((u32fwPAStart & 0xF) || (u32fwPAEnd & 0xF) || (u32WriteReplaceAddr & 0xF))
1171 {
1172 VPU_MSG_ERR("[Error] address need 128 bits align\n");
1173 return FALSE;
1174 }
1175
1176 u32fwPAStart >>= 4;
1177 u32fwPAEnd >>= 4;
1178 u32WriteReplaceAddr >>= 4;
1179
1180 // configure 1st secure range start address
1181 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1182 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1183 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1184
1185 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1186 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1187 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1188
1189 // configure 1st secure range end address
1190 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1191 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1192 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1193
1194 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1195 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1196 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1197
1198 // configure replaced address
1199 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1200 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1201 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1202
1203 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1204 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1205 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1206
1207 // Enable limit write access
1208 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1209
1210 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1211
1212 // Enable 1st limit range
1213 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1214
1215 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1216
1217 // Enable One-way bit
1218 _VPU_WriteWordMask(REG_ONEWAY_B16, ONEWAY_B16, ONEWAY_B16);
1219 _VPU_WriteWordMask(REG_LOCK_ONEWAY_B16, LOCK_ONEWAY_B16, LOCK_ONEWAY_B16);
1220
1221 #endif
1222
1223 return TRUE;
1224 }
1225
1226
1227
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1228 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1229 {
1230 MS_PHY u32fwPA = NULL; //physical address
1231 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_240MHZ;
1232
1233 if (TRUE == HAL_VPU_EX_IsPowered())
1234 {
1235 VPU_MSG_DBG("IsPowered\n");
1236 return TRUE;
1237 }
1238 else
1239 {
1240 //VPU hold
1241 HAL_VPU_EX_SwRst(FALSE);
1242
1243 //VPU clock on
1244 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1245
1246 if (VPU_I_R_ON_MIU0)
1247 VPUInitParams.u8MiuSel = 0;
1248 else if (VPU_I_R_ON_MIU1)
1249 VPUInitParams.u8MiuSel = 1;
1250 // else if (VPU_I_R_ON_MIU2)
1251 // VPUInitParams.u8MiuSel = 2;
1252
1253 HAL_VPU_EX_Init(&VPUInitParams);
1254 }
1255
1256 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1257 VPU_EX_TaskInfo *pTaskInfo = NULL;
1258 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1259
1260 if (pInitPara)
1261 {
1262 pFWCodeCfg = pInitPara->pFWCodeCfg;
1263 pTaskInfo = pInitPara->pTaskInfo;
1264 pVlcCfg = pInitPara->pVLCCfg;
1265
1266 if(_VPU_EX_InitAddressLimiter(pFWCodeCfg) == FALSE)
1267 {
1268 VPU_MSG_ERR("(%d) InitAddressLimiter fail\n", __LINE__);
1269 return FALSE;
1270 }
1271 }
1272 else
1273 {
1274 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1275 return FALSE;
1276 }
1277
1278 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1279 //#ifdef MBX_2K
1280 #if 1
1281 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1282 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1283 {
1284 SYS_TEEINFO teemode;
1285 MDrv_SYS_ReadKernelCmdLine();
1286 MDrv_SYS_GetTEEInfo(&teemode);
1287 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1288 {
1289 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1290
1291 if (FALSE == HAL_VPU_EX_GetFWReload())
1292 {
1293 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1294 {
1295 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1296 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1297 {
1298 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1299 return FALSE;
1300 }
1301 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1302 }
1303 else
1304 {
1305 //Check f/w prefix "VDEC30"
1306 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1307 {
1308 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1309 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1310 {
1311 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1312 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1313 return FALSE;
1314 }
1315 }
1316 else
1317 {
1318 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1319 }
1320 }
1321 }
1322 else
1323 {
1324 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1325 {
1326 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1327 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1328 return FALSE;
1329 }
1330 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1331 }
1332 }
1333 }
1334 else
1335 #endif
1336 #endif
1337 {
1338 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1339
1340 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1341 {
1342 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1343 return FALSE;
1344 }
1345 }
1346
1347 if (pVlcCfg)
1348 {
1349 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1350 {
1351 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1352 return FALSE;
1353 }
1354 }
1355
1356 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1357 {
1358 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1359 return FALSE;
1360 }
1361
1362 //Init HW
1363 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1364 {
1365 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1366 //_MVD_INIT_FAIL_RET();
1367 return FALSE;
1368 }
1369 else
1370 {
1371 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1372 }
1373
1374 //set vpu clock to FW
1375 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1376 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1377
1378
1379 #if (VPU_ENABLE_IQMEM)
1380 ctl_ptr->bIQmemEnableIfSupport = TRUE;
1381 #endif
1382
1383 ctl_ptr->statue = CTL_STU_NONE;
1384 //notify controller the interface version of VPU driver.
1385 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1386 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1387 MsOS_FlushMemory();
1388 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1389
1390 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1391 if (TRUE == HAL_VPU_EX_IsRsted())
1392 {
1393 VPU_MSG_DBG("VPU_IsRsted\n");
1394 return TRUE;
1395 }
1396 else
1397 {
1398 HAL_VPU_EX_SwRstRelse();
1399 }
1400
1401 return TRUE;
1402 }
1403
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1404 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1405 {
1406 MS_BOOL bRet = FALSE;
1407
1408 #if defined(VDEC3)
1409 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1410 #else
1411 MS_BOOL isEVD = FALSE ;
1412 #endif
1413 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1414 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1415 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1416
1417 if (FALSE == HAL_VPU_EX_MVDInUsed())
1418 {
1419 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1420 }
1421
1422 if (TRUE == isHVD)
1423 {
1424 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1425 }
1426
1427 #if defined(VDEC3)
1428 if (TRUE == isEVD)
1429 {
1430 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1431 }
1432 #endif
1433
1434 #if SUPPORT_G2VP9 && defined(VDEC3)
1435 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1436 {
1437 bRet = HAL_VP9_EX_DeinitHW();
1438 }
1439 #endif
1440 return bRet;
1441 }
1442
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1443 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1444 {
1445 HAL_VPU_EX_SwRst(TRUE);
1446 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1447 HAL_VPU_EX_DeInit();
1448
1449 return TRUE;
1450 }
1451
_VPU_EX_GetActiveCodecCnt(void)1452 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1453 {
1454 MS_U32 i;
1455 MS_U8 u8ActiveCnt = 0;
1456 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1457 {
1458 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1459 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1460 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1461 {
1462 u8ActiveCnt++;
1463 }
1464 }
1465 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1466 {
1467 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1468 }
1469 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1470 return u8ActiveCnt;
1471 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1472 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1473 {
1474 if (TRUE)
1475 {
1476 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1477 }
1478 else
1479 {
1480 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1481 }
1482 }
1483
_VPU_EX_ClockSpeed(MS_U32 u32type)1484 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1485 {
1486 switch (u32type)
1487 {
1488 case VPU_CLOCK_240MHZ:
1489 case VPU_CLOCK_216MHZ:
1490 case VPU_CLOCK_192MHZ:
1491 case VPU_CLOCK_172MHZ:
1492 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1493 break;
1494 default:
1495 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_240MHZ, TOP_CKG_VPU_CLK_MASK);
1496 break;
1497 }
1498 }
1499 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1500 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1501 {
1502 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1503 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1504 {
1505 return TRUE;
1506 }
1507 return FALSE;
1508 }
1509 #endif
1510
1511
1512 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1513 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1514 {
1515 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1516 {
1517 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1518 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1519 ms_VDECDecompressDeInit();
1520 return TRUE;
1521 }
1522 else
1523 {
1524 return FALSE;
1525 }
1526 }
1527 #endif
1528
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1529 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1530 {
1531 MS_BOOL bRet = TRUE;
1532 pVPUHalContext->_bVPUSingleMode = bEnable;
1533 return bRet;
1534 }
1535
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1536 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1537 {
1538 MS_BOOL bRet = TRUE;
1539 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1540 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1541 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1542
1543 return bRet;
1544 }
1545
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1546 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1547 {
1548 MS_BOOL bRet = TRUE;
1549 MS_U8 i=0;
1550 if (pstCfg != NULL)
1551 {
1552 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1553 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1554 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1555 {
1556 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1557 }
1558 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1559 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1560 }
1561 else
1562 {
1563 bRet = FALSE;
1564 }
1565 return bRet;
1566 }
1567
1568 //static MS_BOOL bVpuExReloadFW = TRUE;
1569 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1570 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1571 {
1572 pVPUHalContext->bVpuExReloadFW = bReload;
1573 //VPRINTF("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1574 return TRUE;
1575 }
1576
1577
1578 //-------------------------------------------------------------------------------------------------
1579 // Global Functions
1580 //-------------------------------------------------------------------------------------------------
1581 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1582 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1583 {
1584 #if HVD_ENABLE_RV_FEATURE
1585 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1586 {
1587 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1588 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1589 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1590
1591 if (pVlcCfg->u32BinSize)
1592 {
1593 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1594
1595 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1596 {
1597 cpyflag = E_SPIDMA_DEV_MIU1;
1598 }
1599 else
1600 {
1601 cpyflag = E_SPIDMA_DEV_MIU0;
1602 }
1603
1604 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1605 {
1606 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1607 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1608
1609 return FALSE;
1610 }
1611 }
1612 else
1613 {
1614 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1615 return FALSE;
1616 }
1617 #else
1618 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1619 return FALSE;
1620 #endif
1621 }
1622 else
1623 {
1624 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1625 {
1626 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1627 {
1628 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1629 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1630
1631 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1632 BDMA_Result bdmaRlt;
1633
1634 MsOS_FlushMemory();
1635 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1636
1637 if (E_BDMA_OK != bdmaRlt)
1638 {
1639 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1640 }
1641 #else
1642 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1643 #endif
1644 }
1645 else
1646 {
1647 VPU_MSG_ERR
1648 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1649 return FALSE;
1650 }
1651 }
1652 else
1653 {
1654 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1655 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1656 MS_U8 *pu8HVD_VLC_Binary;
1657
1658 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1659
1660 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1661 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1662 (MS_U32) sizeof(u8HVD_VLC_Binary));
1663
1664 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1665 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1666 #else
1667 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1668 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1669 (MS_U32) sizeof(u8HVD_VLC_Binary));
1670
1671 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1672 #endif
1673 #else
1674 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1675 return FALSE;
1676 #endif
1677 }
1678 }
1679 #endif
1680
1681 return TRUE;
1682 }
1683 #endif
1684
1685
1686 #if (VPU_ENABLE_IQMEM)
HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara * pInitPara)1687 MS_BOOL HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara *pInitPara)
1688 {
1689
1690 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1691 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1692
1693
1694 MS_U32 u32Timeout = 20000;
1695
1696 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_NONE)
1697 {
1698
1699 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1700
1701
1702 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_LOADING;
1703
1704 while (u32Timeout)
1705 {
1706
1707 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_LOADED)
1708 {
1709 break;
1710 }
1711 u32Timeout--;
1712 MsOS_DelayTaskUs(1000);
1713 }
1714
1715 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1716
1717
1718 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_FINISH;
1719
1720 if (u32Timeout==0)
1721 {
1722 HVD_EX_MSG_ERR("Wait E_CTL_IQMEM_INIT_FINISH timeout !!\n");
1723 return FALSE;
1724 }
1725
1726 }
1727 return TRUE;
1728 }
1729
1730 #endif
1731
1732
1733
1734 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1735 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1736 #else
1737 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1738 #endif
1739 {
1740 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1741 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1742 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1743 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1744 MS_U32 u32Arg = 0xFFFFFFFF;
1745 MS_U32 u32Timeout = 0;
1746 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1747 MS_U32 u32CmdArg = 0;
1748 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1749 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1750
1751 _HAL_VPU_Entry();
1752 //Check FW buffer size
1753 if (1 == u8Offset)
1754 {
1755 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1756 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1757
1758 if (u32CurFWBuffSize < u32MinFWBuffSize)
1759 {
1760 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1761 _HAL_VPU_Release();
1762 return FALSE;
1763 }
1764 }
1765
1766 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1767 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1768 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1769 {
1770 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1771 }
1772 #ifdef VDEC3
1773 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1774 #endif
1775
1776 if (0 == pVPUHalContext->u8TaskCnt)
1777 {
1778 //No task is created, need to load f/w, etc.
1779 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1780
1781 if (!_VPU_EX_InitAll(pInitPara))
1782 {
1783 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1784 _HAL_VPU_Release();
1785 return FALSE;
1786 }
1787
1788 //Check if controller finish initialization: clear mailbox, etc.
1789 //Need to check it before sending any controller commands!
1790 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1791 while (CTL_STU_NONE == ctl_ptr->statue)
1792 {
1793 if (HVD_GetSysTime_ms() > u32Timeout)
1794 {
1795 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1796 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1797 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1798 MS_U32 t=0;
1799 for (t=0; t<30; t++)
1800 {
1801 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1802 }
1803 _HAL_VPU_Release();
1804 return FALSE;
1805 }
1806
1807 MsOS_ReadMemory();
1808 }
1809
1810 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1811 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1812
1813 }
1814 else
1815 {
1816 if (pVPUHalContext->_bVPUSingleMode)
1817 {
1818 //Show error message
1819 VPRINTF("This task will use dram instead of sram!!!\n");
1820 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1821 }
1822
1823 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1824 {
1825 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1826 _HAL_VPU_Release();
1827 return FALSE;
1828 }
1829 if (pInitPara->pVLCCfg)
1830 {
1831 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1832 {
1833 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1834 _HAL_VPU_Release();
1835 return FALSE;
1836 }
1837 }
1838 }
1839
1840
1841 #if (VPU_ENABLE_IQMEM)
1842
1843 if( ctl_ptr->bIsIQMEMSupport)
1844 {
1845
1846 HAL_VPU_EX_IQMem_Init(pInitPara);
1847 }
1848 else{
1849 VPU_MSG_ERR("not support IQMEM\n");
1850 }
1851
1852 #endif
1853
1854
1855 #ifdef VDEC_FW31_HVD_NONAUTO_BBU
1856 if (pVPUHalContext->u8TaskCnt == 0)
1857 {
1858 ctl_ptr->bEnableHvdNonAutoBBU = TRUE;
1859 MsOS_FlushMemory();
1860 }
1861 #endif
1862
1863
1864 #ifdef VDEC3
1865 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1866 {
1867 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1868
1869 memset(pTemp4,0,sizeof(VDEC_VBBU));
1870
1871 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1872
1873 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1874
1875 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1876
1877 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1878
1879 memset(pTemp2,0,sizeof(CMD_QUEUE));
1880
1881 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1882
1883 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1884
1885 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1886
1887 memset(pTemp3,0,0x2000);
1888
1889 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1890
1891 memset((void*)pVersion,0,0x8);
1892
1893 *pVersion = 1; //0:diu, 1:wb
1894 }
1895
1896 #endif
1897
1898 #if 1 // For TEE
1899 #ifdef VDEC3
1900 #if SUPPORT_G2VP9
1901 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1902 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1903 #else
1904 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1905 #endif
1906 #else
1907 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1908 #endif
1909 {
1910 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1911
1912 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1913 {
1914 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1915 }
1916 else
1917 {
1918 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1919 }
1920
1921 MsOS_FlushMemory();
1922 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1923
1924 ///VPRINTF("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1925 ///VPRINTF("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1926 }
1927 #endif
1928
1929 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1930 {
1931 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1932 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1933
1934 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1935
1936 MsOS_FlushMemory();
1937 }
1938
1939 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1940 {
1941 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1942 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1943 {
1944 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1945 }
1946 }
1947
1948 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1949 {
1950 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1951 //arg=1 to get better performance for single task
1952 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1953 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1954 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1955 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1956 {
1957 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1958 }
1959 }
1960 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1961 {
1962 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1963 {
1964 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1965 {
1966 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1967 u32CmdArg = CTL_MODE_3DTV;
1968 break;
1969 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1970 u32CmdArg = CTL_MODE_3DTV_PROG;
1971 break;
1972 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1973 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1974 break;
1975 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1976 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1977 break;
1978 default:
1979 u32CmdArg = CTL_MODE_3DTV;
1980 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1981 break;
1982 }
1983 }
1984 else
1985 {
1986 u32CmdArg = CTL_MODE_3DWMV;
1987 }
1988 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1989 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1990 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1991 {
1992 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1993 }
1994 }
1995 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1996 {
1997 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1998 {
1999 u32CmdArg = CTL_MODE_ONE_STC;
2000 }
2001 else
2002 {
2003 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
2004 }
2005 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
2006 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
2007 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
2008 {
2009 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
2010 }
2011 }
2012
2013 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
2014 #if defined(SUPPORT_NEW_MEM_LAYOUT)
2015 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2016 #ifdef VDEC3
2017 {
2018 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2019 }
2020 #else
2021 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2022 #endif
2023
2024 #ifdef VDEC3
2025 #if SUPPORT_G2VP9
2026 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2027 #else
2028 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2029 #endif
2030 {
2031 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2032 }
2033 #else
2034 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2035 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
2036 #endif
2037 else
2038 {
2039 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2040 _HAL_VPU_Release();
2041 return FALSE;
2042 }
2043 #else
2044 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
2045 #endif
2046
2047 /* VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset); */
2048 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
2049
2050 MsOS_ReadMemory();
2051 VPRINTF("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2052 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2053
2054 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2055 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2056 {
2057 if (HVD_GetSysTime_ms() > u32Timeout)
2058 {
2059 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2060 MS_U32 t=0;
2061 for (t=0; t<30; t++)
2062 {
2063 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
2064 }
2065 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2066 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2067 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2068 _HAL_VPU_Release();
2069 return FALSE;
2070 //#endif
2071 }
2072
2073 MsOS_ReadMemory();
2074 }
2075
2076 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2077 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2078
2079 #ifdef VDEC3
2080 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2081 #else
2082 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2083 #endif
2084 {
2085 HAL_HVD_EX_SetNalTblAddr(u32Id);
2086 }
2087
2088 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2089 {
2090 eDecType = E_VPU_EX_DECODER_MVD;
2091 }
2092 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2093 {
2094 eDecType = E_VPU_EX_DECODER_HVD;
2095 }
2096 #ifdef VDEC3
2097 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2098 {
2099 eDecType = E_VPU_EX_DECODER_EVD;
2100 }
2101 #if SUPPORT_G2VP9
2102 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2103 {
2104 eDecType = E_VPU_EX_DECODER_G2VP9;
2105 }
2106 #endif
2107 #endif
2108 else
2109 {
2110 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2111 _HAL_VPU_Release();
2112 return FALSE;
2113 }
2114
2115 #ifdef VDEC3
2116 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
2117 {
2118 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2119 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2120 }
2121 #endif
2122
2123 if (pTaskInfo->eDecType != eDecType)
2124 {
2125 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2126 pTaskInfo->eDecType, eDecType);
2127 }
2128 goto _SAVE_DEC_TYPE;
2129
2130 _SAVE_DEC_TYPE:
2131 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2132 {
2133 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
2134 }
2135 else
2136 {
2137 VPU_MSG_ERR("Cannot save eDecType!!\n");
2138 }
2139
2140 (pVPUHalContext->u8TaskCnt)++;
2141 _HAL_VPU_Release();
2142 return TRUE;
2143 }
2144
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2145 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2146 {
2147 HVD_Return eRet;
2148 #ifdef VDEC3
2149 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2150 #else
2151 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2152 #endif
2153 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2154 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2155
2156 _HAL_VPU_Entry();
2157 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2158
2159 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2160 if(eRet != E_HVD_RETURN_SUCCESS)
2161 {
2162 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2163 }
2164
2165 {
2166 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2167 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2168 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2169
2170 MsOS_ReadMemory();
2171
2172 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2173 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2174
2175 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2176 {
2177 if (HVD_GetSysTime_ms() > u32Timeout)
2178 {
2179 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2180 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2181 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2182
2183 if(pVPUHalContext->u8TaskCnt == 1)
2184 {
2185 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2186 break;
2187 }
2188 else if(pVPUHalContext->u8TaskCnt == 2)
2189 {
2190 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2191 break;
2192 }
2193 else
2194 {
2195 VPU_MSG_ERR("Task number is not correct\n");
2196 _HAL_VPU_Release();
2197 return FALSE;
2198 }
2199 }
2200
2201 MsOS_ReadMemory();
2202 }
2203
2204 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2205 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2206 }
2207 #if SUPPORT_EVD
2208 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2209 {
2210 HAL_EVD_EX_ClearTSPInput(u32Id);
2211 }
2212 #endif
2213
2214 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2215 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2216 {
2217 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2218 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2219 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2220 }
2221
2222 if (pVPUHalContext->u8TaskCnt)
2223 {
2224 (pVPUHalContext->u8TaskCnt)--;
2225 }
2226 else
2227 {
2228 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2229 }
2230
2231 if (0 == pVPUHalContext->u8TaskCnt)
2232 {
2233 int i;
2234 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2235 _VPU_EX_DeinitAll(pInitPara);
2236 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2237 pVPUHalContext->u32VPUSHMAddr = 0;
2238
2239 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2240 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2241 }
2242 else
2243 {
2244 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2245 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2246 }
2247
2248 _HAL_VPU_Release();
2249 return TRUE;
2250 }
2251
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2252 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2253 {
2254 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2255 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2256 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2257 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2258 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2259 #endif
2260
2261 if (FALSE == HAL_VPU_EX_GetFWReload())
2262 {
2263 //VPRINTF("%s bFWReload FALSE!!!\n", __FUNCTION__);
2264 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2265 {
2266 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2267 }
2268 else
2269 {
2270 //Check f/w prefix "VDEC30"
2271 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2272 {
2273 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2274 }
2275 else
2276 {
2277 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2278 return TRUE;
2279 }
2280 }
2281 }
2282
2283 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2284 {
2285 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2286 if (u32Size != 0)
2287 {
2288 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2289
2290
2291 MS_U32 u32Start;
2292 MS_U32 u32StartOffset;
2293 MS_U8 u8MiuSel;
2294
2295 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2296
2297
2298 if(u8MiuSel == E_CHIP_MIU_0)
2299 cpyflag = E_SPIDMA_DEV_MIU0;
2300 else if(u8MiuSel == E_CHIP_MIU_1)
2301 cpyflag = E_SPIDMA_DEV_MIU1;
2302 else if(u8MiuSel == E_CHIP_MIU_2)
2303 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2304
2305 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2306 {
2307 goto _load_code_fail;
2308 }
2309 }
2310 else
2311 {
2312 goto _load_code_fail;
2313 }
2314 #else
2315 goto _load_code_fail;
2316 #endif
2317 }
2318 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2319 {
2320 if (u32BinAddr != 0 && u32Size != 0)
2321 {
2322 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2323 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2324 {
2325 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2326 {
2327 VPU_MSG_INFO("Decompress ok!!!\n");
2328 }
2329 else
2330 {
2331 VPU_MSG_INFO("Decompress fail!!!\n");
2332 }
2333 }
2334 else
2335 #endif
2336 {
2337 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2338 }
2339 }
2340 else
2341 {
2342 goto _load_code_fail;
2343 }
2344 }
2345 else
2346 {
2347 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2348 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2349 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2350 (MS_U32) sizeof(u8HVD_FW_Binary));
2351
2352 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2353 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2354 {
2355 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2356 {
2357 VPU_MSG_INFO("Decompress ok!!!\n");
2358 }
2359 else
2360 {
2361 VPU_MSG_INFO("Decompress fail!!!\n");
2362 }
2363 }
2364 else
2365 #endif
2366 {
2367 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2368 }
2369 #else
2370 goto _load_code_fail;
2371 #endif
2372 }
2373
2374 MAsm_CPU_Sync();
2375 MsOS_FlushMemory();
2376
2377 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2378 {
2379 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2380 goto _load_code_fail;
2381 }
2382
2383 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2384 return TRUE;
2385
2386 _load_code_fail:
2387 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2388 return FALSE;
2389 }
2390
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2391 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2392 {
2393 u32VPURegOSBase = u32RegBase;
2394 }
2395
HAL_VPU_EX_Init_Share_Mem(void)2396 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2397 {
2398 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2399
2400 MS_U32 u32ShmId;
2401 MS_VIRT u32Addr;
2402 MS_U32 u32BufSize;
2403
2404
2405 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2406 sizeof(VPU_Hal_CTX),
2407 &u32ShmId,
2408 &u32Addr,
2409 &u32BufSize,
2410 MSOS_SHM_QUERY))
2411 {
2412 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2413 sizeof(VPU_Hal_CTX),
2414 &u32ShmId,
2415 &u32Addr,
2416 &u32BufSize,
2417 MSOS_SHM_CREATE))
2418 {
2419 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2420 if(pVPUHalContext == NULL)
2421 {
2422 pVPUHalContext = &gVPUHalContext;
2423 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2424 _VPU_EX_Context_Init();
2425 VPRINTF("[%s]Global structure init Success!!!\n",__FUNCTION__);
2426 }
2427 else
2428 {
2429 VPRINTF("[%s]Global structure exists!!!\n",__FUNCTION__);
2430 }
2431 //return FALSE;
2432 }
2433 else
2434 {
2435 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2436 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2437 _VPU_EX_Context_Init();
2438 }
2439 }
2440 else
2441 {
2442 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2443 }
2444 #else
2445 if(pVPUHalContext == NULL)
2446 {
2447 pVPUHalContext = &gVPUHalContext;
2448 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2449 _VPU_EX_Context_Init();
2450 }
2451 #endif
2452
2453 return TRUE;
2454
2455 }
2456
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2457 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2458 {
2459 MS_U32 i = 0;
2460
2461 _HAL_VPU_MutexCreate();
2462
2463 _HAL_VPU_Entry();
2464
2465 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2466 {
2467 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2468 {
2469 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2470 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2471 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2472 _HAL_VPU_Release();
2473 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2474 }
2475 }
2476 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2477 {
2478 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2479 {
2480 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2481 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2482 {
2483 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2484 _HAL_VPU_Release();
2485 return pVPUHalContext->_stVPUStream[i].eStreamId;
2486 }
2487 }
2488 }
2489 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2490 {
2491 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2492 {
2493 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2494 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2495 {
2496 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2497 _HAL_VPU_Release();
2498 return pVPUHalContext->_stVPUStream[i].eStreamId;
2499 }
2500 }
2501 }
2502 #ifdef VDEC3
2503 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2504 {
2505 #if 1 // bound FW task to main/sub stream
2506 i = eStreamType - E_HAL_VPU_N_STREAM;
2507 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2508 {
2509 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2510 _HAL_VPU_Release();
2511 return pVPUHalContext->_stVPUStream[i].eStreamId;
2512 }
2513 #else // dynamic select FW task id
2514 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2515 {
2516 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2517 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2518 {
2519 return pVPUHalContext->_stVPUStream[i].eStreamId;
2520 }
2521 }
2522 #endif
2523 }
2524 #endif
2525
2526 _HAL_VPU_Release();
2527
2528 return E_HAL_VPU_STREAM_NONE;
2529 }
2530
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2531 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2532 {
2533 _HAL_VPU_Entry();
2534
2535 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2536 {
2537 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2538 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2539 }
2540 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2541 {
2542 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2543 }
2544
2545 _HAL_VPU_Release();
2546
2547 return TRUE;
2548 }
2549
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2550 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2551 {
2552 MS_U8 u8Idx = 0;
2553
2554 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2555
2556 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2557 {
2558 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2559 {
2560 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2561 return 0;
2562 }
2563 }
2564 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2565 {
2566 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2567 {
2568 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2569 return 1;
2570 }
2571 }
2572
2573 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2574 {
2575 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2576 break;
2577 }
2578
2579 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2580 {
2581 VPU_MSG_ERR("all vpu free streams are occupied \n");
2582 return 0xFF;
2583 }
2584
2585 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2586 return u8Idx;
2587 }
2588
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2589 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2590 {
2591 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2592
2593 // enable module
2594 _VPU_EX_ClockInv(InitParams->bClockInv);
2595 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2596 HAL_VPU_EX_PowerCtrl(TRUE);
2597
2598 #ifdef CONFIG_MSTAR_CLKM
2599 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2600 #endif
2601
2602 #ifdef CONFIG_MSTAR_SRAMPD
2603 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2604 HVD_Delay_ms(1);
2605 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2606 HVD_Delay_ms(1);
2607 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2608 HVD_Delay_ms(1);
2609 #endif
2610 #if 1 //Create VPU's own mutex
2611 //_HAL_VPU_MutexCreate();
2612 #else
2613 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2614 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2615 #endif
2616
2617 return TRUE;
2618 }
2619
HAL_VPU_EX_DeInit(void)2620 MS_BOOL HAL_VPU_EX_DeInit(void)
2621 {
2622 if (0 != _VPU_EX_GetActiveCodecCnt())
2623 {
2624 VPU_MSG_DBG("do nothing since codec is active.\n");
2625 return TRUE;
2626 }
2627
2628 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2629
2630 #ifdef CONFIG_MSTAR_CLKM
2631 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2632 #else
2633 HAL_VPU_EX_PowerCtrl(FALSE);
2634 #endif
2635
2636 #ifdef CONFIG_MSTAR_SRAMPD
2637 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2638 HVD_Delay_ms(1);
2639 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2640 HVD_Delay_ms(1);
2641 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2642 HVD_Delay_ms(1);
2643 #endif
2644
2645 HAL_VPU_EX_SwRelseMAU();
2646 //_HAL_VPU_MutexDelete();
2647
2648 return TRUE;
2649 }
2650
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2651 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2652 {
2653 if (bEnable)
2654 {
2655 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2656 _VPU_WriteWordMask(REG_TOP_VPU, VPU_ICG_EN, VPU_ICG_EN);
2657 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2658 pVPUHalContext->_bVPUPowered = TRUE;
2659 }
2660 else
2661 {
2662 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2663 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2664 pVPUHalContext->_bVPUPowered = FALSE;
2665 }
2666 }
2667
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2668 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2669 {
2670 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2671 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2672 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2673 VPU_EX_TimerDelayMS(1);
2674 }
2675
2676 ///-----------------------------------------------------------------------------
2677 /// config AVCH264 CPU
2678 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2679 /// @param u8dlend_en \b IN: endian
2680 /// - 1, little endian
2681 /// - 0, big endian
2682 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2683 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2684 {
2685 MS_BOOL bRet = TRUE;
2686 MS_U32 u32Offset = 0;
2687 MS_U16 tempreg = 0;
2688 MS_U8 u8MiuSel;
2689 //MS_U32 u32TmpStartOffset;
2690
2691 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2692
2693 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2694 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2695 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2696 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2697 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2698 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2699 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2700 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2701 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2702 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2703
2704 #if (VPU_ENABLE_IQMEM)
2705 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2706 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2707 #endif
2708
2709 #if (VPU_FORCE_MIU_MODE)
2710 // Data sram base Unit: byte address
2711 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2712 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2713 // Instruction sram base Unit: byte address
2714 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2715 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2716
2717 #ifndef HAL_FEATURE_MAU
2718 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2719 #endif
2720 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2721
2722 //use force miu mode
2723 if(u8MiuSel == E_CHIP_MIU_0)
2724 {
2725 #ifdef HAL_FEATURE_MAU
2726 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2727 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2728 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2729 #else
2730 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2731 #endif
2732 }
2733 else if(u8MiuSel == E_CHIP_MIU_1)
2734 {
2735 #ifdef HAL_FEATURE_MAU
2736 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2737 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2738 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2739 #else
2740 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2741 #endif
2742 }
2743 else //miu 2
2744 {
2745 #ifdef HAL_FEATURE_MAU
2746 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2747 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2748 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2749 #else
2750 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2751 #endif
2752 }
2753 #else
2754 ///TODO:
2755 #endif
2756
2757
2758 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2759 tempreg |= VPU_REG_IO2_EN;
2760 tempreg |= VPU_REG_QMEM_SPACE_EN;
2761 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2762
2763 return bRet;
2764 }
2765
2766 ///-----------------------------------------------------------------------------
2767 /// Set IQMem data access mode or instruction fetch mode
2768 /// @param u8dlend_en \b IN: endian
2769 /// - 1, switch to data access mode
2770 /// - 0, switch to instruction fetch mode
2771 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2772 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2773 {
2774
2775 if(bEnable){
2776
2777 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2778 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)|0x20);
2779
2780 }
2781 else{
2782
2783 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& (~0x10));
2784 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)& (~0x20));
2785 }
2786 }
2787
2788 ///-----------------------------------------------------------------------------
2789 /// H.264 SW reset
2790 /// @return TRUE or FALSE
2791 /// - TRUE, Success
2792 /// - FALSE, Failed
2793 ///-----------------------------------------------------------------------------
2794
2795
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2796 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2797 {
2798 MS_U16 tempreg = 0, tempreg1 = 0;
2799 MS_U16 idle_cnt;
2800 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2801 tempreg |= VPU_REG_CPU_STALL_EN;
2802 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2803
2804 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2805 // 0xf means VPU is not stalled
2806 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2807 pVPUHalContext->u8ForceRst = 0;
2808 // write R2 RIU registers to select DCU/ICU debug data
2809 // Writing these registers here provides enough time for them to
2810 // take effect.
2811 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2812 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2813 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2814 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2815
2816 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2817 // This step is important because in the next step we want to make
2818 // sure "DCU is not replaying when R2 is stalled".
2819 idle_cnt = 100;
2820 do
2821 {
2822 if (--idle_cnt == 0)
2823 {
2824 VPRINTF("VPU_REG_CPU_STALL_EN is not set\n");
2825 break;
2826 }
2827 MsOS_DelayTask(1);
2828 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2829 // check CPU status: DCU should NOT be replaying
2830 // If R2 has been stalled, we can guarantee that if we found DCU is
2831 // NOT replaying, it will NOT replay later even CPU is going to issue
2832 // a load/store instruction.
2833 idle_cnt = 100;
2834 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2835 {
2836 if (--idle_cnt == 0)
2837 {
2838 VPRINTF("DCU is replaying\n");
2839 break;
2840 }
2841 MsOS_DelayTask(1);
2842 }
2843 // wait 1ms to prevent race condition between (1) DCU is not
2844 // replaying, and (2) BIU start to doing new job or ICU start to
2845 // fetch new instruction
2846 MsOS_DelayTask(1);
2847
2848 // check BIU should be empty
2849 idle_cnt = 100;
2850 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2851 {
2852 if (--idle_cnt == 0)
2853 {
2854 VPRINTF("BIU DCU idle time out~~~~~\n");
2855 break;
2856 }
2857 MsOS_DelayTask(1);
2858 }
2859
2860 // check CPU is not requesting ICU
2861 idle_cnt = 100;
2862 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2863 {
2864 if (--idle_cnt == 0)
2865 {
2866 VPRINTF("CPU keeps requesting ICU\n");
2867 break;
2868 }
2869 MsOS_DelayTask(1);
2870 }
2871
2872 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2873 // (2) ISB start to fetch
2874 MsOS_DelayTask(1);
2875
2876 // check ISB should be idle
2877 idle_cnt = 100;
2878 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2879 {
2880 if (--idle_cnt == 0)
2881 {
2882 VPRINTF("ISB is busy\n");
2883 break;
2884 }
2885 MsOS_DelayTask(1);
2886 }
2887 }
2888 #ifdef HAL_FEATURE_MAU
2889 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2890 if (bCheckMauIdle)
2891 {
2892 MS_U32 mau_idle_cnt = 100;// ms
2893 while (mau_idle_cnt)
2894 {
2895 if (TRUE == _VPU_EX_MAU_IDLE())
2896 {
2897 break;
2898 }
2899 mau_idle_cnt--;
2900 MsOS_DelayTask(1);
2901 }
2902
2903 if (mau_idle_cnt == 0)
2904 {
2905 VPRINTF("MAU idle time out~~~~~\n");
2906 }
2907 }
2908 #endif
2909
2910 // this command set MIU to block R2 (does not ack R2's request)
2911 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2912
2913 #ifdef HAL_FEATURE_MAU
2914 // reset MAU
2915 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2916 tempreg1 |= MAU1_REG_SW_RESET;
2917 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2918 #if defined(UDMA_FPGA_ENVI)
2919 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2920 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2921 #endif
2922 #endif
2923
2924 // reset R2
2925 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2926 // by the same RIU write, the R2 reset signal may reach afifo eralier
2927 // than MIU reset and afifo write pointer will be reset to position 0.
2928 // In this case, afifo consider it is not empty because read/write
2929 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2930 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2931 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2932 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2933 VPU_EX_TimerDelayMS(1);
2934 tempreg &= ~VPU_REG_CPU_R2_EN;
2935 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2936 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2937
2938 VPU_EX_TimerDelayMS(1);
2939
2940 // this command set MIU to accept R2 (can ack R2's request)
2941 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2942
2943 pVPUHalContext->_bVPURsted = FALSE;
2944 return TRUE;
2945 }
2946
2947
2948
2949 /*
2950 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2951 {
2952 MS_U16 tempreg = 0, tempreg1 = 0;
2953 #ifndef HAL_FEATURE_MAU
2954 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2955 tempreg |= VPU_REG_CPU_STALL_EN;
2956 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2957
2958 MS_U32 idle_cnt = 100;// ms
2959 while (idle_cnt)
2960 {
2961 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2962 {
2963 break;
2964 }
2965 idle_cnt--;
2966 MsOS_DelayTask(1);
2967 }
2968
2969 if (idle_cnt == 0)
2970 {
2971 VPRINTF("ISB ICU idle time out~~~~~\n");
2972 }
2973
2974 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2975 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2976 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2977 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2978
2979 MS_U32 idle_cnt_1 = 100;// ms
2980 while (idle_cnt_1)
2981 {
2982 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2983 {
2984 break;
2985 }
2986 idle_cnt_1--;
2987 MsOS_DelayTask(1);
2988 }
2989
2990 if (idle_cnt_1 == 0)
2991 {
2992 VPRINTF("BIU DCU idle time out~~~~~\n");
2993 }
2994
2995 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2996 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2997 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2998 VPU_EX_TimerDelayMS(1);
2999 tempreg &= ~VPU_REG_CPU_R2_EN;
3000 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3001 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3002
3003 #else
3004 //MAU has been removed since manhattan, so it is not necessary to check MAU status
3005
3006 if (bCheckMauIdle)
3007 {
3008 MS_U32 mau_idle_cnt = 100;// ms
3009 while (mau_idle_cnt)
3010 {
3011 if (TRUE == _VPU_EX_MAU_IDLE())
3012 {
3013 break;
3014 }
3015 mau_idle_cnt--;
3016 MsOS_DelayTask(1);
3017 }
3018
3019 if (mau_idle_cnt == 0)
3020 {
3021 VPRINTF("MAU idle time out~~~~~\n");
3022 }
3023 }
3024
3025
3026 HAL_VPU_EX_MIU_RW_Protect(TRUE);
3027
3028 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3029 tempreg1 |= MAU1_REG_SW_RESET;
3030 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3031
3032 #if defined(UDMA_FPGA_ENVI)
3033 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3034 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3035 #endif
3036
3037 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3038 tempreg &= ~VPU_REG_CPU_R2_EN;
3039 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3040 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3041 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3042 #endif
3043 VPU_EX_TimerDelayMS(1);
3044 HAL_VPU_EX_MIU_RW_Protect(FALSE);
3045
3046 pVPUHalContext->_bVPURsted = FALSE;
3047 return TRUE;
3048 }
3049 */
3050 ///-----------------------------------------------------------------------------
3051 /// CPU reset release
3052 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)3053 void HAL_VPU_EX_SwRstRelse(void)
3054 {
3055 MS_U16 tempreg = 0;
3056
3057 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
3058 tempreg &= ~VPU_REG_CPU_STALL_EN;
3059 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
3060
3061 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3062 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3063 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3064 VPU_EX_TimerDelayMS(1);
3065 tempreg |= VPU_REG_CPU_SW_RSTZ;
3066 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3067 VPU_EX_TimerDelayMS(1);
3068 tempreg |= VPU_REG_CPU_R2_EN;
3069 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3070 #ifdef HAL_FEATURE_MAU
3071 MS_U16 tempreg1 = 0;
3072 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3073 tempreg1 &= ~MAU1_REG_SW_RESET;
3074 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3075 #endif
3076 pVPUHalContext->_bVPURsted = TRUE;
3077 }
3078
HAL_VPU_EX_SwRelseMAU(void)3079 void HAL_VPU_EX_SwRelseMAU(void)
3080 {
3081
3082 #ifdef HAL_FEATURE_MAU
3083 MS_U16 tempreg = 0;
3084 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
3085 tempreg &= ~MAU1_REG_SW_RESET;
3086 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
3087 #endif
3088 }
3089
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3090 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3091 {
3092 MS_U32 u32value = 0;
3093
3094 return u32value;
3095 }
3096
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3097 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3098 {
3099 MS_BOOL bRet = TRUE;
3100
3101 return bRet;
3102 }
3103
3104 ///-----------------------------------------------------------------------------
3105 /// Check AVCH264 Ready or not
3106 /// @return TRUE or FALSE
3107 /// - TRUE, MailBox is free
3108 /// - FALSE, MailBox is busy
3109 /// @param u8MBox \b IN: MailBox to check
3110 /// - AVCH264_HI_MBOX0,
3111 /// - AVCH264_HI_MBOX1,
3112 /// - AVCH264_RISC_MBOX0,
3113 /// - AVCH264_RISC_MBOX1,
3114 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)3115 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
3116 {
3117 MS_BOOL bResult = FALSE;
3118
3119 switch (u32type)
3120 {
3121 case VPU_HI_MBOX0:
3122 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3123 break;
3124 case VPU_HI_MBOX1:
3125 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3126 break;
3127 case VPU_RISC_MBOX0:
3128 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3129 break;
3130 case VPU_RISC_MBOX1:
3131 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3132 break;
3133 default:
3134 break;
3135 }
3136 return bResult;
3137 }
3138
3139
3140 ///-----------------------------------------------------------------------------
3141 /// Read message from AVCH264
3142 /// @return TRUE or FALSE
3143 /// - TRUE, success
3144 /// - FALSE, failed
3145 /// @param u8MBox \b IN: MailBox to read
3146 /// - AVCH264_RISC_MBOX0
3147 /// - AVCH264_RISC_MBOX1
3148 /// @param u32Msg \b OUT: message read
3149 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)3150 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
3151 {
3152 MS_BOOL bResult = TRUE;
3153
3154 switch (u32type)
3155 {
3156 case VPU_HI_MBOX0:
3157 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3158 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3159 break;
3160 case VPU_HI_MBOX1:
3161 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3162 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3163 break;
3164 case VPU_RISC_MBOX0:
3165 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3166 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3167 break;
3168 case VPU_RISC_MBOX1:
3169 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3170 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3171 break;
3172 default:
3173 *u32Msg = 0;
3174 bResult = FALSE;
3175 break;
3176 }
3177 return bResult;
3178 }
3179
3180 ///-----------------------------------------------------------------------------
3181 /// Mailbox from AVCH264 clear bit resest
3182 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3183 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3184 {
3185 switch (u32type)
3186 {
3187 case VPU_RISC_MBOX0:
3188 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3189 break;
3190 case VPU_RISC_MBOX1:
3191 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3192 break;
3193 default:
3194 break;
3195 }
3196 }
3197
3198 ///-----------------------------------------------------------------------------
3199 /// Send message to AVCH264
3200 /// @return TRUE or FALSE
3201 /// - TRUE, Success
3202 /// - FALSE, Failed
3203 /// @param u8MBox \b IN: MailBox
3204 /// - AVCH264_HI_MBOX0,
3205 /// - AVCH264_HI_MBOX1,
3206 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3207 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3208 {
3209 MS_BOOL bResult = TRUE;
3210
3211 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3212
3213 switch (u32type)
3214 {
3215 case VPU_HI_MBOX0:
3216 {
3217 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3218 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3219 break;
3220 }
3221 case VPU_HI_MBOX1:
3222 {
3223 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3224 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3225 break;
3226 }
3227 default:
3228 {
3229 bResult = FALSE;
3230 break;
3231 }
3232 }
3233
3234 return bResult;
3235 }
3236
HAL_VPU_EX_GetProgCnt(void)3237 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3238 {
3239
3240 MS_U16 expc_l=0;
3241 MS_U16 expc_h=0;
3242 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3243 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3244 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3245 }
3246
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3247 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3248 {
3249 return _VPU_EX_GetOffsetIdx(u32Id);
3250 }
3251
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3252 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3253 {
3254 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3255
3256 if (u32ShmAddr == 0)
3257 {
3258 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3259 }
3260 else
3261 {
3262 if (u8Offset == 0)
3263 {
3264 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3265 }
3266 else if (u8Offset == 1)
3267 {
3268 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3269 }
3270 }
3271
3272 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3273 return;
3274 }
3275
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3276 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3277 {
3278 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3279
3280 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3281 }
3282
3283 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3284 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3285 {
3286 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3287 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3288 MS_VIRT VsyncBridgeOffset = 0;
3289
3290 if (VPUSHMAddr != 0) // TEE project
3291 {
3292 if ((u8Offset == 0) || (u8Offset == 1))
3293 {
3294 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3295 }
3296 else
3297 {
3298 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3299 }
3300 }
3301 else // normal project
3302 {
3303 if ((u8Offset == 0) || (u8Offset == 1))
3304 {
3305 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3306 }
3307 else
3308 {
3309 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3310 }
3311 }
3312
3313 return VsyncBridgeOffset;
3314 }
3315
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3316 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3317 {
3318 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3319 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3320 MS_VIRT VsyncBridgeExtOffset = 0;
3321
3322 if (VPUSHMAddr != 0) // TEE project
3323 {
3324 if ((u8Offset == 0) || (u8Offset == 1))
3325 {
3326 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3327 }
3328 else
3329 {
3330 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3331 }
3332 }
3333 else // normal project
3334 {
3335 if ((u8Offset == 0) || (u8Offset == 1))
3336 {
3337 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3338 }
3339 else
3340 {
3341 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3342 }
3343 }
3344
3345 return VsyncBridgeExtOffset;
3346 }
3347 #endif
3348
HAL_VPU_EX_IsPowered(void)3349 MS_BOOL HAL_VPU_EX_IsPowered(void)
3350 {
3351 return pVPUHalContext->_bVPUPowered;
3352 }
3353
HAL_VPU_EX_IsRsted(void)3354 MS_BOOL HAL_VPU_EX_IsRsted(void)
3355 {
3356 return pVPUHalContext->_bVPURsted;
3357 }
3358
HAL_VPU_EX_IsEVDR2(void)3359 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3360 {
3361 #ifdef EVDR2
3362 return TRUE;
3363 #else
3364 return FALSE;
3365 #endif
3366 }
3367
HAL_VPU_EX_MVDInUsed(void)3368 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3369 {
3370 //MVD is in used for MVD or HVD_TSP mode.
3371 MS_U8 i;
3372 MS_U8 u8UseCnt = 0;
3373
3374 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3375 {
3376 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3377 #ifdef VDEC3
3378 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3379 #endif
3380 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3381 {
3382 u8UseCnt++;
3383 }
3384 }
3385
3386 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3387
3388 if (u8UseCnt != 0)
3389 {
3390 return TRUE;
3391 }
3392 else
3393 {
3394 return FALSE;
3395 }
3396 }
3397
HAL_VPU_EX_HVDInUsed(void)3398 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3399 {
3400 //HVD is in used for HVD or MVD in sub stream.
3401 MS_U8 i;
3402 MS_U8 u8UseCnt = 0;
3403 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3404 {
3405
3406 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype))
3407 {
3408 u8UseCnt++;
3409 }
3410 }
3411
3412 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3413
3414 if (u8UseCnt != 0)
3415 {
3416 return TRUE;
3417 }
3418 else
3419 {
3420 return FALSE;
3421 }
3422 }
3423
HAL_VPU_EX_Mutex_Lock(void)3424 void HAL_VPU_EX_Mutex_Lock(void)
3425 {
3426 _HAL_VPU_Entry();
3427 }
3428
HAL_VPU_EX_Mutex_UnLock(void)3429 void HAL_VPU_EX_Mutex_UnLock(void)
3430 {
3431 _HAL_VPU_Release();
3432 }
3433
3434 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3435 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3436 {
3437 MS_U8 i;
3438 MS_U8 u8UseCnt = 0;
3439
3440 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3441 {
3442 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3443 {
3444 u8UseCnt++;
3445 }
3446 }
3447
3448 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3449
3450 if (u8UseCnt != 0)
3451 {
3452 return TRUE;
3453 }
3454 else
3455 {
3456 return FALSE;
3457 }
3458 }
3459
3460 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3461 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3462 {
3463 MS_U8 i;
3464 MS_U8 u8UseCnt = 0;
3465
3466 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3467 {
3468 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3469 {
3470 u8UseCnt++;
3471 }
3472 }
3473
3474 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3475
3476 if (u8UseCnt != 0)
3477 {
3478 return TRUE;
3479 }
3480 else
3481 {
3482 return FALSE;
3483 }
3484 }
3485 #endif
3486 #endif
3487
3488 //-----------------------------------------------------------------------------
3489 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3490 /// @brief \b Function \b Description: Set debug level
3491 /// @param -elevel \b IN : debug level
3492 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3493 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3494 {
3495 VPRINTF("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3496
3497 switch (eLevel)
3498 {
3499 case E_VPU_EX_UART_LEVEL_ERR:
3500 {
3501 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3502 break;
3503 }
3504 case E_VPU_EX_UART_LEVEL_INFO:
3505 {
3506 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3507 break;
3508 }
3509 case E_VPU_EX_UART_LEVEL_DBG:
3510 {
3511 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3512 break;
3513 }
3514 case E_VPU_EX_UART_LEVEL_TRACE:
3515 {
3516 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3517 break;
3518 }
3519 case E_VPU_EX_UART_LEVEL_FW:
3520 {
3521 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3522 break;
3523 }
3524 default:
3525 {
3526 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3527 break;
3528 }
3529 }
3530 }
3531
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3532 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3533 {
3534 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3535 MS_U32 u32CmdArg = (MS_U32)eVerType;
3536 MS_U32 u32Version = 0xFFFFFFFF;
3537 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3538 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3539 {
3540 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3541 return u32Version;
3542 }
3543
3544 MS_BOOL bRet = false;
3545 MS_U32 u32TimeOut = 0xFFFFFFFF;
3546
3547 while(--u32TimeOut)
3548 {
3549 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3550 {
3551 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3552 if (false == bRet)
3553 {
3554 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3555 return u32Version;
3556 }
3557
3558 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3559 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3560 return u32Version;
3561 }
3562 }
3563
3564 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3565
3566 return u32Version;
3567 }
3568
HAL_VPU_EX_NotSupportDS(void)3569 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3570 {
3571 return FALSE;// maserati disable SN DS
3572 }
3573
3574 //-----------------------------------------------------------------------------
3575 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3576 /// @brief \b Function \b Description: Get VPU MIU base address
3577 /// @return - vpu MIU1 base
3578 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3579 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3580 {
3581 return VPU_MIU1BASE_ADDR;
3582 }
3583
3584
HAL_VPU_EX_GetSHMAddr(void)3585 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3586 {
3587 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3588 {
3589 return 0;
3590 }
3591 return pVPUHalContext->u32VPUSHMAddr;
3592 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3593 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3594 {
3595 pVPUHalContext->bEnableVPUSecureMode = enable;
3596 return TRUE;
3597 }
3598
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3599 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3600 {
3601 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3602
3603 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3604 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3605 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3606 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3607 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3608 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3609 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3610 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3611
3612 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3613 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3614 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3615 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3616 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3617 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3618 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3619 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3620 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3621 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3622
3623 return TRUE;
3624 }
3625
3626 //-----------------------------------------------------------------------------
3627 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3628 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3629 /// @return - success/fail
3630 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3631 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3632 {
3633 #define MAX_CAPABILITY_INFO_NUM 8
3634 #define MAX_CODEC_TYPE_NUM 18
3635
3636 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3637 {
3638 //width, height , frmrate, profile, level, version bit rate reserved2
3639 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3640 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3641 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3642 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3643 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3644 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3645 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3646 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 45, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3647 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 45, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3648 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3649 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3650 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_H264
3651 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 60, 0},//E_HVD_EX_CODEC_TYPE_AVS
3652 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3653 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_MVC
3654 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3655 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3656 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_VP9
3657 };
3658
3659 if(eCodecType < MAX_CODEC_TYPE_NUM)
3660 {
3661 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3662 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3663 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3664 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3665 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3666 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3667 return TRUE;
3668 }
3669 else
3670 {
3671 return FALSE;
3672 }
3673 }
3674
3675 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3676 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3677 {
3678 (void) u32Id;
3679 BBU_STATE *bbu_state;
3680
3681 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3682 || (eDecType == E_VPU_EX_DECODER_VP8)
3683 #if SUPPORT_G2VP9
3684 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3685 #endif
3686 )
3687 {
3688 // MVD should not call this function.
3689 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3690 return;
3691 }
3692
3693 switch (eDecType)
3694 {
3695 case E_VPU_EX_DECODER_EVD:
3696 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3697 break;
3698 case E_VPU_EX_DECODER_HVD:
3699 case E_VPU_EX_DECODER_RVD:
3700 case E_VPU_EX_DECODER_MVC:
3701 default:
3702 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3703 break;
3704 }
3705
3706 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3707 return;
3708 }
3709
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3710 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3711 {
3712 (void) u32Id;
3713 BBU_STATE *bbu_state;
3714
3715 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3716 || (eDecType == E_VPU_EX_DECODER_VP8)
3717 #if SUPPORT_G2VP9
3718 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3719 #endif
3720 )
3721 {
3722 // MVD should not call this function.
3723 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3724 return TRUE;
3725 }
3726
3727 switch (eDecType)
3728 {
3729 case E_VPU_EX_DECODER_EVD:
3730 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3731 break;
3732 case E_VPU_EX_DECODER_HVD:
3733 case E_VPU_EX_DECODER_RVD:
3734 case E_VPU_EX_DECODER_MVC:
3735 default:
3736 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3737 break;
3738 }
3739
3740 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3741 }
3742
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3743 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3744 {
3745 (void) u32Id;
3746 BBU_STATE *bbu_state;
3747
3748 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3749 || (eDecType == E_VPU_EX_DECODER_VP8)
3750 #if SUPPORT_G2VP9
3751 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3752 #endif
3753 )
3754 {
3755 // MVD should not call this function.
3756 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3757 return;
3758 }
3759
3760 switch (eDecType)
3761 {
3762 case E_VPU_EX_DECODER_EVD:
3763 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3764 break;
3765 case E_VPU_EX_DECODER_HVD:
3766 case E_VPU_EX_DECODER_RVD:
3767 case E_VPU_EX_DECODER_MVC:
3768 default:
3769 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3770 break;
3771 }
3772
3773 if (bbu_state[u32BBUId].u32Used == 0)
3774 {
3775 bbu_state[u32BBUId].u8RegSetting = 0;
3776 }
3777
3778 return;
3779 }
3780
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3781 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3782 {
3783 MS_U32 i, max_bbu_cnt;
3784 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3785
3786 if(pTaskInfo == NULL)
3787 return retBBUId;
3788
3789 BBU_STATE *bbu_state;
3790 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3791 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3792
3793 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3794
3795 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3796
3797 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3798 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3799 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3800
3801 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3802 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3803
3804 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3805 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3806 */
3807 #if 1
3808 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3809 {
3810 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3811 if (bTSP)
3812 {
3813 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3814 {
3815 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3816 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3817 slq_state[u8TaskId].bTSP = TRUE;
3818 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3819 return u8TaskId;
3820 }
3821 }
3822 else
3823 {
3824 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3825 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3826 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3827 {
3828 if (slq_state[i].u32Used != 0)
3829 {
3830 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3831 {
3832 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3833 }
3834 }
3835 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3836 {
3837 avaliable_bbu_idx = i; // recored the first empty bbu
3838 }
3839 }
3840
3841 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3842
3843 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3844 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3845 slq_state[shared_bbu_idx].bTSP = FALSE;
3846 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3847 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3848 return shared_bbu_idx;
3849 }
3850 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3851 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3852 slq_state[u8TaskId].bTSP = FALSE;
3853 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3854
3855 if (bShareBBU == FALSE)
3856 {
3857 slq_state[u8TaskId].bTSP = TRUE;
3858 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3859 }
3860 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3861 return u8TaskId;
3862 }
3863 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3864 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3865 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3866 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3867
3868 if (bShareBBU == FALSE)
3869 {
3870 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3871 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3872 }
3873 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3874 return avaliable_bbu_idx;
3875 }
3876 else {
3877 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3878 }
3879 }
3880 }
3881 #if SUPPORT_G2VP9
3882 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3883 {
3884 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3885 // Don't care the return value, G2_VP9 will not use it.
3886 return 0;
3887 }
3888 #endif
3889 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3890 {
3891 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3892 // Don't care the return value, VP8 will not use it.
3893 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3894 return u8Offset;
3895 //return 0;
3896 }
3897 else
3898 {
3899 switch (pTaskInfo->eDecType)
3900 {
3901 case E_VPU_EX_DECODER_EVD:
3902 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3903 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3904 break;
3905 case E_VPU_EX_DECODER_HVD:
3906 case E_VPU_EX_DECODER_RVD:
3907 case E_VPU_EX_DECODER_MVC:
3908 default:
3909 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3910 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3911 break;
3912 }
3913
3914 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3915 if (bTSP)
3916 {
3917 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3918 {
3919 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \033[0m\n", u32Id, u8TaskId, u8TaskId);
3920 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3921 bbu_state[u8TaskId].bTSP = TRUE;
3922 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3923 slq_state[u8TaskId].bTSP = TRUE;
3924 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3925 return u8TaskId;
3926 }
3927 }
3928 else
3929 {
3930 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3931 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3932 for (i = 0; i < max_bbu_cnt; i++)
3933 {
3934 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3935 {
3936 if (bbu_state[i].bTSP == FALSE)
3937 {
3938 shared_bbu_idx = i;
3939 }
3940 }
3941 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3942 {
3943 avaliable_bbu_idx = i;
3944 }
3945 }
3946
3947 /* VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx); */
3948
3949 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3950 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3951 /* VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx); */
3952 return shared_bbu_idx;
3953 }
3954 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3955 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3956
3957 if (bShareBBU == FALSE)
3958 {
3959 bbu_state[u8TaskId].bTSP = TRUE;
3960 VPRINTF("[NDec] occupy one BBU_ID \n");
3961 }
3962 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3963 return u8TaskId;
3964 }
3965 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3966 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3967
3968 if (bShareBBU == FALSE)
3969 {
3970 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3971 VPRINTF("[NDec] occupy one BBU_ID \n");
3972 }
3973 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3974 return avaliable_bbu_idx;
3975 }
3976 else {
3977 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3978 }
3979 }
3980 }
3981 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3982 MS_U32 j;
3983 MS_BOOL Got = FALSE;
3984 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3985 {
3986 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3987 {
3988 if(slq_state[i].u32Used != 0)
3989 {
3990 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3991 {
3992 retBBUId = i;
3993 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3994 slq_state[retBBUId].bTSP = bTSP;
3995 slq_state[retBBUId].bUsedbyMVD = TRUE;
3996 return retBBUId;
3997 }
3998 }
3999 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
4000 {
4001 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
4002 {
4003 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
4004 {
4005 Got = TRUE;
4006 retBBUId = i;
4007 }
4008 }
4009
4010 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
4011 {
4012 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
4013 {
4014 Got = TRUE;
4015 retBBUId = i;
4016 }
4017 }
4018
4019 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
4020 retBBUId = i;
4021 }
4022 }
4023 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4024 {
4025 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4026 slq_state[retBBUId].bTSP = bTSP;
4027 slq_state[retBBUId].bUsedbyMVD = TRUE;
4028 }
4029 }
4030 #if SUPPORT_G2VP9
4031 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4032 {
4033 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4034 // Don't care the return value, G2_VP9 will not use it.
4035 return 0;
4036 }
4037 #endif
4038 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4039 {
4040 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4041 // Don't care the return value, VP8 will not use it.
4042 return 0;
4043 }
4044 else // HVD/EVD case
4045 {
4046 switch (pTaskInfo->eDecType)
4047 {
4048 case E_VPU_EX_DECODER_EVD:
4049 case E_VPU_EX_DECODER_G2VP9:
4050 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4051 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4052 break;
4053 case E_VPU_EX_DECODER_HVD:
4054 case E_VPU_EX_DECODER_RVD:
4055 case E_VPU_EX_DECODER_MVC:
4056 default:
4057 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4058 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4059 break;
4060 }
4061
4062 for (i = 0; i < max_bbu_cnt; i++)
4063 {
4064 if(bbu_state[i].u32Used != 0)
4065 {
4066 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
4067 {
4068 retBBUId = i;
4069 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4070 bbu_state[retBBUId].bTSP = bTSP;
4071 return retBBUId;
4072 }
4073 }
4074 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
4075 {
4076 if(i < MAX_MVD_SLQ_COUNT)
4077 {
4078 if(!bTSP) //HVD/EVD first MM case
4079 {
4080 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
4081 {
4082 retBBUId = i;
4083 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4084 bbu_state[retBBUId].bTSP = bTSP;
4085 return retBBUId;
4086 }
4087
4088 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
4089 retBBUId = i;
4090 }
4091 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
4092 {
4093 retBBUId = i;
4094 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4095 bbu_state[retBBUId].bTSP = bTSP;
4096 slq_state[retBBUId].bUsedbyMVD = FALSE;
4097 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4098 slq_state[retBBUId].bTSP = bTSP;
4099 return retBBUId;
4100 }
4101 }
4102 }
4103 }
4104 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4105 {
4106 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4107 bbu_state[retBBUId].bTSP = bTSP;
4108 if(bTSP)
4109 {
4110 slq_state[retBBUId].bUsedbyMVD = FALSE;
4111 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4112 slq_state[retBBUId].bTSP = bTSP;
4113 }
4114 }
4115 }
4116 #endif
4117 return retBBUId;
4118 }
4119
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)4120 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
4121 {
4122 MS_U32 max_bbu_cnt;
4123 BBU_STATE *bbu_state;
4124 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
4125
4126 if(pTaskInfo == NULL)
4127 return FALSE;
4128 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4129 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4130
4131 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4132 /* MS_U32 i;
4133 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4134 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4135
4136 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4137 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
4138
4139 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4140 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
4141 */
4142 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4143 {
4144 // TO DO
4145 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4146 {
4147 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4148 slq_state[u32BBUId].bTSP = FALSE;
4149 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4150 return TRUE;
4151 }
4152 }
4153 #if SUPPORT_G2VP9
4154 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4155 {
4156 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4157 return TRUE;
4158 }
4159 #endif
4160 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4161 {
4162 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4163 return TRUE;
4164 }
4165 else
4166 {
4167 switch (pTaskInfo->eDecType)
4168 {
4169 case E_VPU_EX_DECODER_EVD:
4170 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4171 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4172 break;
4173 case E_VPU_EX_DECODER_HVD:
4174 case E_VPU_EX_DECODER_RVD:
4175 case E_VPU_EX_DECODER_MVC:
4176 default:
4177 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4178 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4179 break;
4180 }
4181
4182 if (u32BBUId < max_bbu_cnt)
4183 {
4184 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4185 bbu_state[u32BBUId].bTSP = FALSE;
4186
4187 if (bTSP)
4188 {
4189 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4190 slq_state[u32BBUId].bTSP = FALSE;
4191 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4192 }
4193
4194 #if 1
4195 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4196 #else
4197 if (bbu_state[u32BBUId].u32Used == 0)
4198 {
4199 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4200 }
4201 #endif
4202
4203 return TRUE;
4204 }
4205 }
4206 return FALSE;
4207 }
4208
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4209 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4210 {
4211 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4212
4213 if (CHECK_NULL_PTR(pstVBBU))
4214 return 0;
4215 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4216 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4217 MS_U32 u32Vacancy = 0;
4218
4219 if (u32WrPtr == u32RdPtr)
4220 {
4221 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4222 }
4223 else if (u32WrPtr > u32RdPtr)
4224 {
4225 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4226 }
4227 else
4228 {
4229 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4230 }
4231
4232 return u32Vacancy;
4233 }
4234
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4235 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4236 {
4237 return MAX_VDEC_VBBU_ENTRY_COUNT;
4238 }
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4239 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4240 {
4241 return pVPUHalContext->u32FWCodeAddr;
4242 }
4243
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4244 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4245 {
4246 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4247 #if SUPPORT_G2VP9
4248 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4249 #endif
4250
4251 if (CHECK_NULL_PTR(pstVBBU))
4252 return FALSE;
4253 MsOS_ReadMemory();
4254 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4255
4256 if(NULL == stEntry)
4257 {
4258 return 0;
4259 }
4260
4261 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4262 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4263 {
4264 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4265 }
4266 else
4267 {
4268 #if SUPPORT_G2VP9
4269 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4270 {
4271 if (stEntry->u32Offset == 0)
4272 return 0;
4273 else
4274 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4275 }
4276 else
4277 #endif
4278 {
4279 return stEntry->u32Offset;
4280 }
4281 }
4282 }
4283
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4284 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4285 {
4286 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4287 VDEC_VBBU_Entry *stEntry;
4288 #if SUPPORT_G2VP9
4289 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4290 #endif
4291
4292 MsOS_ReadMemory();
4293 if (CHECK_NULL_PTR(pstVBBU))
4294 return 0;
4295 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4296
4297 if (u32WrPtr == 0)
4298 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4299 else
4300 u32WrPtr--;
4301
4302 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4303
4304 if(NULL == stEntry)
4305 {
4306 return 0;
4307 }
4308
4309 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4310 #if SUPPORT_G2VP9
4311 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4312 {
4313 if (stEntry->u32Offset == 0)
4314 return 0;
4315 else
4316 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4317 }
4318 else
4319 #endif
4320 {
4321 return stEntry->u32Offset + stEntry->u32Length;
4322 }
4323 }
4324
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4325 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4326 {
4327 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4328 #if SUPPORT_G2VP9
4329 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4330 #endif
4331
4332 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4333 return FALSE;
4334 MsOS_ReadMemory();
4335 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4336 MS_U32 u32NewWrPtr;
4337
4338 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4339 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4340 {
4341 u32NewWrPtr = 0;
4342 }
4343
4344 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4345
4346 stEntry->u32Offset = stVpuPkt->u32Offset;
4347
4348 #if SUPPORT_G2VP9
4349 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4350 {
4351 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4352 }
4353 #endif
4354
4355 stEntry->u32Length = stVpuPkt->u32Length;
4356 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4357 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4358 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4359
4360 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4361
4362 pstVBBU->u32WrPtr = u32NewWrPtr;
4363
4364 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4365
4366 MsOS_FlushMemory();
4367
4368 return TRUE;
4369 }
4370
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4371 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4372 {
4373 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4374
4375 if (CHECK_NULL_PTR(pstVBBU))
4376 return FALSE;
4377 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4378 }
4379
4380 ///-----------------------------------------------------------------------------
4381 /// specify the command send to Mail box or DRAM
4382 /// @return TRUE or FALSE
4383 /// - TRUE, Mail box
4384 /// - FALSE, Dram
4385 /// @param u32Cmd \b IN: Command is going to be sned
4386 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4387 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4388 {
4389 MS_BOOL bResult = TRUE;
4390
4391 switch (u32Cmd)
4392 {
4393 // *********** Runtime action Command
4394 /* case E_HVD_CMD_RELEASE_DISPQ:
4395 case E_HVD_CMD_UPDATE_DISPQ:
4396 case E_HVD_CMD_FLUSH_DEC_Q:
4397 case E_HVD_CMD_FLUSH:
4398 case E_HVD_CMD_PLAY:
4399 case E_HVD_CMD_PAUSE:
4400 case E_HVD_CMD_STOP:
4401 case E_HVD_CMD_STEP_DECODE:
4402 case E_HVD_CMD_SKIP_DEC:
4403 case E_HVD_CMD_DISP_I_DIRECT:*/
4404 // *********** Dual-Stream Create Task Command
4405 case E_DUAL_CMD_TASK0_HVD_BBU:
4406 case E_DUAL_CMD_TASK0_HVD_TSP:
4407 case E_DUAL_CMD_TASK0_MVD_SLQ:
4408 case E_DUAL_CMD_TASK0_MVD_TSP:
4409 case E_DUAL_CMD_TASK1_HVD_BBU:
4410 case E_DUAL_CMD_TASK1_HVD_TSP:
4411 case E_DUAL_CMD_MODE:
4412 #ifndef _WIN32
4413 case E_DUAL_CMD_TASK1_MVD_SLQ:
4414 case E_DUAL_CMD_TASK1_MVD_TSP:
4415 #endif
4416 case E_DUAL_CMD_DEL_TASK:
4417 case E_DUAL_CMD_SINGLE_TASK:
4418 case E_DUAL_VERSION:
4419 case E_DUAL_R2_CMD_EXIT:
4420 case E_DUAL_CMD_STC_MODE:
4421 #ifdef VDEC3
4422 case E_DUAL_R2_CMD_FBADDR:
4423 case E_DUAL_R2_CMD_FBSIZE:
4424 // *********** N-Streams
4425 case E_NST_CMD_TASK_HVD_TSP:
4426 case E_NST_CMD_TASK_HVD_BBU:
4427 case E_NST_CMD_TASK_MVD_TSP:
4428 case E_NST_CMD_TASK_MVD_SLQ:
4429 case E_NST_CMD_DEL_TASK:
4430 case E_NST_CMD_COMMON_MASK:
4431 case E_NST_CMD_COMMON_CMD1:
4432 #endif
4433 case E_DUAL_CMD_COMMON:
4434 {
4435 bResult = TRUE;
4436 }
4437 break;
4438 default:
4439 {
4440 bResult = FALSE;
4441 }
4442 break;
4443 }
4444
4445 return bResult;
4446 }
4447
4448 ///-----------------------------------------------------------------------------
4449 /// specify the command send to Mail box or DRAM
4450 /// @return TRUE or FALSE
4451 /// - TRUE, Mail box
4452 /// - FALSE, Dram
4453 /// @param u32Cmd \b IN: Command is going to be sned
4454 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4455 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4456 {
4457 MS_BOOL bResult = TRUE;
4458
4459 switch (u32Cmd)
4460 {
4461 // *********** Runtime action Command
4462 case E_HVD_CMD_RELEASE_DISPQ:
4463 case E_HVD_CMD_UPDATE_DISPQ:
4464 case E_HVD_CMD_FLUSH_DEC_Q:
4465 case E_HVD_CMD_PAUSE:
4466 case E_HVD_CMD_FLUSH:
4467 case E_HVD_CMD_PLAY:
4468 case E_HVD_CMD_STOP:
4469 case E_HVD_CMD_SKIP_DEC:
4470 case E_HVD_CMD_DISP_I_DIRECT:
4471 case E_HVD_CMD_STEP_DECODE:
4472 case E_HVD_CMD_INC_DISPQ_NUM:
4473 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4474 {
4475 bResult = TRUE;
4476 }
4477 break;
4478 default:
4479 {
4480 bResult = FALSE;
4481 }
4482 break;
4483 }
4484
4485 return bResult;
4486 }
4487
4488 ///-----------------------------------------------------------------------------
4489 /// Send message to HVD stream command queue
4490 /// @return TRUE or FALSE
4491 /// - TRUE, Success
4492 /// - FALSE, Failed
4493 /// @param u32DramAddr \b IN: address to be writen
4494 /// @param u32Msg \b IN: data to be writen
4495 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4496 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4497 {
4498 MS_BOOL bResult = TRUE;
4499
4500 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4501
4502 WRITE_LONG(u32DramAddr,u32Msg);
4503
4504 return bResult;
4505 }
4506
4507 ///-----------------------------------------------------------------------------
4508 /// Read task share memory to specify that task command queue is empty or not
4509 /// @return TRUE or FALSE
4510 /// - TRUE, Empty
4511 /// - FALSE, Non empty
4512 /// @param u32Id \b IN: Task information
4513 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4514 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4515 {
4516 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4517 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4518 if (!cmd_q)
4519 {
4520 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4521 return FALSE;
4522 }
4523
4524 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4525 }
4526
4527 ///-----------------------------------------------------------------------------
4528 /// Read task share memory to specify that task command queue is full or not
4529 /// @return TRUE or FALSE
4530 /// - TRUE, Full
4531 /// - FALSE, Non full
4532 /// @param u32Id \b IN: Task information
4533 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4534 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4535 {
4536 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4537 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4538 if (!cmd_q)
4539 {
4540 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4541 return TRUE;
4542 }
4543 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4544
4545 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4546 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4547
4548 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4549 }
4550
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4551 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4552 {
4553 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4554 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4555 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4556
4557 #if HVD_ENABLE_MVC
4558 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4559 {
4560 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4561 }
4562 #endif
4563
4564 if (CHECK_NULL_PTR(cmd_q))
4565 {
4566 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4567 return bResult;
4568 }
4569 MS_VIRT u32CmdQWdPtr;
4570
4571 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4572 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4573
4574 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4575 return E_HVD_COMMAND_QUEUE_FULL;
4576 else
4577 {
4578 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4579 }
4580
4581 switch (u8CmdType)
4582 {
4583 case E_HVD_CMDQ_CMD:
4584 {
4585 u32Msg |= (u8TaskID << 24);
4586 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4587
4588 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4589
4590 if (bResult)
4591 {
4592 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4593
4594 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4595 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4596
4597 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4598 }
4599 break;
4600 }
4601 case E_HVD_CMDQ_ARG:
4602 {
4603 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4604 if (bResult)
4605 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4606 break;
4607 }
4608 default:
4609 {
4610 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4611 break;
4612 }
4613 }
4614
4615 MsOS_FlushMemory();
4616
4617 return bResult;
4618 }
4619
4620 ///-----------------------------------------------------------------------------
4621 /// Read task share memory to specify that task display command queue is empty or not
4622 /// @return TRUE or FALSE
4623 /// - TRUE, Empty
4624 /// - FALSE, Non empty
4625 /// @param u32Id \b IN: Task information
4626 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4627 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4628 {
4629 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4630 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4631 if (!cmd_q)
4632 {
4633 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4634 return FALSE;
4635 }
4636
4637 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4638 }
4639
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4640 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4641 {
4642 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4643 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4644 if (!cmd_q)
4645 {
4646 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4647 return TRUE;
4648 }
4649
4650 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4651
4652 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4653 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4654
4655 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4656 }
4657
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4658 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4659 {
4660 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4661 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4662 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4663
4664 #if HVD_ENABLE_MVC
4665 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4666 {
4667 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4668 }
4669 #endif
4670
4671 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4672 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4673
4674 if (CHECK_NULL_PTR(cmd_q))
4675 {
4676 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4677 return bResult;
4678 }
4679
4680 MS_VIRT u32DISPCMDQWdPtr;
4681
4682 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4683 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4684
4685 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4686 return E_HVD_COMMAND_QUEUE_FULL;
4687 else
4688 {
4689 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4690 }
4691
4692 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4693
4694 switch (u8CmdType)
4695 {
4696 case E_HVD_CMDQ_CMD:
4697 {
4698 u32Msg |= (u8TaskID << 24);
4699 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4700
4701 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4702
4703 if (bResult)
4704 {
4705 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4706
4707 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4708 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4709
4710 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4711 }
4712 break;
4713 }
4714 case E_HVD_CMDQ_ARG:
4715 {
4716 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4717 if (bResult)
4718 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4719 break;
4720 }
4721 default:
4722 {
4723 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4724 break;
4725 }
4726 }
4727
4728 MsOS_FlushMemory();
4729
4730 return bResult;
4731 }
4732
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4733 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4734 {
4735 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4736 MS_U32 u32StAddr;
4737 MS_U8 u8TmpMiuSel;
4738
4739 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4740
4741 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4742
4743 return TRUE;
4744 }
4745 #endif
4746
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4747 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4748 {
4749 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4750
4751 if(u32address >= HAL_MIU1_BASE)
4752 {
4753 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4754 }
4755 else
4756 {
4757 pVPUHalContext->u32DynamicFBAddress = u32address;
4758 }
4759
4760 pVPUHalContext->u32DynamicFBSize = u32Size;
4761 }
4762 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4763 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4764 {
4765 MS_S32 handle;
4766 switch(eClkPortType)
4767 {
4768 case E_VPU_EX_CLKPORT_MVD:
4769 {
4770 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4771 if(bEnable)
4772 {
4773 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4774 }
4775 else
4776 {
4777 Drv_Clkm_Clk_Gate_Disable(handle);
4778 }
4779 break;
4780 }
4781 case E_VPU_EX_CLKPORT_MVD_CORE:
4782 {
4783 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4784 if(bEnable)
4785 {
4786 Drv_Clkm_Set_Clk_Source(handle, "");
4787 }
4788 else
4789 {
4790 Drv_Clkm_Clk_Gate_Disable(handle);
4791 }
4792 break;
4793 }
4794 case E_VPU_EX_CLKPORT_MVD_PAS:
4795 {
4796 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4797 if(bEnable)
4798 {
4799 Drv_Clkm_Set_Clk_Source(handle, "");
4800 }
4801 else
4802 {
4803 Drv_Clkm_Clk_Gate_Disable(handle);
4804 }
4805 break;
4806 }
4807 case E_VPU_EX_CLKPORT_HVD:
4808 {
4809 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4810 if(bEnable)
4811 {
4812 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4813 }
4814 else
4815 {
4816 Drv_Clkm_Clk_Gate_Disable(handle);
4817 }
4818 break;
4819 }
4820 case E_VPU_EX_CLKPORT_HVD_IDB:
4821 {
4822 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4823 if(bEnable)
4824 {
4825 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4826 }
4827 else
4828 {
4829 Drv_Clkm_Clk_Gate_Disable(handle);
4830 }
4831 break;
4832 }
4833 case E_VPU_EX_CLKPORT_HVD_AEC:
4834 {
4835 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4836 if(bEnable)
4837 {
4838 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4839 }
4840 else
4841 {
4842 Drv_Clkm_Clk_Gate_Disable(handle);
4843 }
4844 break;
4845 }
4846 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4847 {
4848 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4849 if(bEnable)
4850 {
4851 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4852 }
4853 else
4854 {
4855 Drv_Clkm_Clk_Gate_Disable(handle);
4856 }
4857 break;
4858 }
4859 case E_VPU_EX_CLKPORT_VP8:
4860 {
4861 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4862 if(bEnable)
4863 {
4864 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4865 }
4866 else
4867 {
4868 Drv_Clkm_Clk_Gate_Disable(handle);
4869 }
4870 break;
4871 }
4872 case E_VPU_EX_CLKPORT_EVD:
4873 {
4874 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4875 if(bEnable)
4876 {
4877 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4878 }
4879 else
4880 {
4881 Drv_Clkm_Clk_Gate_Disable(handle);
4882 }
4883 break;
4884 }
4885 case E_VPU_EX_CLKPORT_EVD_PPU:
4886 {
4887 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4888 if(bEnable)
4889 {
4890 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4891 }
4892 else
4893 {
4894 Drv_Clkm_Clk_Gate_Disable(handle);
4895 }
4896 break;
4897 }
4898 case E_VPU_EX_CLKPORT_EVD_LITE:
4899 {
4900 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4901 if(bEnable)
4902 {
4903 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4904 }
4905 else
4906 {
4907 Drv_Clkm_Clk_Gate_Disable(handle);
4908 }
4909 break;
4910 }
4911 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4912 {
4913 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4914 if(bEnable)
4915 {
4916 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4917 }
4918 else
4919 {
4920 Drv_Clkm_Clk_Gate_Disable(handle);
4921 }
4922 break;
4923 }
4924 case E_VPU_EX_CLKPORT_VD_MHEG5:
4925 {
4926 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4927 if(bEnable)
4928 {
4929 Drv_Clkm_Set_Clk_Source(handle, "");
4930 }
4931 else
4932 {
4933 Drv_Clkm_Clk_Gate_Disable(handle);
4934 }
4935 break;
4936 }
4937 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4938 {
4939 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4940 if(bEnable)
4941 {
4942 Drv_Clkm_Set_Clk_Source(handle, "");
4943 }
4944 else
4945 {
4946 Drv_Clkm_Clk_Gate_Disable(handle);
4947 }
4948 break;
4949 }
4950 }
4951 }
4952 #endif //#ifdef CONFIG_MSTAR_CLKM
4953
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4954 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4955 {
4956 MS_SIZE FrameBufferSize = 0;
4957
4958 switch(eCodecType)
4959 {
4960 case E_VPU_EX_CODEC_TYPE_MPEG2:
4961 case E_VPU_EX_CODEC_TYPE_H263:
4962 case E_VPU_EX_CODEC_TYPE_MPEG4:
4963 case E_VPU_EX_CODEC_TYPE_DIVX311:
4964 case E_VPU_EX_CODEC_TYPE_DIVX412:
4965 case E_VPU_EX_CODEC_TYPE_FLV:
4966 FrameBufferSize = 0x1E00000;
4967 break;
4968 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4969 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4970 FrameBufferSize = 0x6C00000;
4971 break;
4972 case E_VPU_EX_CODEC_TYPE_RV8:
4973 case E_VPU_EX_CODEC_TYPE_RV9:
4974 FrameBufferSize = 0x1B00000;
4975 break;
4976 case E_VPU_EX_CODEC_TYPE_VP8:
4977 FrameBufferSize = 0x1500000;
4978 break;
4979 case E_VPU_EX_CODEC_TYPE_H264:
4980 FrameBufferSize = 0x8200000;
4981 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4982 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4983 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4984 break;
4985 case E_VPU_EX_CODEC_TYPE_AVS:
4986 FrameBufferSize = 0x1B00000;
4987 break;
4988 case E_VPU_EX_CODEC_TYPE_MJPEG:
4989 FrameBufferSize = 0x2800000;
4990 break;
4991 case E_VPU_EX_CODEC_TYPE_MVC:
4992 FrameBufferSize = 0x4200000;
4993 break;
4994 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4995 FrameBufferSize = 0xB000000;
4996 break;
4997 case E_VPU_EX_CODEC_TYPE_HEVC:
4998 #if SUPPORT_MSVP9
4999 case E_VPU_EX_CODEC_TYPE_VP9:
5000 #endif
5001 FrameBufferSize = 0xA000000;
5002 break;
5003 #if !SUPPORT_MSVP9
5004 case E_VPU_EX_CODEC_TYPE_VP9:
5005 FrameBufferSize = 0x7800000;
5006 break;
5007 #endif
5008 default:
5009 FrameBufferSize = 0;
5010 break;
5011 }
5012
5013 return FrameBufferSize;
5014 }
5015
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)5016 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
5017 {
5018 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5019 }
5020
5021 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)5022 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
5023 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
5024 {
5025 MS_SIZE FrameBufferSize = 0;
5026
5027 if (!offset || !length)
5028 return FALSE;
5029
5030 total_length -= unUseSize;
5031 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
5032 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
5033
5034 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5035
5036 if(FrameBufferSize == 0)
5037 {
5038 return FALSE;
5039 }
5040 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
5041 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
5042 if (total_length < FrameBufferSize)
5043 {
5044 *offset = unUseSize;
5045 *length = total_length;
5046 }
5047 else // todo, dual decode case
5048 {
5049 *offset = unUseSize;
5050 *length = FrameBufferSize;
5051 }
5052 return TRUE;
5053 }
5054
HAL_VPU_EX_strcmp(const char * string1,const char * string2)5055 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
5056 {
5057 int iRet, i;
5058
5059 i = 0;
5060 while(string1[i] || string2[i])
5061 {
5062 iRet = string1[i] - string2[i];
5063 if(iRet)
5064 {
5065 return iRet;
5066 }
5067 i++;
5068 }
5069 return 0;
5070 }
5071
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)5072 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
5073 {
5074 typedef enum
5075 {
5076 E_CAP_NDEC_FB_MIU_SELECT,
5077 E_CAP_NDEC_NSTREAM_FB_SIZE,
5078 E_CAP_NDEC_NSTREAM_BS_SIZE,
5079 E_CAP_NDEC_SUPPORT_SHAREBBU,
5080 E_CAP_SUPPORT_ALLOCATOR,
5081
5082 } VPU_EX_GetCapabilityCmdId;
5083
5084 typedef struct
5085 {
5086 VPU_EX_GetCapabilityCmdId eCmdId;
5087 MS_U8 u8CmdName[32];
5088
5089 } VPU_EX_GetCapabilityCmd;
5090
5091 static VPU_EX_GetCapabilityCmd stCapCmd[] =
5092 {
5093 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
5094 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
5095 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
5096 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
5097 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
5098 };
5099
5100 MS_U32 bRet = FALSE;
5101 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
5102 MS_U32 u32CmdCnt;
5103
5104 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
5105 {
5106 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
5107 {
5108 bRet = TRUE;
5109 switch(stCapCmd[u32CmdCnt].eCmdId)
5110 {
5111 case E_CAP_NDEC_FB_MIU_SELECT:
5112 {
5113 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5114 *pSupport = FALSE;
5115 }
5116 break;
5117
5118 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
5119 case E_CAP_NDEC_NSTREAM_FB_SIZE:
5120 {
5121 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5122 *pSize = 0;
5123 }
5124 break;
5125
5126 // FIXME: Patch for waiting dynamic bitstream buffer
5127 case E_CAP_NDEC_NSTREAM_BS_SIZE:
5128 {
5129 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5130 *pSize = 0;
5131 }
5132 break;
5133
5134 case E_CAP_NDEC_SUPPORT_SHAREBBU:
5135 {
5136 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
5137 *pbSupportShareBBU = TRUE;
5138 }
5139 break;
5140
5141 case E_CAP_SUPPORT_ALLOCATOR:
5142 {
5143 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5144 *pSupport = TRUE;
5145 }
5146 break;
5147
5148 default:
5149 bRet = FALSE;
5150 break;
5151 }
5152 }
5153 }
5154
5155 return bRet;
5156 }
5157
5158 #else
5159 #include "halVPU_EX.h"
5160 #include "drvMMIO.h"
5161 #include "../hvd_v3/regHVD_EX.h"
5162 #include "halCHIP.h"
5163
5164 #if defined(MSOS_TYPE_NUTTX)
5165 extern int lib_lowprintf(const char *fmt, ...);
5166 #define PRINTF lib_lowprintf
5167 #elif defined(MSOS_TYPE_OPTEE)
5168 #define PRINTF printf
5169 #endif
5170
5171 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5172 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5173
5174 MS_U8 u8FW_Binary[] = {
5175 #include "fwVPU.dat"
5176 };
5177
5178 MS_U32 u32HVDRegOSBase;
5179
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5180 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5181 {
5182 //PRINTF("do load code,u32DestAddr %x\n",addr);
5183 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5184 MAsm_CPU_Sync();
5185 MsOS_FlushMemory();
5186
5187 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5188 {
5189 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5190 return FALSE;
5191 }
5192 return TRUE;
5193 }
5194
HAL_VPU_EX_SetLockDownRegister(void * param)5195 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5196 {
5197 #if 1
5198 MS_PHY u32StAddr_main;
5199 MS_PHY u32StAddr_sub;
5200 MS_U32 u32NonPMBankSize = 0;
5201 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5202
5203 if(param == NULL)
5204 {
5205 return FALSE;
5206 }
5207
5208 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5209
5210 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5211
5212 // ES buffer
5213 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5214 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5215
5216
5217 MS_PHY u32StartOffset;
5218 MS_U8 u8MiuSel;
5219
5220 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5221 u32StAddr_main = u32StartOffset;
5222
5223 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5224 u32StAddr_sub = u32StartOffset;
5225
5226 //Lock down register
5227 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5228 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5229
5230 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
5231 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
5232 //~
5233
5234 // Lock Down
5235 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5236 //~
5237 #endif
5238 return TRUE;
5239 }
5240
5241 #endif
5242