1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #if defined(REDLION_LINUX_KERNEL_ENVI)
101 #include "drvHVD_Common.h"
102 #else
103 #include "MsCommon.h"
104 #endif
105 // Internal Definition
106 #include "regVPU.h"
107 #include "halVPU.h"
108 #include "halCHIP.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Driver Compiler Options
112 //-------------------------------------------------------------------------------------------------
113
114
115 //-------------------------------------------------------------------------------------------------
116 // Local Defines
117 //-------------------------------------------------------------------------------------------------
118 #define VPU_MIU1BASE_ADDR 0x40000000 //Notice: this define must be comfirm with designer
119
120 #define VPU_MSG_ERR(format, args...) //printf(format, ##args)
121 #define VPU_MSG_DEG(format, args...) //printf(format, ##args)
122 #define VPU_MSG_INFO(format, args...) //printf(format, ##args)
123
124 //------------------------------ MIU SETTINGS ----------------------------------
125 #define _MaskMiuReq_VPU_D_RW( m ) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
126 #define _MaskMiuReq_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
127 #define _MaskMiuReq_VPU_I_R( m ) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))
128
129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
132
133 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
134 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6))
135 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) //g08
136 #define _VPU_MIU_SetReqMask( miu_clients, mask ) \
137 do { \
138 if (miu_clients##_ON_MIU1 == 0) \
139 _MaskMiuReq_##miu_clients( mask ); \
140 else \
141 _MaskMiu1Req_##miu_clients( mask ); \
142 }while(0)
143
144 #if ENABLE_VPU_MUTEX_PROTECTION
145 static MS_S32 s32VPUMutexID = -1;
146 static MS_U8 _u8VPU_Mutex[] = {"VPU_Mutex"};
147 #define _HAL_VPU_MutexCreate() \
148 if( s32VPUMutexID < 0 ) \
149 { \
150 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO, (char *)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
151 }
152 #define _HAL_VPU_MutexDelete() \
153 if( s32VPUMutexID >= 0 ) \
154 { \
155 MsOS_DeleteMutex(s32VPUMutexID); \
156 s32VPUMutexID = -1; \
157 }
158 #define _HAL_VPU_Entry() \
159 if( s32VPUMutexID >= 0 ) \
160 { \
161 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
162 { \
163 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
164 } \
165 }
166 #define _HAL_VPU_Return(_ret) \
167 { \
168 if( s32VPUMutexID >= 0 ) \
169 { \
170 MsOS_ReleaseMutex(s32VPUMutexID); \
171 } \
172 return _ret; \
173 }
174 #define _HAL_VPU_Release() \
175 { \
176 if( s32VPUMutexID >= 0 ) \
177 { \
178 MsOS_ReleaseMutex(s32VPUMutexID); \
179 } \
180 }
181 #else
182 #define _HAL_VPU_MutexCreate()
183 #define _HAL_VPU_MutexDelete()
184 #define _HAL_VPU_Entry()
185 #define _HAL_VPU_Return(_ret) {return _ret;}
186 #define _HAL_VPU_Release()
187 #endif
188
189 //-------------------------------------------------------------------------------------------------
190 // Local Structures
191 //-------------------------------------------------------------------------------------------------
192
193
194 //-------------------------------------------------------------------------------------------------
195 // Global Variables
196 //-------------------------------------------------------------------------------------------------
197
198
199 //-------------------------------------------------------------------------------------------------
200 // Local Variables
201 //-------------------------------------------------------------------------------------------------
202 #if defined (__aeon__)
203 static MS_U32 u32VPURegOSBase=0xA0000000;
204 #else
205 static MS_U32 u32VPURegOSBase=0xBF200000;
206 #endif
207 static VPU_DecoderType _ePreDecoder = E_VPU_DECODER_NONE;
208
209 //-------------------------------------------------------------------------------------------------
210 // Debug Functions
211 //-------------------------------------------------------------------------------------------------
212
213
214 //-------------------------------------------------------------------------------------------------
215 // Local Functions
216 //-------------------------------------------------------------------------------------------------
217
218
219 //-------------------------------------------------------------------------------------------------
220 // Global Functions
221 //-------------------------------------------------------------------------------------------------
HAL_VPU_InitRegBase(MS_U32 u32RegBase)222 void HAL_VPU_InitRegBase(MS_U32 u32RegBase)
223 {
224 u32VPURegOSBase = u32RegBase;
225 }
226
HAL_VPU_Init(VPU_Init_Params * InitParams)227 MS_BOOL HAL_VPU_Init(VPU_Init_Params* InitParams)
228 {
229 MS_BOOL bRet = TRUE;
230 // enable module
231 HAL_VPU_ClockInv(InitParams->bClockInv);
232 HAL_VPU_ClockSpeed(InitParams->eClockSpeed);
233 HAL_VPU_PowerCtrl( TRUE );
234 #if 1 //Create VPU's own mutex
235 _HAL_VPU_MutexCreate();
236 #else
237 s32VPUMutexID = InitParams->s32VPUMutexID;
238 u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
239 #endif
240 return bRet;
241 }
242
HAL_VPU_DeInit(void)243 MS_BOOL HAL_VPU_DeInit(void)
244 {
245 MS_BOOL bRet = TRUE;
246 HAL_VPU_PowerCtrl( FALSE );
247 _HAL_VPU_MutexDelete();
248 return bRet;
249 }
250
HAL_VPU_PowerCtrl(MS_BOOL bEnable)251 void HAL_VPU_PowerCtrl(MS_BOOL bEnable)
252 {
253 if( bEnable )
254 {
255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS );
256 }
257 else
258 {
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS );
260 }
261 }
262
HAL_VPU_ClockSpeed(MS_U32 u32type)263 void HAL_VPU_ClockSpeed(MS_U32 u32type)
264 {
265 // setup clock.
266 switch( u32type )
267 {
268 case VPU_CLOCK_216MHZ:
269 case VPU_CLOCK_192MHZ:
270 case VPU_CLOCK_160MHZ:
271 case VPU_CLOCK_144MHZ:
272 _VPU_WriteWordMask( REG_TOP_VPU , u32type , TOP_CKG_VPU_CLK_MASK );
273 break;
274 default:
275 _VPU_WriteWordMask( REG_TOP_VPU , VPU_CLOCK_216MHZ , TOP_CKG_VPU_CLK_MASK );
276 break;
277 }
278 }
279
HAL_VPU_ClockInv(MS_BOOL bEnable)280 void HAL_VPU_ClockInv(MS_BOOL bEnable)
281 {
282 if( TRUE )
283 {
284 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_INV );
285 }
286 else
287 {
288 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_INV , TOP_CKG_VPU_INV );
289 }
290 }
291
HAL_VPU_MIU_RW_Protect(MS_BOOL bEnable)292 void HAL_VPU_MIU_RW_Protect(MS_BOOL bEnable)
293 {
294 _VPU_MIU_SetReqMask( VPU_D_RW , bEnable );
295 _VPU_MIU_SetReqMask( VPU_Q_RW , bEnable );
296 _VPU_MIU_SetReqMask( VPU_I_R , bEnable );
297 VPU_Timer_delay_ms(1);
298 }
299
300 ///-----------------------------------------------------------------------------
301 /// config AVCH264 CPU
302 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
303 /// @param u8dlend_en \b IN: endian
304 /// - 1, little endian
305 /// - 0, big endian
306 ///-----------------------------------------------------------------------------
HAL_VPU_CPUSetting(MS_U32 u32StAddr)307 MS_BOOL HAL_VPU_CPUSetting(MS_U32 u32StAddr)
308 {
309 MS_BOOL bRet = TRUE;
310 MS_U32 u32Offset = 0;
311 MS_U16 tempreg = 0;
312
313 u32Offset = (u32StAddr >= HAL_MIU1_BASE) ? (u32StAddr-HAL_MIU1_BASE) : u32StAddr ;
314
315 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
316 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
317 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
318 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
319 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
320 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0x8000);
321 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
322 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0x2000);
323
324 if(u32StAddr >= HAL_MIU1_BASE)
325 {
326 // Data sram base Unit: byte address
327 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)((u32Offset | VPU_MIU1BASE_ADDR) & 0x0000ffff)) ;
328 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)(((u32Offset | VPU_MIU1BASE_ADDR)>>16) & 0xffff));
329
330 // Instruction sram base Unit: byte address
331 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
332 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
333 }
334 else
335 {
336 // Data sram base Unit: byte address
337 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
338 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
339
340 // Instruction sram base Unit: byte address
341 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
342 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset>>16) & 0xffff));
343 }
344
345 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
346 tempreg |= VPU_REG_IO2_EN;
347 tempreg |= VPU_REG_QMEM_SPACE_EN;
348 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
349
350 return bRet;
351 }
352
353 ///-----------------------------------------------------------------------------
354 /// H.264 SW reset
355 /// @return TRUE or FALSE
356 /// - TRUE, Success
357 /// - FALSE, Failed
358 ///-----------------------------------------------------------------------------
HAL_VPU_SwRst(void)359 MS_BOOL HAL_VPU_SwRst(void)
360 {
361 MS_U16 tempreg=0, tempreg1=0;
362 MS_BOOL bRet = TRUE;
363
364 HAL_VPU_MIU_RW_Protect(TRUE);
365
366 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
367 tempreg1 |= MAU1_REG_SW_RESET;
368 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
369
370 #if defined(UDMA_FPGA_ENVI)
371 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
372 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
373 #endif
374
375 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
376 tempreg &= ~VPU_REG_CPU_R2_EN;
377 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
378 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
379 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
380
381 VPU_Timer_delay_ms(1);
382 HAL_VPU_MIU_RW_Protect(FALSE);
383 return bRet;
384 }
385
386 ///-----------------------------------------------------------------------------
387 /// CPU reset release
388 ///-----------------------------------------------------------------------------
HAL_VPU_SwRstRelse(void)389 void HAL_VPU_SwRstRelse(void)
390 {
391 MS_U16 tempreg=0, tempreg1=0;
392
393 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
394 tempreg |= VPU_REG_CPU_R2_EN;
395 tempreg |= VPU_REG_CPU_SW_RSTZ;
396 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
397 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
398
399 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
400 tempreg1 &= ~MAU1_REG_SW_RESET;
401 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
402
403 //MsOS_DelayTask(1);
404 }
405
HAL_VPU_SwRelseMAU(void)406 void HAL_VPU_SwRelseMAU(void)
407 {
408 MS_U16 tempreg=0;
409
410 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
411 tempreg &= ~MAU1_REG_SW_RESET;
412 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
413 }
414
415 //todo: hvd PTS R/W pointer need upate from sram to dram
HAL_VPU_MemRead(MS_U32 u32Addr)416 MS_U32 HAL_VPU_MemRead(MS_U32 u32Addr)
417 {
418 MS_U32 u32value = 0;
419
420 return u32value;
421 }
422
HAL_VPU_MemWrite(MS_U32 u32Addr,MS_U32 u32value)423 MS_BOOL HAL_VPU_MemWrite(MS_U32 u32Addr , MS_U32 u32value)
424 {
425 MS_BOOL bRet=TRUE;
426
427 return bRet;
428 }
429
430 ///-----------------------------------------------------------------------------
431 /// Check AVCH264 Ready or not
432 /// @return TRUE or FALSE
433 /// - TRUE, MailBox is free
434 /// - FALSE, MailBox is busy
435 /// @param u8MBox \b IN: MailBox to check
436 /// - AVCH264_HI_MBOX0,
437 /// - AVCH264_HI_MBOX1,
438 /// - AVCH264_RISC_MBOX0,
439 /// - AVCH264_RISC_MBOX1,
440 ///-----------------------------------------------------------------------------
HAL_VPU_MBoxRdy(MS_U32 u32type)441 MS_BOOL HAL_VPU_MBoxRdy(MS_U32 u32type)
442 {
443 MS_BOOL bResult = FALSE;
444 switch(u32type)
445 {
446 case VPU_HI_MBOX0:
447 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY)&VPU_REG_HI_MBOX0_RDY)?FALSE:TRUE;
448 break;
449 case VPU_HI_MBOX1:
450 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY)&VPU_REG_HI_MBOX1_RDY)?FALSE:TRUE;
451 break;
452 case VPU_RISC_MBOX0:
453 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY)&VPU_REG_RISC_MBOX0_RDY)?TRUE:FALSE;
454 break;
455 case VPU_RISC_MBOX1:
456 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY)&VPU_REG_RISC_MBOX1_RDY)?TRUE:FALSE;
457 break;
458 default:
459 break;
460 }
461 return bResult;
462 }
463
464
465 ///-----------------------------------------------------------------------------
466 /// Read message from AVCH264
467 /// @return TRUE or FALSE
468 /// - TRUE, success
469 /// - FALSE, failed
470 /// @param u8MBox \b IN: MailBox to read
471 /// - AVCH264_RISC_MBOX0
472 /// - AVCH264_RISC_MBOX1
473 /// @param u32Msg \b OUT: message read
474 ///-----------------------------------------------------------------------------
HAL_VPU_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)475 MS_BOOL HAL_VPU_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg)
476 {
477 MS_BOOL bResult = TRUE;
478 switch(u32type)
479 {
480 case VPU_HI_MBOX0:
481 *u32Msg = ((MS_U32)(_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
482 ((MS_U32)(_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
483 break;
484 case VPU_HI_MBOX1:
485 *u32Msg = ((MS_U32)(_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
486 ((MS_U32)(_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
487 break;
488 case VPU_RISC_MBOX0:
489 *u32Msg = ((MS_U32)(_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
490 ((MS_U32)(_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
491 break;
492 case VPU_RISC_MBOX1:
493 *u32Msg = ((MS_U32)(_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
494 ((MS_U32)(_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
495 break;
496
497 default:
498 *u32Msg=0;
499 bResult = FALSE;
500 break;
501 }
502 return bResult;
503 }
504
505 ///-----------------------------------------------------------------------------
506 /// Mailbox from AVCH264 clear bit resest
507 ///-----------------------------------------------------------------------------
HAL_VPU_MBoxClear(MS_U32 u32type)508 void HAL_VPU_MBoxClear(MS_U32 u32type)
509 {
510 switch(u32type)
511 {
512 case VPU_RISC_MBOX0:
513 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR );
514 break;
515 case VPU_RISC_MBOX1:
516 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX1_CLR , VPU_REG_RISC_MBOX1_CLR );
517 break;
518 default:
519 break;
520 }
521 }
522
523 ///-----------------------------------------------------------------------------
524 /// Send message to AVCH264
525 /// @return TRUE or FALSE
526 /// - TRUE, Success
527 /// - FALSE, Failed
528 /// @param u8MBox \b IN: MailBox
529 /// - AVCH264_HI_MBOX0,
530 /// - AVCH264_HI_MBOX1,
531 ///-----------------------------------------------------------------------------
HAL_VPU_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)532 MS_BOOL HAL_VPU_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
533 {
534 MS_BOOL bResult = TRUE;
535 switch(u32type)
536 {
537 case VPU_HI_MBOX0:
538 _VPU_Write4Byte( VPU_REG_HI_MBOX0_L , u32Msg );
539 _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET );
540 break;
541 case VPU_HI_MBOX1:
542 _VPU_Write4Byte( VPU_REG_HI_MBOX1_L , u32Msg );
543 _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET );
544 break;
545 default:
546 bResult = FALSE;
547 break;
548 }
549 return bResult;
550 }
551
HAL_VPU_GetProgCnt(void)552 MS_U32 HAL_VPU_GetProgCnt(void)
553 {
554 MS_U16 expc_l=0;
555 MS_U16 expc_h=0;
556
557 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
558 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
559
560 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
561 }
562
563 /// Drivers can query if they need to reload f/w
HAL_VPU_IsNeedReload(VPU_DecoderType eDecoder)564 MS_BOOL HAL_VPU_IsNeedReload(VPU_DecoderType eDecoder)
565 {
566 //printf("Pre=%x, Cur=%x\n", _ePreDecoder, eDecoder);
567 return (_ePreDecoder != eDecoder);
568 }
569
570 /// Drivers should set its eDecoderType to VPU after initialization succeed.
HAL_VPU_SetFWDecoder(VPU_DecoderType eDecoder)571 void HAL_VPU_SetFWDecoder(VPU_DecoderType eDecoder)
572 {
573 _ePreDecoder = eDecoder;
574 }
575
576 /// Driver can query the current eDecoderType
HAL_VPU_GetFWDecoder(void)577 VPU_DecoderType HAL_VPU_GetFWDecoder(void)
578 {
579 return _ePreDecoder;
580 }
581
582
HAL_VPU_MAU_IDLE(void)583 MS_BOOL HAL_VPU_MAU_IDLE(void)
584 {
585 if(((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
586 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
587 {
588 return TRUE;
589 }
590
591 return FALSE;
592 }
593
594
595