1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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8 // Any use, modification, reproduction, retransmission, or republication of all
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11 //
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15 //
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
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90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216 typedef struct
217 {
218 MS_BOOL bSTCSetMode;
219 MS_U32 u32STCIndex;
220 } VPU_EX_STC;
221
222 #define VPU_MSG_ERR(format, args...) \
223 do \
224 { \
225 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
226 { \
227 printf("[VPU][ERR]%s:", __FUNCTION__); \
228 printf(format, ##args); \
229 } \
230 } while (0)
231
232 #define VPU_MSG_DBG(format, args...) \
233 do \
234 { \
235 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
236 { \
237 printf("[VPU][DBG]%s:", __FUNCTION__); \
238 printf(format, ##args); \
239 } \
240 } while (0)
241
242 #define VPU_MSG_INFO(format, args...) \
243 do \
244 { \
245 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
246 { \
247 printf("[VPU][INF]%s:", __FUNCTION__); \
248 printf(format, ##args); \
249 } \
250 } while (0)
251
252 //------------------------------ MIU SETTINGS ----------------------------------
253 #ifdef EVDR2
254 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
255 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
256 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2)) // G32
257
258 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
259 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
260 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2)) // G32
261
262 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
263 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
264 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
265
266 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
267 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
268 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
269 #endif
270
271
272
273 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
274 do \
275 { \
276 if (miu_clients##_ON_MIU0 == 1) \
277 { \
278 _MaskMiuReq_##miu_clients(mask); \
279 } \
280 else \
281 { \
282 if (miu_clients##_ON_MIU1 == 1) \
283 { \
284 _MaskMiu1Req_##miu_clients(mask); \
285 } \
286 } \
287 } while(0)
288
289
290
291
292 #if ENABLE_VPU_MUTEX_PROTECTION
293 MS_S32 s32VPUMutexID = -1;
294 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
295
296 #define _HAL_VPU_MutexCreate() \
297 if (s32VPUMutexID < 0) \
298 { \
299 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
300 }
301
302 #define _HAL_VPU_MutexDelete() \
303 if (s32VPUMutexID >= 0) \
304 { \
305 MsOS_DeleteMutex(s32VPUMutexID); \
306 s32VPUMutexID = -1; \
307 }
308
309 #define _HAL_VPU_Entry() \
310 if (s32VPUMutexID >= 0) \
311 { \
312 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
313 { \
314 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
315 } \
316 }
317
318 #define _HAL_VPU_Return(_ret) \
319 { \
320 if (s32VPUMutexID >= 0) \
321 { \
322 MsOS_ReleaseMutex(s32VPUMutexID); \
323 } \
324 return _ret; \
325 }
326
327 #define _HAL_VPU_Release() \
328 { \
329 if (s32VPUMutexID >= 0) \
330 { \
331 MsOS_ReleaseMutex(s32VPUMutexID); \
332 } \
333 }
334 #else
335 #define _HAL_VPU_MutexCreate()
336 #define _HAL_VPU_MutexDelete()
337 #define _HAL_VPU_Entry()
338 #define _HAL_VPU_Return(_ret) {return _ret;}
339 #define _HAL_VPU_Release()
340 #endif
341
342 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
343 #define VPU_CMD_TIMEOUT 1000 // 1 sec
344
345 //-------------------------------------------------------------------------------------------------
346 // Local Structures
347 //-------------------------------------------------------------------------------------------------
348 typedef struct _VPU_HWInitFunc
349 {
350 MS_BOOL (*pfMVDHW_Init)(void);
351 MS_BOOL (*pfMVDHW_Deinit)(void);
352 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
353 MS_BOOL (*pfHVDHW_Deinit)(void);
354 } VPU_HWInitFunc;
355
356 typedef struct
357 {
358 MS_U32 u32ApiHW_Version; //<Version of current structure>
359 MS_U16 u16ApiHW_Length; //<Length of this structure>
360
361 MS_U8 u8Cap_Support_Decoder_Num;
362
363 MS_BOOL bCap_Support_MPEG2;
364 MS_BOOL bCap_Support_H263;
365 MS_BOOL bCap_Support_MPEG4;
366 MS_BOOL bCap_Support_DIVX311;
367 MS_BOOL bCap_Support_DIVX412;
368 MS_BOOL bCap_Support_FLV;
369 MS_BOOL bCap_Support_VC1ADV;
370 MS_BOOL bCap_Support_VC1MAIN;
371
372 MS_BOOL bCap_Support_RV8;
373 MS_BOOL bCap_Support_RV9;
374 MS_BOOL bCap_Support_H264;
375 MS_BOOL bCap_Support_AVS;
376 MS_BOOL bCap_Support_AVS_PLUS;
377 MS_BOOL bCap_Support_MJPEG;
378 MS_BOOL bCap_Support_MVC;
379 MS_BOOL bCap_Support_VP8;
380 MS_BOOL bCap_Support_VP9;
381 MS_BOOL bCap_Support_HEVC;
382
383 /*New HW Cap and Feature add in struct at the end*/
384 }VDEC_HwCap;
385
386 //-------------------------------------------------------------------------------------------------
387 // Local Functions Prototype
388 //-------------------------------------------------------------------------------------------------
389 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
390 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
391 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
392
393 //-------------------------------------------------------------------------------------------------
394 // Global Variables
395 //-------------------------------------------------------------------------------------------------
396 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
397 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
398 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
399 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
400 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
401 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
402 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
403 #if SUPPORT_G2VP9 && defined(VDEC3)
404 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
405 #endif
406 #if defined (__aeon__)
407 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
408 #else
409 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
410 #endif
411
412 //-------------------------------------------------------------------------------------------------
413 // Local Variables
414 //-------------------------------------------------------------------------------------------------
415 #if 0
416
417 static MS_BOOL _bVPUPowered = FALSE;
418 static MS_BOOL _bVPURsted = FALSE;
419 static MS_BOOL _bVPUSingleMode = FALSE;
420 static VPU_EX_DecModCfg _stVPUDecMode;
421
422 static MS_U8 u8TaskCnt = 0;
423
424 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
425
426 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
427 static VPU_EX_Stream _stVPUStream[] =
428 {
429 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
430 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
431 };
432 static VPU_HWInitFunc stHWInitFunc =
433 {
434 &HAL_MVD_InitHW,
435 &HAL_MVD_DeinitHW,
436 &HAL_HVD_EX_InitHW,
437 &HAL_HVD_EX_DeinitHW,
438 };
439
440 #endif
441
442 #if VPU_ENABLE_EMBEDDED_FW_BINARY
443 static const MS_U8 u8HVD_FW_Binary[] = {
444 #include "fwVPU.dat"
445 };
446
447 #if HVD_ENABLE_RV_FEATURE
448 static const MS_U8 u8HVD_VLC_Binary[] = {
449 #include "fwVPU_VLC.dat"
450 };
451 #endif
452 #endif
453
454
455 #ifdef VDEC3
456 typedef struct
457 {
458 MS_BOOL bTSP;
459 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
460 MS_U32 u32Used;
461 } BBU_STATE;
462
463 typedef struct
464 {
465 MS_BOOL bTSP;
466 MS_BOOL bUsedbyMVD;
467 MS_U32 u32Used;
468 } SLQ_STATE;
469 #endif
470
471 typedef struct
472 {
473 MS_BOOL _bVPUPowered;
474 MS_BOOL _bVPURsted;
475 MS_BOOL _bVPUSingleMode;
476 VPU_EX_DecModCfg _stVPUDecMode;
477 MS_U8 u8TaskCnt;
478 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
479 #ifdef VDEC3
480 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
481 #else
482 VPU_EX_Stream _stVPUStream[2];
483 #endif
484
485 VPU_HWInitFunc stHWInitFunc;
486
487 MS_BOOL bVpuExReloadFW;
488 MS_BOOL bVpuExLoadFWRlt;
489 MS_VIRT u32VPUSHMAddr; //PA
490 MS_BOOL bEnableVPUSecureMode;
491
492 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
493 MS_BOOL bEnableDymanicFBMode;
494 MS_PHY u32DynamicFBAddress;
495 MS_U32 u32DynamicFBSize;
496 #ifdef VDEC3
497 MS_VIRT u32FWCodeAddr;
498 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
499
500 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
501 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
502 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
503
504 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
505 #endif
506 MS_U8 u8ForceRst;
507 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
508 } VPU_Hal_CTX;
509
510 //global variables
511 VPU_Hal_CTX* pVPUHalContext = NULL;
512 VPU_Hal_CTX gVPUHalContext;
513 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
514 MS_BOOL bVPUMbxInitFlag = 0;
515 MS_U8 u8VPUMbxMsgClass = 0;
516 MBX_Msg VPUReeToTeeMbxMsg;
517 MBX_Msg VPUTeeToReeMbxMsg;
518
519 //-------------------------------------------------------------------------------------------------
520 // Debug Functions
521 //-------------------------------------------------------------------------------------------------
522
523
524 //-------------------------------------------------------------------------------------------------
525 // Local Functions
526 //-------------------------------------------------------------------------------------------------
527
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)528 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
529 {
530 #if HVD_ENABLE_RV_FEATURE
531 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
532 {
533 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
534 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
535 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
536
537 if (pVlcCfg->u32BinSize)
538 {
539 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
540
541 MS_U32 u32Start;
542 MS_U32 u32StartOffset;
543 MS_U8 u8MiuSel;
544
545 // Get MIU selection and offset from physical address = 0x30000000
546 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
547
548
549 if(u8MiuSel == E_CHIP_MIU_0)
550 cpyflag = E_SPIDMA_DEV_MIU0;
551 else if(u8MiuSel == E_CHIP_MIU_1)
552 cpyflag = E_SPIDMA_DEV_MIU1;
553 else if(u8MiuSel == E_CHIP_MIU_2)
554 cpyflag = E_SPIDMA_DEV_MIU2;
555
556 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
557 {
558 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
559 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
560
561 return FALSE;
562 }
563 }
564 else
565 {
566 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
567 return FALSE;
568 }
569 #else
570 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
571 return FALSE;
572 #endif
573 }
574 else
575 {
576 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
577 {
578 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
579 {
580 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
581 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
582
583 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
584 BDMA_Result bdmaRlt;
585 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
586
587 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
588 u32SrcAdd = pVlcCfg->u32BinAddr;
589 u32tabsize = pVlcCfg->u32BinSize;
590 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
591 MsOS_FlushMemory();
592 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
593
594 if (E_BDMA_OK != bdmaRlt)
595 {
596 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
597 }
598 #else
599 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
600 #endif
601 }
602 else
603 {
604 VPU_MSG_ERR
605 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
606 return FALSE;
607 }
608 }
609 else
610 {
611 #if VPU_ENABLE_EMBEDDED_FW_BINARY
612 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
613 MS_U8 *pu8HVD_VLC_Binary;
614
615 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
616
617 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
618 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
619 (MS_U32) sizeof(u8HVD_VLC_Binary));
620
621 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
622 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
623 #else
624 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
625 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
626 (MS_U32) sizeof(u8HVD_VLC_Binary));
627
628 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
629 #endif
630 #else
631 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
632 return FALSE;
633 #endif
634 }
635 }
636 #endif
637
638 return TRUE;
639 }
640
641 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)642 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
643 {
644 MS_U8 u8OffsetIdx = 0;
645 MS_U8 u8VSidBaseMask = 0xF0;
646 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
647
648 switch (eVSidBase)
649 {
650 case E_HAL_VPU_MAIN_STREAM_BASE:
651 {
652 u8OffsetIdx = 0;
653 break;
654 }
655 case E_HAL_VPU_SUB_STREAM_BASE:
656 {
657 u8OffsetIdx = 1;
658 break;
659 }
660 case E_HAL_VPU_MVC_STREAM_BASE:
661 {
662 u8OffsetIdx = 0;
663 break;
664 }
665 #ifdef VDEC3
666 case E_HAL_VPU_N_STREAM_BASE:
667 {
668 u8OffsetIdx = u32Id & 0x0F;
669 break;
670 }
671 #endif
672 default:
673 {
674 u8OffsetIdx = 0;
675 break;
676 }
677 }
678
679 /*
680 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
681 u32Id, eVSidBase, u8OffsetIdx);
682 */
683 return u8OffsetIdx;
684 }
685
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)686 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
687 {
688 return _VPU_EX_GetOffsetIdx(u32Id);
689 }
690
_VPU_EX_Context_Init(void)691 static void _VPU_EX_Context_Init(void)
692 {
693 #ifdef VDEC3
694 MS_U8 i;
695
696 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
697 {
698 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
699 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
700 }
701
702 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
703 {
704 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
705 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
706 }
707
708 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
709 {
710 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
711 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
712 }
713
714 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
715 {
716 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
717 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
718 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
719 }
720 #else
721 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
722 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
723 #endif
724 pVPUHalContext->bVpuExReloadFW = TRUE;
725 pVPUHalContext->u8ForceRst = 0;
726
727 }
728
HAL_VPU_EX_ForceSwRst(void)729 void HAL_VPU_EX_ForceSwRst(void)
730 {
731 pVPUHalContext->u8ForceRst = 1;
732 }
733
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)734 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
735 {
736 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
737 MS_U8 u8OffsetIdx = 0;
738
739 if (NULL == pTaskInfo)
740 {
741 return eCmd;
742 }
743
744 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
745
746 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
747 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
748
749 #ifdef VDEC3
750 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
751 {
752 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
753 {
754 eCmd = E_NST_CMD_TASK_MVD_TSP;
755 }
756 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
757 {
758 eCmd = E_NST_CMD_TASK_MVD_SLQ;
759 }
760 }
761 #else
762 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
763 {
764 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
765 {
766 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
767 }
768 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
769 {
770 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
771 }
772 }
773 #endif
774 #ifdef VDEC3
775 #if SUPPORT_G2VP9
776 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
777 #else
778 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
779 #endif
780 {
781 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
782 {
783 eCmd = E_NST_CMD_TASK_HVD_TSP;
784 }
785 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
786 {
787 eCmd = E_NST_CMD_TASK_HVD_BBU;
788 }
789 }
790 #else
791 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
792 {
793 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
794 {
795 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
796 }
797 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
798 {
799 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
800 }
801 }
802 #endif
803
804 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
805 return eCmd;
806 }
807
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)808 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
809 {
810 if (!pTaskInfo)
811 {
812 VPU_MSG_ERR("null input\n");
813 return FALSE;
814 }
815
816 //Check if we need to init MVD HW
817 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
818 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
819 {
820 //Init HW
821 if (FALSE == HAL_VPU_EX_MVDInUsed())
822 {
823 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
824 {
825 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
826 return FALSE;
827 }
828 }
829 else
830 {
831 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
832 }
833 }
834
835 //MVD use sub mvop
836 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
837 #ifdef VDEC3
838 (pTaskInfo->u8HalId == 1) )
839 #else
840 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
841 #endif
842 {
843 VPU_MSG_ERR("Force turn on HVD\n");
844 if(!HAL_VPU_EX_HVDInUsed())
845 {
846 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
847 {
848 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
849 {
850 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
851 return FALSE;
852 }
853 }
854 else
855 {
856 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
857 #ifdef CONFIG_MSTAR_CLKM
858 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
859 #else
860 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
861 #endif
862 }
863 }
864 else
865 {
866 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
867 }
868 }
869
870 //Check if we need to init HVD HW
871 #ifdef VDEC3
872 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
873 #else
874 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
875 #endif
876 {
877 if (!HAL_VPU_EX_MVDInUsed())
878 {
879 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
880 {
881 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
882 return FALSE;
883 }
884 }
885
886 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
887 {
888 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
889 return FALSE;
890 }
891 #if SUPPORT_MSVP9
892 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
893 {
894 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
895 }
896 #endif
897 }
898
899 #if SUPPORT_G2VP9 && defined(VDEC3)
900 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
901 {
902 if (!HAL_VPU_EX_MVDInUsed())
903 {
904 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
905 {
906 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
907 return FALSE;
908 }
909 }
910 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
911 {
912 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
913 return FALSE;
914 }
915 }
916 #endif
917
918 return TRUE;
919 }
920
_VPU_EX_InClock(MS_U32 u32type)921 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
922 {
923 switch (u32type)
924 {
925 case VPU_CLOCK_240MHZ:
926 return 240000000UL;
927 case VPU_CLOCK_216MHZ:
928 return 216000000UL;
929 case VPU_CLOCK_192MHZ:
930 return 192000000UL;
931 case VPU_CLOCK_12MHZ:
932 return 12000000UL;
933 case VPU_CLOCK_320MHZ:
934 return 320000000UL;
935 case VPU_CLOCK_288MHZ:
936 return 288000000UL;
937 case VPU_CLOCK_432MHZ:
938 return 432000000UL;
939 default:
940 return 384000000UL;
941 }
942 }
943
944
945 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
946 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)947 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
948 {
949 //#ifndef MSOS_TYPE_LINUX_KERNEL
950 #if 1
951 MS_U8 ClassNum = 0;
952 MBX_Result result;
953
954 #if 0
955 if (bVPUMbxInitFlag == TRUE)
956 {
957 return TRUE;
958 }
959 #endif
960
961 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
962 {
963 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
964 return FALSE;
965 }
966 else
967 {
968 MApi_MBX_Enable(TRUE);
969 }
970
971 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
972
973 if (E_MBX_SUCCESS != result)
974 {
975 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
976 return FALSE;
977 }
978
979 result = MApi_MBX_RegisterMSG(ClassNum, 10);
980
981 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
982 {
983 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
984 return FALSE;
985 }
986 else
987 {
988 bVPUMbxInitFlag = TRUE;
989 u8VPUMbxMsgClass = ClassNum;
990 return TRUE;
991 }
992 #else
993 return FALSE;
994 #endif
995 }
996
997 //#ifdef MBX_2K
998 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)999 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
1000 {
1001 MBX_Result result;
1002 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
1003
1004 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1005 {
1006 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1007 }
1008
1009 if (bVPUMbxInitFlag == FALSE)
1010 {
1011 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1012 }
1013
1014 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1015 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1016 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1017 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1018 VPUReeToTeeMbxMsg.u8Index = msg_type;
1019
1020 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1021 if (E_MBX_SUCCESS != result)
1022 {
1023 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1024 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1025 }
1026
1027 // Receive Reply ACK from TEE side.
1028 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1029
1030 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1031
1032 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1033 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1034 {
1035 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1036 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1037 }
1038 else
1039 #else
1040 do
1041 {
1042 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1043 } while(E_MBX_SUCCESS != result);
1044 #endif
1045 {
1046 u8Index = VPUTeeToReeMbxMsg.u8Index;
1047 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1048
1049 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1050 {
1051 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1052 }
1053 }
1054
1055 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1056 }
1057 #endif
1058
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1059 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1060 {
1061 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1062 {
1063 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1064 {
1065 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1066 return FALSE;
1067 }
1068 else
1069 {
1070 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1071 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1072 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1073 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1074 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1075 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1076 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1077 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1078
1079 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1080
1081
1082 MS_U32 u32Start;
1083
1084 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1085 {
1086 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1087 pVPUHalContext->u32VPUSHMAddr = u32Start;
1088 }
1089 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1090 {
1091 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1092 pVPUHalContext->u32VPUSHMAddr = u32Start;
1093
1094 }
1095 else // == 0
1096 {
1097 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1098 }
1099 }
1100 }
1101 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1102 {
1103 MS_U32 u32Offset;
1104 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1105 {
1106 u32Offset = u32SHMAddr-u32MIU1Addr;
1107 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1108 }
1109 else
1110 {
1111 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1112 }
1113 }
1114 return TRUE;
1115 }
1116
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1117 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1118 {
1119 bVPUMbxInitFlag = TRUE;
1120 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1121 return TRUE;
1122 }
1123
1124 #endif
1125
HAL_VPU_EX_GetFWReload(void)1126 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1127 {
1128 return pVPUHalContext->bVpuExReloadFW;
1129 }
1130
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1131 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1132 {
1133 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1134 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1135 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1136 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1137 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1138 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1139 )
1140 {
1141 return FALSE;
1142 }
1143 else
1144 {
1145 return TRUE;
1146 }
1147 }
1148
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1149 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1150 {
1151 MS_PHY u32fwPA = NULL; //physical address
1152 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1153
1154 if (TRUE == HAL_VPU_EX_IsPowered())
1155 {
1156 VPU_MSG_DBG("IsPowered\n");
1157 return TRUE;
1158 }
1159 else
1160 {
1161 //VPU hold
1162 HAL_VPU_EX_SwRst(FALSE);
1163
1164 //VPU clock on
1165 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1166
1167 if (VPU_I_R_ON_MIU0)
1168 VPUInitParams.u8MiuSel = 0;
1169 else if (VPU_I_R_ON_MIU1)
1170 VPUInitParams.u8MiuSel = 1;
1171
1172 HAL_VPU_EX_Init(&VPUInitParams);
1173 }
1174
1175 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1176 VPU_EX_TaskInfo *pTaskInfo = NULL;
1177 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1178
1179 if (pInitPara)
1180 {
1181 pFWCodeCfg = pInitPara->pFWCodeCfg;
1182 pTaskInfo = pInitPara->pTaskInfo;
1183 pVlcCfg = pInitPara->pVLCCfg;
1184 }
1185 else
1186 {
1187 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1188 return FALSE;
1189 }
1190
1191 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1192 //#ifdef MBX_2K
1193 #if 1
1194 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1195 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1196 {
1197 SYS_TEEINFO teemode;
1198 MDrv_SYS_ReadKernelCmdLine();
1199 MDrv_SYS_GetTEEInfo(&teemode);
1200 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1201 {
1202 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1203
1204 if (FALSE == HAL_VPU_EX_GetFWReload())
1205 {
1206 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1207 {
1208 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1209 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1210 {
1211 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1212 return FALSE;
1213 }
1214 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1215 }
1216 else
1217 {
1218 //Check f/w prefix "VDEC30"
1219 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1220 {
1221 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1222 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1223 {
1224 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1225 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1226 return FALSE;
1227 }
1228 }
1229 else
1230 {
1231 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1232 }
1233 }
1234 }
1235 else
1236 {
1237 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1238 {
1239 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1240 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1241 return FALSE;
1242 }
1243 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1244 }
1245 }
1246 }
1247 else
1248 #endif
1249 #endif
1250 {
1251 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1252
1253 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1254 {
1255 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1256 return FALSE;
1257 }
1258 }
1259
1260 if (pVlcCfg)
1261 {
1262 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1263 {
1264 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1265 return FALSE;
1266 }
1267 }
1268
1269 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1270 {
1271 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1272 return FALSE;
1273 }
1274
1275 //Init HW
1276 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1277 {
1278 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1279 //_MVD_INIT_FAIL_RET();
1280 return FALSE;
1281 }
1282 else
1283 {
1284 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1285 }
1286
1287 //set vpu clock to FW
1288 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1289 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1290
1291 ctl_ptr->statue = CTL_STU_NONE;
1292 //notify controller the interface version of VPU driver.
1293 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1294 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1295 MsOS_FlushMemory();
1296 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1297
1298 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1299 if (TRUE == HAL_VPU_EX_IsRsted())
1300 {
1301 VPU_MSG_DBG("VPU_IsRsted\n");
1302 return TRUE;
1303 }
1304 else
1305 {
1306 HAL_VPU_EX_SwRstRelse();
1307 }
1308
1309 return TRUE;
1310 }
1311
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1312 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1313 {
1314 MS_BOOL bRet = FALSE;
1315 #if defined(VDEC3)
1316 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1317 #else
1318 MS_BOOL isEVD = FALSE ;
1319 #endif
1320 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1321 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1322 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1323
1324 if (TRUE == isHVD)
1325 {
1326 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1327 }
1328
1329 #if defined(VDEC3)
1330 if (TRUE == isEVD)
1331 {
1332 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1333 }
1334 #endif
1335
1336 #if SUPPORT_G2VP9 && defined(VDEC3)
1337 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1338 {
1339 bRet = HAL_VP9_EX_DeinitHW();
1340 }
1341 #endif
1342 return bRet;
1343 }
1344
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1345 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1346 {
1347 HAL_VPU_EX_SwRst(TRUE);
1348 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1349 HAL_VPU_EX_DeInit();
1350
1351 return TRUE;
1352 }
1353
_VPU_EX_GetActiveCodecCnt(void)1354 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1355 {
1356 MS_U32 i;
1357 MS_U8 u8ActiveCnt = 0;
1358 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1359 {
1360 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1361 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1362 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1363 {
1364 u8ActiveCnt++;
1365 }
1366 }
1367 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1368 {
1369 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1370 }
1371 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1372 return u8ActiveCnt;
1373 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1374 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1375 {
1376 if (TRUE)
1377 {
1378 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1379 }
1380 else
1381 {
1382 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1383 }
1384 }
1385
_VPU_EX_ClockSpeed(MS_U32 u32type)1386 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1387 {
1388 switch (u32type)
1389 {
1390 case VPU_CLOCK_240MHZ:
1391 case VPU_CLOCK_216MHZ:
1392 case VPU_CLOCK_192MHZ:
1393 case VPU_CLOCK_12MHZ:
1394 case VPU_CLOCK_320MHZ:
1395 case VPU_CLOCK_288MHZ:
1396 case VPU_CLOCK_384MHZ:
1397 case VPU_CLOCK_432MHZ:
1398 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1399 break;
1400 default:
1401 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1402 break;
1403 }
1404 }
1405 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1406 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1407 {
1408 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1409 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1410 {
1411 return TRUE;
1412 }
1413 return FALSE;
1414 }
1415 #endif
1416
1417
1418 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1419 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1420 {
1421 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1422 {
1423 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1424 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1425 ms_VDECDecompressDeInit();
1426 return TRUE;
1427 }
1428 else
1429 {
1430 return FALSE;
1431 }
1432 }
1433 #endif
1434
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1435 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1436 {
1437 MS_BOOL bRet = TRUE;
1438 pVPUHalContext->_bVPUSingleMode = bEnable;
1439 return bRet;
1440 }
1441
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1442 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1443 {
1444 MS_BOOL bRet = TRUE;
1445 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1446 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1447 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1448
1449 return bRet;
1450 }
1451
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1452 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1453 {
1454 MS_BOOL bRet = TRUE;
1455 MS_U8 i=0;
1456 if (pstCfg != NULL)
1457 {
1458 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1459 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1460 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1461 {
1462 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1463 }
1464 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1465 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1466 }
1467 else
1468 {
1469 bRet = FALSE;
1470 }
1471 return bRet;
1472 }
1473
1474 //static MS_BOOL bVpuExReloadFW = TRUE;
1475 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1476 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1477 {
1478 pVPUHalContext->bVpuExReloadFW = bReload;
1479 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1480 return TRUE;
1481 }
1482
1483
1484 //-------------------------------------------------------------------------------------------------
1485 // Global Functions
1486 //-------------------------------------------------------------------------------------------------
1487 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1488 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1489 {
1490 #if HVD_ENABLE_RV_FEATURE
1491 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1492 {
1493 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1494 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1495 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1496
1497 if (pVlcCfg->u32BinSize)
1498 {
1499 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1500
1501 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1502 {
1503 cpyflag = E_SPIDMA_DEV_MIU1;
1504 }
1505 else
1506 {
1507 cpyflag = E_SPIDMA_DEV_MIU0;
1508 }
1509
1510 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1511 {
1512 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1513 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1514
1515 return FALSE;
1516 }
1517 }
1518 else
1519 {
1520 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1521 return FALSE;
1522 }
1523 #else
1524 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1525 return FALSE;
1526 #endif
1527 }
1528 else
1529 {
1530 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1531 {
1532 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1533 {
1534 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1535 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1536
1537 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1538 BDMA_Result bdmaRlt;
1539
1540 MsOS_FlushMemory();
1541 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1542
1543 if (E_BDMA_OK != bdmaRlt)
1544 {
1545 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1546 }
1547 #else
1548 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1549 #endif
1550 }
1551 else
1552 {
1553 VPU_MSG_ERR
1554 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1555 return FALSE;
1556 }
1557 }
1558 else
1559 {
1560 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1561 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1562 MS_U8 *pu8HVD_VLC_Binary;
1563
1564 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1565
1566 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1567 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1568 (MS_U32) sizeof(u8HVD_VLC_Binary));
1569
1570 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1571 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1572 #else
1573 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1574 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1575 (MS_U32) sizeof(u8HVD_VLC_Binary));
1576
1577 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1578 #endif
1579 #else
1580 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1581 return FALSE;
1582 #endif
1583 }
1584 }
1585 #endif
1586
1587 return TRUE;
1588 }
1589 #endif
1590 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1591 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1592 #else
1593 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1594 #endif
1595 {
1596 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1597 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1598 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1599 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1600 MS_U32 u32Arg = 0xFFFFFFFF;
1601 MS_U32 u32Timeout = 0;
1602 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1603 MS_U32 u32CmdArg = 0;
1604 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1605 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1606
1607 _HAL_VPU_Entry();
1608 //Check FW buffer size
1609 if (1 == u8Offset)
1610 {
1611 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1612 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1613
1614 if (u32CurFWBuffSize < u32MinFWBuffSize)
1615 {
1616 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1617 _HAL_VPU_Release();
1618 return FALSE;
1619 }
1620 }
1621
1622 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1623 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1624 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1625 {
1626 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1627 }
1628 #ifdef VDEC3
1629 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1630 #endif
1631
1632 if (0 == pVPUHalContext->u8TaskCnt)
1633 {
1634 //No task is created, need to load f/w, etc.
1635 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1636
1637 if (!_VPU_EX_InitAll(pInitPara))
1638 {
1639 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1640 _HAL_VPU_Release();
1641 return FALSE;
1642 }
1643
1644 //Check if controller finish initialization: clear mailbox, etc.
1645 //Need to check it before sending any controller commands!
1646 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1647 while (CTL_STU_NONE == ctl_ptr->statue)
1648 {
1649 if (HVD_GetSysTime_ms() > u32Timeout)
1650 {
1651 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1652 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1653 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1654 MS_U32 t=0;
1655 for (t=0; t<30; t++)
1656 {
1657 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1658 }
1659 _HAL_VPU_Release();
1660 return FALSE;
1661 }
1662
1663 MsOS_ReadMemory();
1664 }
1665
1666 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1667 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1668
1669 }
1670 else
1671 {
1672 if (pVPUHalContext->_bVPUSingleMode)
1673 {
1674 //Show error message
1675 printf("This task will use dram instead of sram!!!\n");
1676 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1677 }
1678
1679 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1680 {
1681 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1682 _HAL_VPU_Release();
1683 return FALSE;
1684 }
1685 if (pInitPara->pVLCCfg)
1686 {
1687 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1688 {
1689 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1690 _HAL_VPU_Release();
1691 return FALSE;
1692 }
1693 }
1694 }
1695
1696
1697 #ifdef VDEC3
1698 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1699 {
1700 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1701
1702 memset(pTemp4,0,sizeof(VDEC_VBBU));
1703
1704 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1705
1706 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1707
1708 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1709
1710 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1711
1712 memset(pTemp2,0,sizeof(CMD_QUEUE));
1713
1714 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1715
1716 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1717
1718 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1719
1720 memset(pTemp3,0,0x2000);
1721
1722 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1723
1724 memset((void*)pVersion,0,0x8);
1725
1726 *pVersion = 1; //0:diu, 1:wb
1727 }
1728
1729 #endif
1730
1731 #if 1 // For TEE
1732 #ifdef VDEC3
1733 #if SUPPORT_G2VP9
1734 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1735 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1736 #else
1737 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1738 #endif
1739 #else
1740 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1741 #endif
1742 {
1743 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1744
1745 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1746 {
1747 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1748 }
1749 else
1750 {
1751 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1752 }
1753
1754 MsOS_FlushMemory();
1755 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1756
1757 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1758 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1759 }
1760 #endif
1761
1762 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1763 {
1764 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1765 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1766
1767 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1768
1769 MsOS_FlushMemory();
1770 }
1771
1772 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1773 {
1774 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1775 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1776 {
1777 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1778 }
1779 }
1780
1781 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1782 {
1783 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1784 //arg=1 to get better performance for single task
1785 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1786 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1787 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1788 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1789 {
1790 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1791 }
1792 }
1793 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1794 {
1795 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1796 {
1797 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1798 {
1799 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1800 u32CmdArg = CTL_MODE_3DTV;
1801 break;
1802 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1803 u32CmdArg = CTL_MODE_3DTV_PROG;
1804 break;
1805 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1806 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1807 break;
1808 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1809 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1810 break;
1811 default:
1812 u32CmdArg = CTL_MODE_3DTV;
1813 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1814 break;
1815 }
1816 }
1817 else
1818 {
1819 u32CmdArg = CTL_MODE_3DWMV;
1820 }
1821 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1822 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1823 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1824 {
1825 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1826 }
1827 }
1828 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1829 {
1830 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1831 {
1832 u32CmdArg = CTL_MODE_ONE_STC;
1833 }
1834 else
1835 {
1836 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1837 }
1838 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1839 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1840 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1841 {
1842 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1843 }
1844 }
1845
1846 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1847 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1848 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1849 #ifdef VDEC3
1850 {
1851 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1852 }
1853 #else
1854 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1855 #endif
1856
1857 #ifdef VDEC3
1858 #if SUPPORT_G2VP9
1859 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1860 #else
1861 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1862 #endif
1863 {
1864 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1865 }
1866 #else
1867 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1868 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1869 #endif
1870 else
1871 {
1872 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1873 _HAL_VPU_Release();
1874 return FALSE;
1875 }
1876 #else
1877 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1878 #endif
1879
1880 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1881 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1882
1883 MsOS_ReadMemory();
1884 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1885 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1886
1887 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1888 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1889 {
1890 if (HVD_GetSysTime_ms() > u32Timeout)
1891 {
1892 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1893 MS_U32 t=0;
1894 for (t=0; t<30; t++)
1895 {
1896 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1897 }
1898 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1899 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1900 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1901 _HAL_VPU_Release();
1902 return FALSE;
1903 //#endif
1904 }
1905
1906 MsOS_ReadMemory();
1907 }
1908
1909 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1910 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1911
1912 #ifdef VDEC3
1913 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1914 #else
1915 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1916 #endif
1917 {
1918 HAL_HVD_EX_SetNalTblAddr(u32Id);
1919 }
1920
1921 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1922 {
1923 eDecType = E_VPU_EX_DECODER_MVD;
1924 }
1925 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1926 {
1927 eDecType = E_VPU_EX_DECODER_HVD;
1928 }
1929 #ifdef VDEC3
1930 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1931 {
1932 eDecType = E_VPU_EX_DECODER_EVD;
1933 }
1934 #if SUPPORT_G2VP9
1935 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1936 {
1937 eDecType = E_VPU_EX_DECODER_G2VP9;
1938 }
1939 #endif
1940 #endif
1941 else
1942 {
1943 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1944 _HAL_VPU_Release();
1945 return FALSE;
1946 }
1947
1948 #ifdef VDEC3
1949 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1950 {
1951 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1952 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1953 }
1954 #endif
1955
1956 if (pTaskInfo->eDecType != eDecType)
1957 {
1958 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1959 pTaskInfo->eDecType, eDecType);
1960 }
1961 goto _SAVE_DEC_TYPE;
1962
1963 _SAVE_DEC_TYPE:
1964 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1965 {
1966 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1967 }
1968 else
1969 {
1970 VPU_MSG_ERR("Cannot save eDecType!!\n");
1971 }
1972
1973 (pVPUHalContext->u8TaskCnt)++;
1974 _HAL_VPU_Release();
1975 return TRUE;
1976 }
1977
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1978 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1979 {
1980 HVD_Return eRet;
1981 #ifdef VDEC3
1982 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
1983 #else
1984 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
1985 #endif
1986 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1987 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
1988
1989 _HAL_VPU_Entry();
1990 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
1991
1992 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
1993 if(eRet != E_HVD_RETURN_SUCCESS)
1994 {
1995 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
1996 }
1997
1998 {
1999 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2000 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2001 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2002
2003 MsOS_ReadMemory();
2004
2005 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2006 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2007
2008 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2009 {
2010 if (HVD_GetSysTime_ms() > u32Timeout)
2011 {
2012 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2013 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2014 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2015
2016 if(pVPUHalContext->u8TaskCnt == 1)
2017 {
2018 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2019 break;
2020 }
2021 else if(pVPUHalContext->u8TaskCnt == 2)
2022 {
2023 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2024 break;
2025 }
2026 else
2027 {
2028 VPU_MSG_ERR("Task number is not correct\n");
2029 _HAL_VPU_Release();
2030 return FALSE;
2031 }
2032 }
2033
2034 MsOS_ReadMemory();
2035 }
2036
2037 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2038 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2039 }
2040 #if SUPPORT_EVD
2041 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2042 {
2043 HAL_EVD_EX_ClearTSPInput(u32Id);
2044 }
2045 #endif
2046
2047 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2048 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2049 {
2050 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2051 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2052 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2053 }
2054
2055 if (pVPUHalContext->u8TaskCnt)
2056 {
2057 (pVPUHalContext->u8TaskCnt)--;
2058 }
2059 else
2060 {
2061 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2062 }
2063
2064 if (0 == pVPUHalContext->u8TaskCnt)
2065 {
2066 int i;
2067 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2068 _VPU_EX_DeinitAll(pInitPara);
2069 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2070 pVPUHalContext->u32VPUSHMAddr = 0;
2071
2072 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2073 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2074 }
2075 else
2076 {
2077 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2078 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2079 }
2080
2081 _HAL_VPU_Release();
2082 return TRUE;
2083 }
2084
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2085 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2086 {
2087 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2088 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2089 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2090 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2091 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2092 #endif
2093
2094 if (FALSE == HAL_VPU_EX_GetFWReload())
2095 {
2096 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2097 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2098 {
2099 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2100 }
2101 else
2102 {
2103 //Check f/w prefix "VDEC30"
2104 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2105 {
2106 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2107 }
2108 else
2109 {
2110 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2111 return TRUE;
2112 }
2113 }
2114 }
2115
2116 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2117 {
2118 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2119 if (u32Size != 0)
2120 {
2121 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2122
2123
2124 MS_U32 u32Start;
2125 MS_U32 u32StartOffset;
2126 MS_U8 u8MiuSel;
2127
2128 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2129
2130
2131 if(u8MiuSel == E_CHIP_MIU_0)
2132 cpyflag = E_SPIDMA_DEV_MIU0;
2133 else if(u8MiuSel == E_CHIP_MIU_1)
2134 cpyflag = E_SPIDMA_DEV_MIU1;
2135 else if(u8MiuSel == E_CHIP_MIU_2)
2136 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2137
2138 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2139 {
2140 goto _load_code_fail;
2141 }
2142 }
2143 else
2144 {
2145 goto _load_code_fail;
2146 }
2147 #else
2148 goto _load_code_fail;
2149 #endif
2150 }
2151 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2152 {
2153 if (u32BinAddr != 0 && u32Size != 0)
2154 {
2155 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2156 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2157 {
2158 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2159 {
2160 VPU_MSG_INFO("Decompress ok!!!\n");
2161 }
2162 else
2163 {
2164 VPU_MSG_INFO("Decompress fail!!!\n");
2165 }
2166 }
2167 else
2168 #endif
2169 {
2170 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2171 }
2172 }
2173 else
2174 {
2175 goto _load_code_fail;
2176 }
2177 }
2178 else
2179 {
2180 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2181 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2182 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2183 (MS_U32) sizeof(u8HVD_FW_Binary));
2184
2185 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2186 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2187 {
2188 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2189 {
2190 VPU_MSG_INFO("Decompress ok!!!\n");
2191 }
2192 else
2193 {
2194 VPU_MSG_INFO("Decompress fail!!!\n");
2195 }
2196 }
2197 else
2198 #endif
2199 {
2200 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2201 }
2202 #else
2203 goto _load_code_fail;
2204 #endif
2205 }
2206
2207 MAsm_CPU_Sync();
2208 MsOS_FlushMemory();
2209
2210 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2211 {
2212 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2213 goto _load_code_fail;
2214 }
2215
2216 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2217 return TRUE;
2218
2219 _load_code_fail:
2220 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2221 return FALSE;
2222 }
2223
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2224 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2225 {
2226 u32VPURegOSBase = u32RegBase;
2227 }
2228
HAL_VPU_EX_Init_Share_Mem(void)2229 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2230 {
2231 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2232
2233 MS_U32 u32ShmId;
2234 MS_VIRT u32Addr;
2235 MS_U32 u32BufSize;
2236
2237
2238 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2239 sizeof(VPU_Hal_CTX),
2240 &u32ShmId,
2241 &u32Addr,
2242 &u32BufSize,
2243 MSOS_SHM_QUERY))
2244 {
2245 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2246 sizeof(VPU_Hal_CTX),
2247 &u32ShmId,
2248 &u32Addr,
2249 &u32BufSize,
2250 MSOS_SHM_CREATE))
2251 {
2252 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2253 if(pVPUHalContext == NULL)
2254 {
2255 pVPUHalContext = &gVPUHalContext;
2256 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2257 _VPU_EX_Context_Init();
2258 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2259 }
2260 else
2261 {
2262 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2263 }
2264 //return FALSE;
2265 }
2266 else
2267 {
2268 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2269 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2270 _VPU_EX_Context_Init();
2271 }
2272 }
2273 else
2274 {
2275 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2276 }
2277 #else
2278 if(pVPUHalContext == NULL)
2279 {
2280 pVPUHalContext = &gVPUHalContext;
2281 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2282 _VPU_EX_Context_Init();
2283 }
2284 #endif
2285
2286 return TRUE;
2287
2288 }
2289
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2290 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2291 {
2292 MS_U32 i = 0;
2293
2294 _HAL_VPU_MutexCreate();
2295
2296 _HAL_VPU_Entry();
2297
2298 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2299 {
2300 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2301 {
2302 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2303 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2304 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2305 _HAL_VPU_Release();
2306 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2307 }
2308 }
2309 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2310 {
2311 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2312 {
2313 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2314 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2315 {
2316 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2317 _HAL_VPU_Release();
2318 return pVPUHalContext->_stVPUStream[i].eStreamId;
2319 }
2320 }
2321 }
2322 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2323 {
2324 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2325 {
2326 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2327 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2328 {
2329 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2330 _HAL_VPU_Release();
2331 return pVPUHalContext->_stVPUStream[i].eStreamId;
2332 }
2333 }
2334 }
2335 #ifdef VDEC3
2336 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2337 {
2338 #if 1 // bound FW task to main/sub stream
2339 i = eStreamType - E_HAL_VPU_N_STREAM;
2340 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2341 {
2342 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2343 _HAL_VPU_Release();
2344 return pVPUHalContext->_stVPUStream[i].eStreamId;
2345 }
2346 #else // dynamic select FW task id
2347 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2348 {
2349 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2350 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2351 {
2352 return pVPUHalContext->_stVPUStream[i].eStreamId;
2353 }
2354 }
2355 #endif
2356 }
2357 #endif
2358
2359 _HAL_VPU_Release();
2360
2361 return E_HAL_VPU_STREAM_NONE;
2362 }
2363
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2364 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2365 {
2366 _HAL_VPU_Entry();
2367
2368 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2369 {
2370 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2371 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2372 }
2373 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2374 {
2375 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2376 }
2377
2378 _HAL_VPU_Release();
2379
2380 return TRUE;
2381 }
2382
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2383 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2384 {
2385 MS_U8 u8Idx = 0;
2386
2387 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2388
2389 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2390 {
2391 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2392 {
2393 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2394 return 0;
2395 }
2396 }
2397 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2398 {
2399 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2400 {
2401 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2402 return 1;
2403 }
2404 }
2405
2406 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2407 {
2408 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2409 break;
2410 }
2411
2412 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2413 {
2414 VPU_MSG_ERR("all vpu free streams are occupied \n");
2415 return -1;
2416 }
2417
2418 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2419 return u8Idx;
2420 }
2421
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2422 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2423 {
2424 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2425
2426 // enable module
2427 _VPU_EX_ClockInv(InitParams->bClockInv);
2428 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2429 HAL_VPU_EX_PowerCtrl(TRUE);
2430
2431 #ifdef CONFIG_MSTAR_CLKM
2432 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2433 #endif
2434
2435 #ifdef CONFIG_MSTAR_SRAMPD
2436 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2437 HVD_Delay_ms(1);
2438 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2439 HVD_Delay_ms(1);
2440 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2441 HVD_Delay_ms(1);
2442 #endif
2443 #if 1 //Create VPU's own mutex
2444 //_HAL_VPU_MutexCreate();
2445 #else
2446 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2447 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2448 #endif
2449
2450 return TRUE;
2451 }
2452
HAL_VPU_EX_DeInit(void)2453 MS_BOOL HAL_VPU_EX_DeInit(void)
2454 {
2455 if (0 != _VPU_EX_GetActiveCodecCnt())
2456 {
2457 VPU_MSG_DBG("do nothing since codec is active.\n");
2458 return TRUE;
2459 }
2460
2461 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2462
2463 #ifdef CONFIG_MSTAR_CLKM
2464 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2465 #else
2466 HAL_VPU_EX_PowerCtrl(FALSE);
2467 #endif
2468
2469 #ifdef CONFIG_MSTAR_SRAMPD
2470 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2471 HVD_Delay_ms(1);
2472 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2473 HVD_Delay_ms(1);
2474 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2475 HVD_Delay_ms(1);
2476 #endif
2477
2478 HAL_VPU_EX_SwRelseMAU();
2479 //_HAL_VPU_MutexDelete();
2480
2481 return TRUE;
2482 }
2483
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2484 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2485 {
2486 if (bEnable)
2487 {
2488 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2489 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2490 pVPUHalContext->_bVPUPowered = TRUE;
2491 }
2492 else
2493 {
2494 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2495 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2496 pVPUHalContext->_bVPUPowered = FALSE;
2497 }
2498 }
2499
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2500 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2501 {
2502 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2503 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2504 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2505 VPU_EX_TimerDelayMS(1);
2506 }
2507
2508 ///-----------------------------------------------------------------------------
2509 /// config AVCH264 CPU
2510 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2511 /// @param u8dlend_en \b IN: endian
2512 /// - 1, little endian
2513 /// - 0, big endian
2514 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2515 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2516 {
2517 MS_BOOL bRet = TRUE;
2518 MS_U32 u32Offset = 0;
2519 MS_U16 tempreg = 0;
2520 MS_U8 u8MiuSel;
2521 //MS_U32 u32TmpStartOffset;
2522
2523 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2524
2525 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2526 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2527 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2528 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2529 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2530 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2531 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2532 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2533 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2534 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2535
2536 #if (HVD_ENABLE_IQMEM)
2537 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2538 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2539 #endif
2540
2541 #if (VPU_FORCE_MIU_MODE)
2542 // Data sram base Unit: byte address
2543 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2544 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2545 // Instruction sram base Unit: byte address
2546 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2547 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2548
2549 #ifndef HAL_FEATURE_MAU
2550 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2551 #endif
2552 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2553
2554 //use force miu mode
2555 if(u8MiuSel == E_CHIP_MIU_0)
2556 {
2557 #ifdef HAL_FEATURE_MAU
2558 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2559 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2560 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2561 #else
2562 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2563 #endif
2564 }
2565 else if(u8MiuSel == E_CHIP_MIU_1)
2566 {
2567 #ifdef HAL_FEATURE_MAU
2568 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2569 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2570 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2571 #else
2572 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2573 #endif
2574 }
2575 else //miu 2
2576 {
2577 #ifdef HAL_FEATURE_MAU
2578 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2579 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2580 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2581 #else
2582 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2583 #endif
2584 }
2585 #else
2586 ///TODO:
2587 #endif
2588
2589
2590 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2591 tempreg |= VPU_REG_IO2_EN;
2592 tempreg |= VPU_REG_QMEM_SPACE_EN;
2593 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2594
2595 return bRet;
2596 }
2597
2598 ///-----------------------------------------------------------------------------
2599 /// Set IQMem data access mode or instruction fetch mode
2600 /// @param u8dlend_en \b IN: endian
2601 /// - 1, switch to data access mode
2602 /// - 0, switch to instruction fetch mode
2603 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2604 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2605 {
2606
2607 if(bEnable){
2608
2609 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2610 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2611
2612 }
2613 else{
2614
2615 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2616
2617 }
2618 }
2619
2620 ///-----------------------------------------------------------------------------
2621 /// H.264 SW reset
2622 /// @return TRUE or FALSE
2623 /// - TRUE, Success
2624 /// - FALSE, Failed
2625 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2626 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2627 {
2628 MS_U16 tempreg = 0, tempreg1 = 0;
2629 MS_U16 idle_cnt;
2630 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2631 tempreg |= VPU_REG_CPU_STALL_EN;
2632 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2633
2634 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2635 // 0xf means VPU is not stalled
2636 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2637 pVPUHalContext->u8ForceRst = 0;
2638 // write R2 RIU registers to select DCU/ICU debug data
2639 // Writing these registers here provides enough time for them to
2640 // take effect.
2641 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2642 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2643 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2644 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2645
2646 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2647 // This step is important because in the next step we want to make
2648 // sure "DCU is not replaying when R2 is stalled".
2649 idle_cnt = 100;
2650 do
2651 {
2652 if (--idle_cnt == 0)
2653 {
2654 printf("VPU_REG_CPU_STALL_EN is not set\n");
2655 break;
2656 }
2657 MsOS_DelayTask(1);
2658 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2659 // check CPU status: DCU should NOT be replaying
2660 // If R2 has been stalled, we can guarantee that if we found DCU is
2661 // NOT replaying, it will NOT replay later even CPU is going to issue
2662 // a load/store instruction.
2663 idle_cnt = 100;
2664 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2665 {
2666 if (--idle_cnt == 0)
2667 {
2668 printf("DCU is replaying\n");
2669 break;
2670 }
2671 MsOS_DelayTask(1);
2672 }
2673 // wait 1ms to prevent race condition between (1) DCU is not
2674 // replaying, and (2) BIU start to doing new job or ICU start to
2675 // fetch new instruction
2676 MsOS_DelayTask(1);
2677
2678 // check BIU should be empty
2679 idle_cnt = 100;
2680 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2681 {
2682 if (--idle_cnt == 0)
2683 {
2684 printf("BIU DCU idle time out~~~~~\n");
2685 break;
2686 }
2687 MsOS_DelayTask(1);
2688 }
2689
2690 // check CPU is not requesting ICU
2691 idle_cnt = 100;
2692 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2693 {
2694 if (--idle_cnt == 0)
2695 {
2696 printf("CPU keeps requesting ICU\n");
2697 break;
2698 }
2699 MsOS_DelayTask(1);
2700 }
2701
2702 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2703 // (2) ISB start to fetch
2704 MsOS_DelayTask(1);
2705
2706 // check ISB should be idle
2707 idle_cnt = 100;
2708 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2709 {
2710 if (--idle_cnt == 0)
2711 {
2712 printf("ISB is busy\n");
2713 break;
2714 }
2715 MsOS_DelayTask(1);
2716 }
2717 }
2718 #ifdef HAL_FEATURE_MAU
2719 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2720 if (bCheckMauIdle)
2721 {
2722 MS_U32 mau_idle_cnt = 100;// ms
2723 while (mau_idle_cnt)
2724 {
2725 if (TRUE == _VPU_EX_MAU_IDLE())
2726 {
2727 break;
2728 }
2729 mau_idle_cnt--;
2730 MsOS_DelayTask(1);
2731 }
2732
2733 if (mau_idle_cnt == 0)
2734 {
2735 printf("MAU idle time out~~~~~\n");
2736 }
2737 }
2738 #endif
2739
2740 // this command set MIU to block R2 (does not ack R2's request)
2741 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2742
2743 #ifdef HAL_FEATURE_MAU
2744 // reset MAU
2745 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2746 tempreg1 |= MAU1_REG_SW_RESET;
2747 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2748 #if defined(UDMA_FPGA_ENVI)
2749 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2750 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2751 #endif
2752 #endif
2753
2754 // reset R2
2755 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2756 // by the same RIU write, the R2 reset signal may reach afifo eralier
2757 // than MIU reset and afifo write pointer will be reset to position 0.
2758 // In this case, afifo consider it is not empty because read/write
2759 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2760 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2761 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2762 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2763 VPU_EX_TimerDelayMS(1);
2764 tempreg &= ~VPU_REG_CPU_R2_EN;
2765 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2766 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2767
2768 VPU_EX_TimerDelayMS(1);
2769
2770 // this command set MIU to accept R2 (can ack R2's request)
2771 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2772
2773 pVPUHalContext->_bVPURsted = FALSE;
2774 return TRUE;
2775 }
2776 /*
2777 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2778 {
2779 MS_U16 tempreg = 0, tempreg1 = 0;
2780 #ifndef HAL_FEATURE_MAU
2781 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2782 tempreg |= VPU_REG_CPU_STALL_EN;
2783 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2784
2785 MS_U32 idle_cnt = 100;// ms
2786 while (idle_cnt)
2787 {
2788 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2789 {
2790 break;
2791 }
2792 idle_cnt--;
2793 MsOS_DelayTask(1);
2794 }
2795
2796 if (idle_cnt == 0)
2797 {
2798 printf("ISB ICU idle time out~~~~~\n");
2799 }
2800
2801 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2802 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2803 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2804 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2805
2806 MS_U32 idle_cnt_1 = 100;// ms
2807 while (idle_cnt_1)
2808 {
2809 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2810 {
2811 break;
2812 }
2813 idle_cnt_1--;
2814 MsOS_DelayTask(1);
2815 }
2816
2817 if (idle_cnt_1 == 0)
2818 {
2819 printf("BIU DCU idle time out~~~~~\n");
2820 }
2821
2822 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2823 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2824 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2825 VPU_EX_TimerDelayMS(1);
2826 tempreg &= ~VPU_REG_CPU_R2_EN;
2827 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2828 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2829
2830 #else
2831 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2832
2833 if (bCheckMauIdle)
2834 {
2835 MS_U32 mau_idle_cnt = 100;// ms
2836 while (mau_idle_cnt)
2837 {
2838 if (TRUE == _VPU_EX_MAU_IDLE())
2839 {
2840 break;
2841 }
2842 mau_idle_cnt--;
2843 MsOS_DelayTask(1);
2844 }
2845
2846 if (mau_idle_cnt == 0)
2847 {
2848 printf("MAU idle time out~~~~~\n");
2849 }
2850 }
2851
2852
2853 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2854
2855 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2856 tempreg1 |= MAU1_REG_SW_RESET;
2857 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2858
2859 #if defined(UDMA_FPGA_ENVI)
2860 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2861 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2862 #endif
2863
2864 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2865 tempreg &= ~VPU_REG_CPU_R2_EN;
2866 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2867 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2868 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2869 #endif
2870 VPU_EX_TimerDelayMS(1);
2871 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2872
2873 pVPUHalContext->_bVPURsted = FALSE;
2874 return TRUE;
2875 }
2876 */
2877 ///-----------------------------------------------------------------------------
2878 /// CPU reset release
2879 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2880 void HAL_VPU_EX_SwRstRelse(void)
2881 {
2882 MS_U16 tempreg = 0;
2883
2884 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2885 tempreg &= ~VPU_REG_CPU_STALL_EN;
2886 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2887
2888 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2889 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2890 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2891 VPU_EX_TimerDelayMS(1);
2892 tempreg |= VPU_REG_CPU_SW_RSTZ;
2893 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2894 VPU_EX_TimerDelayMS(1);
2895 tempreg |= VPU_REG_CPU_R2_EN;
2896 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2897 #ifdef HAL_FEATURE_MAU
2898 MS_U16 tempreg1 = 0;
2899 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2900 tempreg1 &= ~MAU1_REG_SW_RESET;
2901 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2902 #endif
2903 pVPUHalContext->_bVPURsted = TRUE;
2904 }
2905
HAL_VPU_EX_SwRelseMAU(void)2906 void HAL_VPU_EX_SwRelseMAU(void)
2907 {
2908
2909 #ifdef HAL_FEATURE_MAU
2910 MS_U16 tempreg = 0;
2911 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2912 tempreg &= ~MAU1_REG_SW_RESET;
2913 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2914 #endif
2915 }
2916
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2917 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2918 {
2919 MS_U32 u32value = 0;
2920
2921 return u32value;
2922 }
2923
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2924 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2925 {
2926 MS_BOOL bRet = TRUE;
2927
2928 return bRet;
2929 }
2930
2931 ///-----------------------------------------------------------------------------
2932 /// Check AVCH264 Ready or not
2933 /// @return TRUE or FALSE
2934 /// - TRUE, MailBox is free
2935 /// - FALSE, MailBox is busy
2936 /// @param u8MBox \b IN: MailBox to check
2937 /// - AVCH264_HI_MBOX0,
2938 /// - AVCH264_HI_MBOX1,
2939 /// - AVCH264_RISC_MBOX0,
2940 /// - AVCH264_RISC_MBOX1,
2941 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2942 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2943 {
2944 MS_BOOL bResult = FALSE;
2945
2946 switch (u32type)
2947 {
2948 case VPU_HI_MBOX0:
2949 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2950 break;
2951 case VPU_HI_MBOX1:
2952 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2953 break;
2954 case VPU_RISC_MBOX0:
2955 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2956 break;
2957 case VPU_RISC_MBOX1:
2958 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2959 break;
2960 default:
2961 break;
2962 }
2963 return bResult;
2964 }
2965
2966
2967 ///-----------------------------------------------------------------------------
2968 /// Read message from AVCH264
2969 /// @return TRUE or FALSE
2970 /// - TRUE, success
2971 /// - FALSE, failed
2972 /// @param u8MBox \b IN: MailBox to read
2973 /// - AVCH264_RISC_MBOX0
2974 /// - AVCH264_RISC_MBOX1
2975 /// @param u32Msg \b OUT: message read
2976 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2977 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2978 {
2979 MS_BOOL bResult = TRUE;
2980
2981 switch (u32type)
2982 {
2983 case VPU_HI_MBOX0:
2984 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
2985 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
2986 break;
2987 case VPU_HI_MBOX1:
2988 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
2989 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
2990 break;
2991 case VPU_RISC_MBOX0:
2992 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
2993 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
2994 break;
2995 case VPU_RISC_MBOX1:
2996 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
2997 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
2998 break;
2999 default:
3000 *u32Msg = 0;
3001 bResult = FALSE;
3002 break;
3003 }
3004 return bResult;
3005 }
3006
3007 ///-----------------------------------------------------------------------------
3008 /// Mailbox from AVCH264 clear bit resest
3009 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3010 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3011 {
3012 switch (u32type)
3013 {
3014 case VPU_RISC_MBOX0:
3015 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3016 break;
3017 case VPU_RISC_MBOX1:
3018 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3019 break;
3020 default:
3021 break;
3022 }
3023 }
3024
3025 ///-----------------------------------------------------------------------------
3026 /// Send message to AVCH264
3027 /// @return TRUE or FALSE
3028 /// - TRUE, Success
3029 /// - FALSE, Failed
3030 /// @param u8MBox \b IN: MailBox
3031 /// - AVCH264_HI_MBOX0,
3032 /// - AVCH264_HI_MBOX1,
3033 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3034 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3035 {
3036 MS_BOOL bResult = TRUE;
3037
3038 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3039
3040 switch (u32type)
3041 {
3042 case VPU_HI_MBOX0:
3043 {
3044 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3045 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3046 break;
3047 }
3048 case VPU_HI_MBOX1:
3049 {
3050 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3051 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3052 break;
3053 }
3054 default:
3055 {
3056 bResult = FALSE;
3057 break;
3058 }
3059 }
3060
3061 return bResult;
3062 }
3063
HAL_VPU_EX_GetProgCnt(void)3064 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3065 {
3066
3067 MS_U16 expc_l=0;
3068 MS_U16 expc_h=0;
3069 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3070 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3071 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3072 }
3073
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3074 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3075 {
3076 return _VPU_EX_GetOffsetIdx(u32Id);
3077 }
3078
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3079 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3080 {
3081 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3082
3083 if (u32ShmAddr == 0)
3084 {
3085 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3086 }
3087 else
3088 {
3089 if (u8Offset == 0)
3090 {
3091 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3092 }
3093 else if (u8Offset == 1)
3094 {
3095 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3096 }
3097 }
3098
3099 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3100 return;
3101 }
3102
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3103 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3104 {
3105 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3106
3107 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3108 }
3109
3110 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3111 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3112 {
3113 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3114 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3115 MS_VIRT VsyncBridgeOffset = 0;
3116
3117 if (VPUSHMAddr != 0) // TEE project
3118 {
3119 if ((u8Offset == 0) || (u8Offset == 1))
3120 {
3121 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3122 }
3123 else
3124 {
3125 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3126 }
3127 }
3128 else // normal project
3129 {
3130 if ((u8Offset == 0) || (u8Offset == 1))
3131 {
3132 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3133 }
3134 else
3135 {
3136 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3137 }
3138 }
3139
3140 return VsyncBridgeOffset;
3141 }
3142
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3143 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3144 {
3145 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3146 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3147 MS_VIRT VsyncBridgeExtOffset = 0;
3148
3149 if (VPUSHMAddr != 0) // TEE project
3150 {
3151 if ((u8Offset == 0) || (u8Offset == 1))
3152 {
3153 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3154 }
3155 else
3156 {
3157 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3158 }
3159 }
3160 else // normal project
3161 {
3162 if ((u8Offset == 0) || (u8Offset == 1))
3163 {
3164 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3165 }
3166 else
3167 {
3168 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3169 }
3170 }
3171
3172 return VsyncBridgeExtOffset;
3173 }
3174 #endif
3175
HAL_VPU_EX_IsPowered(void)3176 MS_BOOL HAL_VPU_EX_IsPowered(void)
3177 {
3178 return pVPUHalContext->_bVPUPowered;
3179 }
3180
HAL_VPU_EX_IsRsted(void)3181 MS_BOOL HAL_VPU_EX_IsRsted(void)
3182 {
3183 return pVPUHalContext->_bVPURsted;
3184 }
3185
HAL_VPU_EX_IsEVDR2(void)3186 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3187 {
3188 #ifdef EVDR2
3189 return TRUE;
3190 #else
3191 return FALSE;
3192 #endif
3193 }
3194
HAL_VPU_EX_MVDInUsed(void)3195 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3196 {
3197 //MVD is in used for MVD or HVD_TSP mode.
3198 MS_U8 i;
3199 MS_U8 u8UseCnt = 0;
3200
3201 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3202 {
3203 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3204 #ifdef VDEC3
3205 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3206 #endif
3207 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3208 {
3209 u8UseCnt++;
3210 }
3211 }
3212
3213 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3214
3215 if (u8UseCnt != 0)
3216 {
3217 return TRUE;
3218 }
3219 else
3220 {
3221 return FALSE;
3222 }
3223 }
3224
HAL_VPU_EX_HVDInUsed(void)3225 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3226 {
3227 //HVD is in used for HVD or MVD in sub stream.
3228 MS_U8 i;
3229 MS_U8 u8UseCnt = 0;
3230 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3231 {
3232 if (E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3233 {
3234 u8UseCnt++;
3235 }
3236 }
3237
3238 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3239
3240 if (u8UseCnt != 0)
3241 {
3242 return TRUE;
3243 }
3244 else
3245 {
3246 return FALSE;
3247 }
3248 }
3249
HAL_VPU_EX_Mutex_Lock(void)3250 void HAL_VPU_EX_Mutex_Lock(void)
3251 {
3252 _HAL_VPU_Entry();
3253 }
3254
HAL_VPU_EX_Mutex_UnLock(void)3255 void HAL_VPU_EX_Mutex_UnLock(void)
3256 {
3257 _HAL_VPU_Release();
3258 }
3259
3260 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3261 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3262 {
3263 MS_U8 i;
3264 MS_U8 u8UseCnt = 0;
3265
3266 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3267 {
3268 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3269 {
3270 u8UseCnt++;
3271 }
3272 }
3273
3274 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3275
3276 if (u8UseCnt != 0)
3277 {
3278 return TRUE;
3279 }
3280 else
3281 {
3282 return FALSE;
3283 }
3284 }
3285
3286 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3287 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3288 {
3289 MS_U8 i;
3290 MS_U8 u8UseCnt = 0;
3291
3292 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3293 {
3294 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3295 {
3296 u8UseCnt++;
3297 }
3298 }
3299
3300 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3301
3302 if (u8UseCnt != 0)
3303 {
3304 return TRUE;
3305 }
3306 else
3307 {
3308 return FALSE;
3309 }
3310 }
3311 #endif
3312 #endif
3313
3314 //-----------------------------------------------------------------------------
3315 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3316 /// @brief \b Function \b Description: Set debug level
3317 /// @param -elevel \b IN : debug level
3318 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3319 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3320 {
3321 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3322
3323 switch (eLevel)
3324 {
3325 case E_VPU_EX_UART_LEVEL_ERR:
3326 {
3327 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3328 break;
3329 }
3330 case E_VPU_EX_UART_LEVEL_INFO:
3331 {
3332 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3333 break;
3334 }
3335 case E_VPU_EX_UART_LEVEL_DBG:
3336 {
3337 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3338 break;
3339 }
3340 case E_VPU_EX_UART_LEVEL_TRACE:
3341 {
3342 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3343 break;
3344 }
3345 case E_VPU_EX_UART_LEVEL_FW:
3346 {
3347 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3348 break;
3349 }
3350 default:
3351 {
3352 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3353 break;
3354 }
3355 }
3356 }
3357
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3358 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3359 {
3360 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3361 MS_U32 u32CmdArg = (MS_U32)eVerType;
3362 MS_U32 u32Version = 0xFFFFFFFF;
3363 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3364 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3365 {
3366 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3367 return u32Version;
3368 }
3369
3370 MS_BOOL bRet = false;
3371 MS_U32 u32TimeOut = 0xFFFFFFFF;
3372
3373 while(--u32TimeOut)
3374 {
3375 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3376 {
3377 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3378 if (false == bRet)
3379 {
3380 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3381 return u32Version;
3382 }
3383
3384 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3385 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3386 return u32Version;
3387 }
3388 }
3389
3390 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3391
3392 return u32Version;
3393 }
3394
HAL_VPU_EX_NotSupportDS(void)3395 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3396 {
3397 return FALSE;
3398 }
3399
3400 //-----------------------------------------------------------------------------
3401 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3402 /// @brief \b Function \b Description: Get VPU MIU base address
3403 /// @return - vpu MIU1 base
3404 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3405 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3406 {
3407 return VPU_MIU1BASE_ADDR;
3408 }
3409
3410
HAL_VPU_EX_GetSHMAddr(void)3411 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3412 {
3413 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3414 {
3415 return 0;
3416 }
3417 return pVPUHalContext->u32VPUSHMAddr;
3418 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3419 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3420 {
3421 pVPUHalContext->bEnableVPUSecureMode = enable;
3422 return TRUE;
3423 }
3424
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3425 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3426 {
3427 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3428
3429 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3430 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3431 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3432 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3433 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3434 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3435 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3436 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3437
3438 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3439 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3440 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3441 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3442 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3443 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3444 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3445 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3446 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3447 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3448
3449 return TRUE;
3450 }
3451
3452 //-----------------------------------------------------------------------------
3453 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3454 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3455 /// @return - success/fail
3456 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3457 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3458 {
3459 #define MAX_CAPABILITY_INFO_NUM 8
3460 #define MAX_CODEC_TYPE_NUM 18
3461
3462 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3463 {
3464 //width, height , frmrate, profile, level, version bit rate reserved2
3465 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3466 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3467 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3468 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3469 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3470 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3471 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3472 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3473 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3474 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3475 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3476 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3477 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3478 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3479 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3480 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3481 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3482 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3483 };
3484
3485 if(eCodecType < MAX_CODEC_TYPE_NUM)
3486 {
3487 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3488 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3489 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3490 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3491 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3492 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3493 return TRUE;
3494 }
3495 else
3496 {
3497 return FALSE;
3498 }
3499 }
3500
3501 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3502 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3503 {
3504 (void) u32Id;
3505 BBU_STATE *bbu_state;
3506
3507 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3508 || (eDecType == E_VPU_EX_DECODER_VP8)
3509 #if SUPPORT_G2VP9
3510 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3511 #endif
3512 )
3513 {
3514 // MVD should not call this function.
3515 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3516 return;
3517 }
3518
3519 switch (eDecType)
3520 {
3521 case E_VPU_EX_DECODER_EVD:
3522 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3523 break;
3524 case E_VPU_EX_DECODER_HVD:
3525 case E_VPU_EX_DECODER_RVD:
3526 case E_VPU_EX_DECODER_MVC:
3527 default:
3528 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3529 break;
3530 }
3531
3532 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3533 return;
3534 }
3535
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3536 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3537 {
3538 (void) u32Id;
3539 BBU_STATE *bbu_state;
3540
3541 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3542 || (eDecType == E_VPU_EX_DECODER_VP8)
3543 #if SUPPORT_G2VP9
3544 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3545 #endif
3546 )
3547 {
3548 // MVD should not call this function.
3549 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3550 return TRUE;
3551 }
3552
3553 switch (eDecType)
3554 {
3555 case E_VPU_EX_DECODER_EVD:
3556 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3557 break;
3558 case E_VPU_EX_DECODER_HVD:
3559 case E_VPU_EX_DECODER_RVD:
3560 case E_VPU_EX_DECODER_MVC:
3561 default:
3562 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3563 break;
3564 }
3565
3566 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3567 }
3568
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3569 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3570 {
3571 (void) u32Id;
3572 BBU_STATE *bbu_state;
3573
3574 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3575 || (eDecType == E_VPU_EX_DECODER_VP8)
3576 #if SUPPORT_G2VP9
3577 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3578 #endif
3579 )
3580 {
3581 // MVD should not call this function.
3582 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3583 return;
3584 }
3585
3586 switch (eDecType)
3587 {
3588 case E_VPU_EX_DECODER_EVD:
3589 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3590 break;
3591 case E_VPU_EX_DECODER_HVD:
3592 case E_VPU_EX_DECODER_RVD:
3593 case E_VPU_EX_DECODER_MVC:
3594 default:
3595 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3596 break;
3597 }
3598
3599 if (bbu_state[u32BBUId].u32Used == 0)
3600 {
3601 bbu_state[u32BBUId].u8RegSetting = 0;
3602 }
3603
3604 return;
3605 }
3606
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3607 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3608 {
3609 MS_U32 i, max_bbu_cnt;
3610 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3611
3612 if(pTaskInfo == NULL)
3613 return retBBUId;
3614
3615 BBU_STATE *bbu_state;
3616 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3617 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3618
3619 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3620
3621 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3622
3623 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3624 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3625 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3626
3627 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3628 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3629
3630 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3631 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3632 */
3633 #if 1
3634 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3635 {
3636 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3637 if (bTSP)
3638 {
3639 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3640 {
3641 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3642 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3643 slq_state[u8TaskId].bTSP = TRUE;
3644 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3645 return u8TaskId;
3646 }
3647 }
3648 else
3649 {
3650 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3651 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3652 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3653 {
3654 if (slq_state[i].u32Used != 0)
3655 {
3656 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3657 {
3658 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3659 }
3660 }
3661 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3662 {
3663 avaliable_bbu_idx = i; // recored the first empty bbu
3664 }
3665 }
3666
3667 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3668
3669 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3670 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3671 slq_state[shared_bbu_idx].bTSP = FALSE;
3672 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3673 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3674 return shared_bbu_idx;
3675 }
3676 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3677 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3678 slq_state[u8TaskId].bTSP = FALSE;
3679 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3680
3681 if (bShareBBU == FALSE)
3682 {
3683 slq_state[u8TaskId].bTSP = TRUE;
3684 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3685 }
3686 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3687 return u8TaskId;
3688 }
3689 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3690 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3691 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3692 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3693
3694 if (bShareBBU == FALSE)
3695 {
3696 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3697 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3698 }
3699 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3700 return avaliable_bbu_idx;
3701 }
3702 else {
3703 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3704 }
3705 }
3706 }
3707 #if SUPPORT_G2VP9
3708 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3709 {
3710 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3711 // Don't care the return value, G2_VP9 will not use it.
3712 return 0;
3713 }
3714 #endif
3715 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3716 {
3717 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3718 // Don't care the return value, VP8 will not use it.
3719 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3720 return u8Offset;
3721 //return 0;
3722 }
3723 else
3724 {
3725 switch (pTaskInfo->eDecType)
3726 {
3727 case E_VPU_EX_DECODER_EVD:
3728 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3729 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3730 break;
3731 case E_VPU_EX_DECODER_HVD:
3732 case E_VPU_EX_DECODER_RVD:
3733 case E_VPU_EX_DECODER_MVC:
3734 default:
3735 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3736 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3737 break;
3738 }
3739
3740 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3741 if (bTSP)
3742 {
3743 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3744 {
3745 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3746 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3747 bbu_state[u8TaskId].bTSP = TRUE;
3748 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3749 slq_state[u8TaskId].bTSP = TRUE;
3750 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3751 return u8TaskId;
3752 }
3753 }
3754 else
3755 {
3756 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3757 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3758 for (i = 0; i < max_bbu_cnt; i++)
3759 {
3760 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3761 {
3762 if (bbu_state[i].bTSP == FALSE)
3763 {
3764 shared_bbu_idx = i;
3765 }
3766 }
3767 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3768 {
3769 avaliable_bbu_idx = i;
3770 }
3771 }
3772
3773 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3774
3775 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3776 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3777 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3778 return shared_bbu_idx;
3779 }
3780 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3781 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3782
3783 if (bShareBBU == FALSE)
3784 {
3785 bbu_state[u8TaskId].bTSP = TRUE;
3786 VPRINTF("[NDec] occupy one BBU_ID \n");
3787 }
3788 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3789 return u8TaskId;
3790 }
3791 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3792 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3793
3794 if (bShareBBU == FALSE)
3795 {
3796 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3797 VPRINTF("[NDec] occupy one BBU_ID \n");
3798 }
3799 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3800 return avaliable_bbu_idx;
3801 }
3802 else {
3803 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3804 }
3805 }
3806 }
3807 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3808 MS_U32 j;
3809 MS_BOOL Got = FALSE;
3810 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3811 {
3812 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3813 {
3814 if(slq_state[i].u32Used != 0)
3815 {
3816 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3817 {
3818 retBBUId = i;
3819 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3820 slq_state[retBBUId].bTSP = bTSP;
3821 slq_state[retBBUId].bUsedbyMVD = TRUE;
3822 return retBBUId;
3823 }
3824 }
3825 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3826 {
3827 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3828 {
3829 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3830 {
3831 Got = TRUE;
3832 retBBUId = i;
3833 }
3834 }
3835
3836 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3837 {
3838 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3839 {
3840 Got = TRUE;
3841 retBBUId = i;
3842 }
3843 }
3844
3845 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3846 retBBUId = i;
3847 }
3848 }
3849 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3850 {
3851 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3852 slq_state[retBBUId].bTSP = bTSP;
3853 slq_state[retBBUId].bUsedbyMVD = TRUE;
3854 }
3855 }
3856 #if SUPPORT_G2VP9
3857 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3858 {
3859 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3860 // Don't care the return value, G2_VP9 will not use it.
3861 return 0;
3862 }
3863 #endif
3864 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3865 {
3866 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3867 // Don't care the return value, VP8 will not use it.
3868 return 0;
3869 }
3870 else // HVD/EVD case
3871 {
3872 switch (pTaskInfo->eDecType)
3873 {
3874 case E_VPU_EX_DECODER_EVD:
3875 case E_VPU_EX_DECODER_G2VP9:
3876 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3877 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3878 break;
3879 case E_VPU_EX_DECODER_HVD:
3880 case E_VPU_EX_DECODER_RVD:
3881 case E_VPU_EX_DECODER_MVC:
3882 default:
3883 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3884 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3885 break;
3886 }
3887
3888 for (i = 0; i < max_bbu_cnt; i++)
3889 {
3890 if(bbu_state[i].u32Used != 0)
3891 {
3892 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3893 {
3894 retBBUId = i;
3895 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3896 bbu_state[retBBUId].bTSP = bTSP;
3897 return retBBUId;
3898 }
3899 }
3900 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3901 {
3902 if(i < MAX_MVD_SLQ_COUNT)
3903 {
3904 if(!bTSP) //HVD/EVD first MM case
3905 {
3906 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3907 {
3908 retBBUId = i;
3909 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3910 bbu_state[retBBUId].bTSP = bTSP;
3911 return retBBUId;
3912 }
3913
3914 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3915 retBBUId = i;
3916 }
3917 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3918 {
3919 retBBUId = i;
3920 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3921 bbu_state[retBBUId].bTSP = bTSP;
3922 slq_state[retBBUId].bUsedbyMVD = FALSE;
3923 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3924 slq_state[retBBUId].bTSP = bTSP;
3925 return retBBUId;
3926 }
3927 }
3928 }
3929 }
3930 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3931 {
3932 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3933 bbu_state[retBBUId].bTSP = bTSP;
3934 if(bTSP)
3935 {
3936 slq_state[retBBUId].bUsedbyMVD = FALSE;
3937 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3938 slq_state[retBBUId].bTSP = bTSP;
3939 }
3940 }
3941 }
3942 #endif
3943 return retBBUId;
3944 }
3945
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3946 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3947 {
3948 MS_U32 max_bbu_cnt;
3949 BBU_STATE *bbu_state;
3950 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3951
3952 if(pTaskInfo == NULL)
3953 return FALSE;
3954 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3955 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3956
3957 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3958 /* MS_U32 i;
3959 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3960 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3961
3962 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3963 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3964
3965 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3966 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3967 */
3968 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3969 {
3970 // TO DO
3971 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3972 {
3973 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3974 slq_state[u32BBUId].bTSP = FALSE;
3975 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3976 return TRUE;
3977 }
3978 }
3979 #if SUPPORT_G2VP9
3980 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3981 {
3982 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3983 return TRUE;
3984 }
3985 #endif
3986 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3987 {
3988 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3989 return TRUE;
3990 }
3991 else
3992 {
3993 switch (pTaskInfo->eDecType)
3994 {
3995 case E_VPU_EX_DECODER_EVD:
3996 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3997 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3998 break;
3999 case E_VPU_EX_DECODER_HVD:
4000 case E_VPU_EX_DECODER_RVD:
4001 case E_VPU_EX_DECODER_MVC:
4002 default:
4003 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4004 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4005 break;
4006 }
4007
4008 if (u32BBUId < max_bbu_cnt)
4009 {
4010 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4011 bbu_state[u32BBUId].bTSP = FALSE;
4012
4013 if (bTSP)
4014 {
4015 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4016 slq_state[u32BBUId].bTSP = FALSE;
4017 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4018 }
4019
4020 #if 1
4021 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4022 #else
4023 if (bbu_state[u32BBUId].u32Used == 0)
4024 {
4025 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4026 }
4027 #endif
4028
4029 return TRUE;
4030 }
4031 }
4032 return FALSE;
4033 }
4034
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4035 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4036 {
4037 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4038
4039 if (CHECK_NULL_PTR(pstVBBU))
4040 return 0;
4041 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4042 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4043 MS_U32 u32Vacancy = 0;
4044
4045 if (u32WrPtr == u32RdPtr)
4046 {
4047 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4048 }
4049 else if (u32WrPtr > u32RdPtr)
4050 {
4051 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4052 }
4053 else
4054 {
4055 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4056 }
4057
4058 return u32Vacancy;
4059 }
4060
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4061 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4062 {
4063 return MAX_VDEC_VBBU_ENTRY_COUNT;
4064 }
4065
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4066 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4067 {
4068 return pVPUHalContext->u32FWCodeAddr;
4069 }
4070
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4071 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4072 {
4073 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4074 #if SUPPORT_G2VP9
4075 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4076 #endif
4077
4078 if (CHECK_NULL_PTR(pstVBBU))
4079 return FALSE;
4080 MsOS_ReadMemory();
4081 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4082
4083 if(NULL == stEntry)
4084 {
4085 return 0;
4086 }
4087
4088 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4089 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4090 {
4091 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4092 }
4093 else
4094 {
4095 #if SUPPORT_G2VP9
4096 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4097 {
4098 if (stEntry->u32Offset == 0)
4099 return 0;
4100 else
4101 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4102 }
4103 else
4104 #endif
4105 {
4106 return stEntry->u32Offset;
4107 }
4108 }
4109 }
4110
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4111 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4112 {
4113 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4114 VDEC_VBBU_Entry *stEntry;
4115 #if SUPPORT_G2VP9
4116 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4117 #endif
4118
4119 MsOS_ReadMemory();
4120 if (CHECK_NULL_PTR(pstVBBU))
4121 return 0;
4122 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4123
4124 if (u32WrPtr == 0)
4125 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4126 else
4127 u32WrPtr--;
4128
4129 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4130
4131 if(NULL == stEntry)
4132 {
4133 return 0;
4134 }
4135
4136 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4137 #if SUPPORT_G2VP9
4138 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4139 {
4140 if (stEntry->u32Offset == 0)
4141 return 0;
4142 else
4143 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4144 }
4145 else
4146 #endif
4147 {
4148 return stEntry->u32Offset + stEntry->u32Length;
4149 }
4150 }
4151
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4152 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4153 {
4154 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4155 #if SUPPORT_G2VP9
4156 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4157 #endif
4158
4159 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4160 return FALSE;
4161 MsOS_ReadMemory();
4162 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4163 MS_U32 u32NewWrPtr;
4164
4165 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4166 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4167 {
4168 u32NewWrPtr = 0;
4169 }
4170
4171 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4172
4173 stEntry->u32Offset = stVpuPkt->u32Offset;
4174
4175 #if SUPPORT_G2VP9
4176 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4177 {
4178 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4179 }
4180 #endif
4181
4182 stEntry->u32Length = stVpuPkt->u32Length;
4183 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4184 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4185 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4186
4187 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4188
4189 pstVBBU->u32WrPtr = u32NewWrPtr;
4190
4191 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4192
4193 MsOS_FlushMemory();
4194
4195 return TRUE;
4196 }
4197
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4198 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4199 {
4200 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4201
4202 if (CHECK_NULL_PTR(pstVBBU))
4203 return FALSE;
4204 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4205 }
4206
4207 ///-----------------------------------------------------------------------------
4208 /// specify the command send to Mail box or DRAM
4209 /// @return TRUE or FALSE
4210 /// - TRUE, Mail box
4211 /// - FALSE, Dram
4212 /// @param u32Cmd \b IN: Command is going to be sned
4213 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4214 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4215 {
4216 MS_BOOL bResult = TRUE;
4217
4218 switch (u32Cmd)
4219 {
4220 // *********** Runtime action Command
4221 /* case E_HVD_CMD_RELEASE_DISPQ:
4222 case E_HVD_CMD_UPDATE_DISPQ:
4223 case E_HVD_CMD_FLUSH_DEC_Q:
4224 case E_HVD_CMD_FLUSH:
4225 case E_HVD_CMD_PLAY:
4226 case E_HVD_CMD_PAUSE:
4227 case E_HVD_CMD_STOP:
4228 case E_HVD_CMD_STEP_DECODE:
4229 case E_HVD_CMD_SKIP_DEC:
4230 case E_HVD_CMD_DISP_I_DIRECT:*/
4231 // *********** Dual-Stream Create Task Command
4232 case E_DUAL_CMD_TASK0_HVD_BBU:
4233 case E_DUAL_CMD_TASK0_HVD_TSP:
4234 case E_DUAL_CMD_TASK0_MVD_SLQ:
4235 case E_DUAL_CMD_TASK0_MVD_TSP:
4236 case E_DUAL_CMD_TASK1_HVD_BBU:
4237 case E_DUAL_CMD_TASK1_HVD_TSP:
4238 case E_DUAL_CMD_MODE:
4239 #ifndef _WIN32
4240 case E_DUAL_CMD_TASK1_MVD_SLQ:
4241 case E_DUAL_CMD_TASK1_MVD_TSP:
4242 #endif
4243 case E_DUAL_CMD_DEL_TASK:
4244 case E_DUAL_CMD_SINGLE_TASK:
4245 case E_DUAL_VERSION:
4246 case E_DUAL_R2_CMD_EXIT:
4247 case E_DUAL_CMD_STC_MODE:
4248 #ifdef VDEC3
4249 case E_DUAL_R2_CMD_FBADDR:
4250 case E_DUAL_R2_CMD_FBSIZE:
4251 // *********** N-Streams
4252 case E_NST_CMD_TASK_HVD_TSP:
4253 case E_NST_CMD_TASK_HVD_BBU:
4254 case E_NST_CMD_TASK_MVD_TSP:
4255 case E_NST_CMD_TASK_MVD_SLQ:
4256 case E_NST_CMD_DEL_TASK:
4257 case E_NST_CMD_COMMON_MASK:
4258 case E_NST_CMD_COMMON_CMD1:
4259 #endif
4260 case E_DUAL_CMD_COMMON:
4261 {
4262 bResult = TRUE;
4263 }
4264 break;
4265 default:
4266 {
4267 bResult = FALSE;
4268 }
4269 break;
4270 }
4271
4272 return bResult;
4273 }
4274
4275 ///-----------------------------------------------------------------------------
4276 /// specify the command send to Mail box or DRAM
4277 /// @return TRUE or FALSE
4278 /// - TRUE, Mail box
4279 /// - FALSE, Dram
4280 /// @param u32Cmd \b IN: Command is going to be sned
4281 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4282 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4283 {
4284 MS_BOOL bResult = TRUE;
4285
4286 switch (u32Cmd)
4287 {
4288 // *********** Runtime action Command
4289 case E_HVD_CMD_RELEASE_DISPQ:
4290 case E_HVD_CMD_UPDATE_DISPQ:
4291 case E_HVD_CMD_FLUSH_DEC_Q:
4292 case E_HVD_CMD_PAUSE:
4293 case E_HVD_CMD_FLUSH:
4294 case E_HVD_CMD_PLAY:
4295 case E_HVD_CMD_STOP:
4296 case E_HVD_CMD_SKIP_DEC:
4297 case E_HVD_CMD_DISP_I_DIRECT:
4298 case E_HVD_CMD_STEP_DECODE:
4299 case E_HVD_CMD_INC_DISPQ_NUM:
4300 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4301 {
4302 bResult = TRUE;
4303 }
4304 break;
4305 default:
4306 {
4307 bResult = FALSE;
4308 }
4309 break;
4310 }
4311
4312 return bResult;
4313 }
4314
4315 ///-----------------------------------------------------------------------------
4316 /// Send message to HVD stream command queue
4317 /// @return TRUE or FALSE
4318 /// - TRUE, Success
4319 /// - FALSE, Failed
4320 /// @param u32DramAddr \b IN: address to be writen
4321 /// @param u32Msg \b IN: data to be writen
4322 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4323 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4324 {
4325 MS_BOOL bResult = TRUE;
4326
4327 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4328
4329 WRITE_LONG(u32DramAddr,u32Msg);
4330
4331 return bResult;
4332 }
4333
4334 ///-----------------------------------------------------------------------------
4335 /// Read task share memory to specify that task command queue is empty or not
4336 /// @return TRUE or FALSE
4337 /// - TRUE, Empty
4338 /// - FALSE, Non empty
4339 /// @param u32Id \b IN: Task information
4340 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4341 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4342 {
4343 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4344 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4345 if (!cmd_q)
4346 {
4347 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4348 return FALSE;
4349 }
4350
4351 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4352 }
4353
4354 ///-----------------------------------------------------------------------------
4355 /// Read task share memory to specify that task command queue is full or not
4356 /// @return TRUE or FALSE
4357 /// - TRUE, Full
4358 /// - FALSE, Non full
4359 /// @param u32Id \b IN: Task information
4360 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4361 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4362 {
4363 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4364 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4365 if (!cmd_q)
4366 {
4367 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4368 return TRUE;
4369 }
4370 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4371
4372 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4373 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4374
4375 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4376 }
4377
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4378 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4379 {
4380 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4381 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4382 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4383
4384 #if HVD_ENABLE_MVC
4385 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4386 {
4387 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4388 }
4389 #endif
4390
4391 if (CHECK_NULL_PTR(cmd_q))
4392 {
4393 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4394 return bResult;
4395 }
4396 MS_VIRT u32CmdQWdPtr;
4397
4398 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4399 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4400
4401 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4402 return E_HVD_COMMAND_QUEUE_FULL;
4403 else
4404 {
4405 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4406 }
4407
4408 switch (u8CmdType)
4409 {
4410 case E_HVD_CMDQ_CMD:
4411 {
4412 u32Msg |= (u8TaskID << 24);
4413 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4414
4415 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4416
4417 if (bResult)
4418 {
4419 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4420
4421 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4422 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4423
4424 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4425 }
4426 break;
4427 }
4428 case E_HVD_CMDQ_ARG:
4429 {
4430 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4431 if (bResult)
4432 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4433 break;
4434 }
4435 default:
4436 {
4437 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4438 break;
4439 }
4440 }
4441
4442 MsOS_FlushMemory();
4443
4444 return bResult;
4445 }
4446
4447 ///-----------------------------------------------------------------------------
4448 /// Read task share memory to specify that task display command queue is empty or not
4449 /// @return TRUE or FALSE
4450 /// - TRUE, Empty
4451 /// - FALSE, Non empty
4452 /// @param u32Id \b IN: Task information
4453 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4454 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4455 {
4456 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4457 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4458 if (!cmd_q)
4459 {
4460 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4461 return FALSE;
4462 }
4463
4464 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4465 }
4466
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4467 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4468 {
4469 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4470 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4471 if (!cmd_q)
4472 {
4473 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4474 return TRUE;
4475 }
4476
4477 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4478
4479 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4480 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4481
4482 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4483 }
4484
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4485 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4486 {
4487 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4488 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4489 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4490
4491 #if HVD_ENABLE_MVC
4492 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4493 {
4494 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4495 }
4496 #endif
4497
4498 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4499 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4500
4501 if (CHECK_NULL_PTR(cmd_q))
4502 {
4503 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4504 return bResult;
4505 }
4506
4507 MS_VIRT u32DISPCMDQWdPtr;
4508
4509 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4510 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4511
4512 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4513 return E_HVD_COMMAND_QUEUE_FULL;
4514 else
4515 {
4516 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4517 }
4518
4519 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4520
4521 switch (u8CmdType)
4522 {
4523 case E_HVD_CMDQ_CMD:
4524 {
4525 u32Msg |= (u8TaskID << 24);
4526 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4527
4528 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4529
4530 if (bResult)
4531 {
4532 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4533
4534 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4535 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4536
4537 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4538 }
4539 break;
4540 }
4541 case E_HVD_CMDQ_ARG:
4542 {
4543 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4544 if (bResult)
4545 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4546 break;
4547 }
4548 default:
4549 {
4550 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4551 break;
4552 }
4553 }
4554
4555 MsOS_FlushMemory();
4556
4557 return bResult;
4558 }
4559
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4560 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4561 {
4562 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4563 MS_U32 u32StAddr;
4564 MS_U8 u8TmpMiuSel;
4565
4566 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4567
4568 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4569
4570 return TRUE;
4571 }
4572 #endif
4573
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4574 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4575 {
4576 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4577
4578 if(u32address >= HAL_MIU1_BASE)
4579 {
4580 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4581 }
4582 else
4583 {
4584 pVPUHalContext->u32DynamicFBAddress = u32address;
4585 }
4586
4587 pVPUHalContext->u32DynamicFBSize = u32Size;
4588 }
4589
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4590 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4591 {
4592 MS_SIZE FrameBufferSize = 0;
4593
4594 switch(eCodecType)
4595 {
4596 case E_VPU_EX_CODEC_TYPE_MPEG2:
4597 case E_VPU_EX_CODEC_TYPE_H263:
4598 case E_VPU_EX_CODEC_TYPE_MPEG4:
4599 case E_VPU_EX_CODEC_TYPE_DIVX311:
4600 case E_VPU_EX_CODEC_TYPE_DIVX412:
4601 case E_VPU_EX_CODEC_TYPE_FLV:
4602 FrameBufferSize = 0x1E00000;
4603 break;
4604 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4605 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4606 FrameBufferSize = 0x6C00000;
4607 break;
4608 case E_VPU_EX_CODEC_TYPE_RV8:
4609 case E_VPU_EX_CODEC_TYPE_RV9:
4610 FrameBufferSize = 0x1B00000;
4611 break;
4612 case E_VPU_EX_CODEC_TYPE_VP8:
4613 FrameBufferSize = 0x1500000;
4614 break;
4615 case E_VPU_EX_CODEC_TYPE_H264:
4616 FrameBufferSize = 0x8200000;
4617 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4618 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4619 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4620 break;
4621 case E_VPU_EX_CODEC_TYPE_AVS:
4622 FrameBufferSize = 0x1B00000;
4623 break;
4624 case E_VPU_EX_CODEC_TYPE_MJPEG:
4625 FrameBufferSize = 0x2800000;
4626 break;
4627 case E_VPU_EX_CODEC_TYPE_MVC:
4628 FrameBufferSize = 0x4200000;
4629 break;
4630 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4631 FrameBufferSize = 0xB000000;
4632 break;
4633 case E_VPU_EX_CODEC_TYPE_HEVC:
4634 #if SUPPORT_MSVP9
4635 case E_VPU_EX_CODEC_TYPE_VP9:
4636 #endif
4637 FrameBufferSize = 0xA000000;
4638 break;
4639 #if !SUPPORT_MSVP9
4640 case E_VPU_EX_CODEC_TYPE_VP9:
4641 FrameBufferSize = 0x7800000;
4642 break;
4643 #endif
4644 default:
4645 FrameBufferSize = 0;
4646 break;
4647 }
4648
4649 return FrameBufferSize;
4650 }
4651
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4652 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4653 {
4654 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4655 }
4656
4657 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4658 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4659 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4660 {
4661 MS_SIZE FrameBufferSize = 0;
4662
4663 if (!offset || !length)
4664 return FALSE;
4665
4666 total_length -= unUseSize;
4667 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4668 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4669
4670 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4671
4672 if(FrameBufferSize == 0)
4673 {
4674 return FALSE;
4675 }
4676 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4677 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4678 if (total_length < FrameBufferSize)
4679 {
4680 *offset = unUseSize;
4681 *length = total_length;
4682 }
4683 else // todo, dual decode case
4684 {
4685 *offset = unUseSize;
4686 *length = FrameBufferSize;
4687 }
4688 return TRUE;
4689 }
4690
4691 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4692 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4693 {
4694 MS_S32 handle;
4695 switch(eClkPortType)
4696 {
4697 case E_VPU_EX_CLKPORT_MVD:
4698 {
4699 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4700 if(bEnable)
4701 {
4702 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4703 }
4704 else
4705 {
4706 Drv_Clkm_Clk_Gate_Disable(handle);
4707 }
4708 break;
4709 }
4710 case E_VPU_EX_CLKPORT_MVD_CORE:
4711 {
4712 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4713 if(bEnable)
4714 {
4715 Drv_Clkm_Set_Clk_Source(handle, "");
4716 }
4717 else
4718 {
4719 Drv_Clkm_Clk_Gate_Disable(handle);
4720 }
4721 break;
4722 }
4723 case E_VPU_EX_CLKPORT_MVD_PAS:
4724 {
4725 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4726 if(bEnable)
4727 {
4728 Drv_Clkm_Set_Clk_Source(handle, "");
4729 }
4730 else
4731 {
4732 Drv_Clkm_Clk_Gate_Disable(handle);
4733 }
4734 break;
4735 }
4736 case E_VPU_EX_CLKPORT_HVD:
4737 {
4738 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4739 if(bEnable)
4740 {
4741 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4742 }
4743 else
4744 {
4745 Drv_Clkm_Clk_Gate_Disable(handle);
4746 }
4747 break;
4748 }
4749 case E_VPU_EX_CLKPORT_HVD_IDB:
4750 {
4751 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4752 if(bEnable)
4753 {
4754 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4755 }
4756 else
4757 {
4758 Drv_Clkm_Clk_Gate_Disable(handle);
4759 }
4760 break;
4761 }
4762 case E_VPU_EX_CLKPORT_HVD_AEC:
4763 {
4764 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4765 if(bEnable)
4766 {
4767 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4768 }
4769 else
4770 {
4771 Drv_Clkm_Clk_Gate_Disable(handle);
4772 }
4773 break;
4774 }
4775 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4776 {
4777 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4778 if(bEnable)
4779 {
4780 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4781 }
4782 else
4783 {
4784 Drv_Clkm_Clk_Gate_Disable(handle);
4785 }
4786 break;
4787 }
4788 case E_VPU_EX_CLKPORT_VP8:
4789 {
4790 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4791 if(bEnable)
4792 {
4793 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4794 }
4795 else
4796 {
4797 Drv_Clkm_Clk_Gate_Disable(handle);
4798 }
4799 break;
4800 }
4801 case E_VPU_EX_CLKPORT_EVD:
4802 {
4803 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4804 if(bEnable)
4805 {
4806 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4807 }
4808 else
4809 {
4810 Drv_Clkm_Clk_Gate_Disable(handle);
4811 }
4812 break;
4813 }
4814 case E_VPU_EX_CLKPORT_EVD_PPU:
4815 {
4816 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4817 if(bEnable)
4818 {
4819 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4820 }
4821 else
4822 {
4823 Drv_Clkm_Clk_Gate_Disable(handle);
4824 }
4825 break;
4826 }
4827 case E_VPU_EX_CLKPORT_EVD_LITE:
4828 {
4829 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4830 if(bEnable)
4831 {
4832 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4833 }
4834 else
4835 {
4836 Drv_Clkm_Clk_Gate_Disable(handle);
4837 }
4838 break;
4839 }
4840 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4841 {
4842 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4843 if(bEnable)
4844 {
4845 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4846 }
4847 else
4848 {
4849 Drv_Clkm_Clk_Gate_Disable(handle);
4850 }
4851 break;
4852 }
4853 case E_VPU_EX_CLKPORT_VD_MHEG5:
4854 {
4855 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4856 if(bEnable)
4857 {
4858 Drv_Clkm_Set_Clk_Source(handle, "");
4859 }
4860 else
4861 {
4862 Drv_Clkm_Clk_Gate_Disable(handle);
4863 }
4864 break;
4865 }
4866 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4867 {
4868 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4869 if(bEnable)
4870 {
4871 Drv_Clkm_Set_Clk_Source(handle, "");
4872 }
4873 else
4874 {
4875 Drv_Clkm_Clk_Gate_Disable(handle);
4876 }
4877 break;
4878 }
4879 }
4880 }
4881 #endif //#ifdef CONFIG_MSTAR_CLKM
4882
HAL_VPU_EX_strcmp(const char * string1,const char * string2)4883 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
4884 {
4885 int iRet, i;
4886
4887 i = 0;
4888 while(string1[i] || string2[i])
4889 {
4890 iRet = string1[i] - string2[i];
4891 if(iRet)
4892 {
4893 return iRet;
4894 }
4895 i++;
4896 }
4897 return 0;
4898 }
4899
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)4900 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
4901 {
4902 typedef enum
4903 {
4904 E_CAP_NDEC_FB_MIU_SELECT,
4905 E_CAP_NDEC_NSTREAM_FB_SIZE,
4906 E_CAP_NDEC_NSTREAM_BS_SIZE,
4907 E_CAP_NDEC_SUPPORT_SHAREBBU,
4908 E_CAP_SUPPORT_ALLOCATOR,
4909
4910 } VPU_EX_GetCapabilityCmdId;
4911
4912 typedef struct
4913 {
4914 MS_U8 u8CmdId;
4915 MS_U8 u8CmdName[32];
4916
4917 } VPU_EX_GetCapabilityCmd;
4918
4919 static VPU_EX_GetCapabilityCmd stCapCmd[] =
4920 {
4921 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
4922 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
4923 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
4924 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
4925 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
4926 };
4927
4928 MS_U32 bRet = FALSE;
4929 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
4930 MS_U32 u32CmdCnt;
4931
4932 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
4933 {
4934 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
4935 {
4936 bRet = TRUE;
4937 switch(stCapCmd[u32CmdCnt].u8CmdId)
4938 {
4939 case E_CAP_NDEC_FB_MIU_SELECT:
4940 {
4941 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4942 *pSupport = FALSE;
4943 }
4944 break;
4945
4946 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
4947 case E_CAP_NDEC_NSTREAM_FB_SIZE:
4948 {
4949 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4950 *pSize = 0;
4951 }
4952 break;
4953
4954 // FIXME: Patch for waiting dynamic bitstream buffer
4955 case E_CAP_NDEC_NSTREAM_BS_SIZE:
4956 {
4957 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4958 *pSize = 0;
4959 }
4960 break;
4961
4962 case E_CAP_NDEC_SUPPORT_SHAREBBU:
4963 {
4964 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
4965 *pbSupportShareBBU = FALSE;
4966 }
4967 break;
4968
4969 case E_CAP_SUPPORT_ALLOCATOR:
4970 {
4971 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4972 *pSupport = FALSE;
4973 }
4974 break;
4975
4976 default:
4977 bRet = FALSE;
4978 break;
4979 }
4980 }
4981 }
4982
4983 return bRet;
4984 }
4985
4986 #else
4987 #include "halVPU_EX.h"
4988 #include "drvMMIO.h"
4989 #include "../../../../vdec_v2/hal/maserati/hvd_ex/regHVD_EX.h"
4990 #include "halCHIP.h"
4991
4992 #if defined(MSOS_TYPE_NUTTX)
4993 extern int lib_lowprintf(const char *fmt, ...);
4994 #define PRINTF lib_lowprintf
4995 #elif defined(MSOS_TYPE_OPTEE)
4996 #define PRINTF printf
4997 #endif
4998
4999 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5000 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5001
5002 MS_U8 u8FW_Binary[] = {
5003 #include "fwVPU.dat"
5004 };
5005
5006 MS_U32 u32HVDRegOSBase;
5007
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5008 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5009 {
5010 //PRINTF("do load code,u32DestAddr %x\n",addr);
5011 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5012 MAsm_CPU_Sync();
5013 MsOS_FlushMemory();
5014
5015 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5016 {
5017 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5018 return FALSE;
5019 }
5020 return TRUE;
5021 }
5022
HAL_VPU_EX_SetLockDownRegister(void * param)5023 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5024 {
5025 #if 1
5026 MS_PHY u32StAddr_main;
5027 MS_PHY u32StAddr_sub;
5028 MS_U32 u32NonPMBankSize = 0;
5029 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5030
5031 if(param == NULL)
5032 {
5033 return FALSE;
5034 }
5035
5036 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5037
5038 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5039
5040 // ES buffer
5041 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5042 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5043
5044
5045 MS_PHY u32StartOffset;
5046 MS_U8 u8MiuSel;
5047
5048 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5049 u32StAddr_main = u32StartOffset;
5050
5051 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5052 u32StAddr_sub = u32StartOffset;
5053
5054 //Lock down register
5055 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5056 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5057
5058 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
5059 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
5060 //~
5061
5062 // Lock Down
5063 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5064 //~
5065 #endif
5066 return TRUE;
5067 }
5068 #endif
5069