1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147
148
149 #ifdef MSOS_TYPE_LINUX_KERNEL
150 #define VPRINTF printk
151 #elif defined( MSOS_TYPE_ECOS)
152 #define VPRINTF diag_printf
153 #else
154 #ifndef ANDROID
155 #define VPRINTF printf
156 #else
157 #include <sys/mman.h>
158 #include <cutils/ashmem.h>
159 #include <cutils/log.h>
160 #define VPRINTF ALOGD
161 #endif
162 #endif
163
164 #ifdef CONFIG_MSTAR_CLKM
165 #include "drvCLKM.h"
166 #endif
167 //-------------------------------------------------------------------------------------------------
168 // Driver Compiler Options
169 //-------------------------------------------------------------------------------------------------
170
171
172 //-------------------------------------------------------------------------------------------------
173 // Local Defines
174 //-------------------------------------------------------------------------------------------------
175 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
176
177 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
178 #ifdef VDEC3
179 #define MAX_EVD_BBU_COUNT 4 // This definition is chip-dependent.
180 #define MAX_HVD_BBU_COUNT 4 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
181 #define MAX_MVD_SLQ_COUNT 4
182 #define MAX_SUPPORT_DECODER_NUM 16
183 #else
184 #define MAX_SUPPORT_DECODER_NUM 2
185 #endif
186 typedef enum
187 {
188 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
189 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
190 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
191 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
192
193
194 typedef enum
195 {
196 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
197 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
198 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
199 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
200 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
201 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
202
203 typedef enum
204 {
205 E_VPU_UART_CTRL_DISABLE = BIT(4),
206 E_VPU_UART_CTRL_ERR = BIT(0),
207 E_VPU_UART_CTRL_INFO = BIT(1),
208 E_VPU_UART_CTRL_DBG = BIT(2),
209 E_VPU_UART_CTRL_FW = BIT(3),
210 E_VPU_UART_CTRL_MUST = BIT(4),
211 E_VPU_UART_CTRL_TRACE = BIT(5),
212 } VPU_EX_UartCtrl;
213
214 typedef struct
215 {
216 HAL_VPU_StreamId eStreamId;
217 VPU_EX_DecoderType eDecodertype;
218 } VPU_EX_Stream;
219
220 typedef struct
221 {
222 MS_BOOL bSTCSetMode;
223 MS_U32 u32STCIndex;
224 } VPU_EX_STC;
225
226 #define VPU_MSG_ERR(format, args...) \
227 do \
228 { \
229 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
230 { \
231 VPRINTF("[VPU][ERR]%s:", __FUNCTION__); \
232 VPRINTF(format, ##args); \
233 } \
234 } while (0)
235
236 #define VPU_MSG_DBG(format, args...) \
237 do \
238 { \
239 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
240 { \
241 VPRINTF("[VPU][DBG]%s:", __FUNCTION__); \
242 VPRINTF(format, ##args); \
243 } \
244 } while (0)
245
246 #define VPU_MSG_INFO(format, args...) \
247 do \
248 { \
249 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
250 { \
251 VPRINTF("[VPU][INF]%s:", __FUNCTION__); \
252 VPRINTF(format, ##args); \
253 } \
254 } while (0)
255
256 //------------------------------ MIU SETTINGS ----------------------------------
257 //#ifdef EVDR2
258 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
259 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
260 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(3))
261
262 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
263 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
264 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(3))
265
266
267
268 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
269 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
270 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) ) //g03
271 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
272 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
273 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == BIT(3)) ) //g03
274
275 //#endif
276
277
278
279 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
280 do \
281 { \
282 if (miu_clients##_ON_MIU0 == 1) \
283 { \
284 _MaskMiuReq_##miu_clients(mask); \
285 } \
286 else \
287 { \
288 if (miu_clients##_ON_MIU1 == 1) \
289 { \
290 _MaskMiu1Req_##miu_clients(mask); \
291 } \
292 \
293 } \
294 } while(0)
295
296
297
298
299 #if ENABLE_VPU_MUTEX_PROTECTION
300 MS_S32 s32VPUMutexID = -1;
301 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
302
303 #define _HAL_VPU_MutexCreate() \
304 if (s32VPUMutexID < 0) \
305 { \
306 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
307 }
308
309 #define _HAL_VPU_MutexDelete() \
310 if (s32VPUMutexID >= 0) \
311 { \
312 MsOS_DeleteMutex(s32VPUMutexID); \
313 s32VPUMutexID = -1; \
314 }
315
316 #define _HAL_VPU_Entry() \
317 if (s32VPUMutexID >= 0) \
318 { \
319 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
320 { \
321 VPRINTF("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
322 } \
323 }
324
325 #define _HAL_VPU_Return(_ret) \
326 { \
327 if (s32VPUMutexID >= 0) \
328 { \
329 MsOS_ReleaseMutex(s32VPUMutexID); \
330 } \
331 return _ret; \
332 }
333
334 #define _HAL_VPU_Release() \
335 { \
336 if (s32VPUMutexID >= 0) \
337 { \
338 MsOS_ReleaseMutex(s32VPUMutexID); \
339 } \
340 }
341 #else
342 #define _HAL_VPU_MutexCreate()
343 #define _HAL_VPU_MutexDelete()
344 #define _HAL_VPU_Entry()
345 #define _HAL_VPU_Return(_ret) {return _ret;}
346 #define _HAL_VPU_Release()
347 #endif
348
349 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
350 #define VPU_CMD_TIMEOUT 1000 // 1 sec
351
352 //-------------------------------------------------------------------------------------------------
353 // Local Structures
354 //-------------------------------------------------------------------------------------------------
355 typedef struct _VPU_HWInitFunc
356 {
357 MS_BOOL (*pfMVDHW_Init)(void);
358 MS_BOOL (*pfMVDHW_Deinit)(void);
359 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
360 MS_BOOL (*pfHVDHW_Deinit)(void);
361 } VPU_HWInitFunc;
362
363 typedef struct
364 {
365 MS_U32 u32ApiHW_Version; //<Version of current structure>
366 MS_U16 u16ApiHW_Length; //<Length of this structure>
367
368 MS_U8 u8Cap_Support_Decoder_Num;
369
370 MS_BOOL bCap_Support_MPEG2;
371 MS_BOOL bCap_Support_H263;
372 MS_BOOL bCap_Support_MPEG4;
373 MS_BOOL bCap_Support_DIVX311;
374 MS_BOOL bCap_Support_DIVX412;
375 MS_BOOL bCap_Support_FLV;
376 MS_BOOL bCap_Support_VC1ADV;
377 MS_BOOL bCap_Support_VC1MAIN;
378
379 MS_BOOL bCap_Support_RV8;
380 MS_BOOL bCap_Support_RV9;
381 MS_BOOL bCap_Support_H264;
382 MS_BOOL bCap_Support_AVS;
383 MS_BOOL bCap_Support_AVS_PLUS;
384 MS_BOOL bCap_Support_MJPEG;
385 MS_BOOL bCap_Support_MVC;
386 MS_BOOL bCap_Support_VP8;
387 MS_BOOL bCap_Support_VP9;
388 MS_BOOL bCap_Support_HEVC;
389
390 /*New HW Cap and Feature add in struct at the end*/
391 }VDEC_HwCap;
392
393 //-------------------------------------------------------------------------------------------------
394 // Local Functions Prototype
395 //-------------------------------------------------------------------------------------------------
396 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
397 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
398 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
399
400 //-------------------------------------------------------------------------------------------------
401 // Global Variables
402 //-------------------------------------------------------------------------------------------------
403 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
404 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
405 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
406 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
407 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
408 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
409 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
410 #if SUPPORT_G2VP9 && defined(VDEC3)
411 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
412 #endif
413 #if defined (__aeon__)
414 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
415 #else
416 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
417 #endif
418
419 //-------------------------------------------------------------------------------------------------
420 // Local Variables
421 //-------------------------------------------------------------------------------------------------
422 #if 0
423
424 static MS_BOOL _bVPUPowered = FALSE;
425 static MS_BOOL _bVPURsted = FALSE;
426 static MS_BOOL _bVPUSingleMode = FALSE;
427 static VPU_EX_DecModCfg _stVPUDecMode;
428
429 static MS_U8 u8TaskCnt = 0;
430
431 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
432
433 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
434 static VPU_EX_Stream _stVPUStream[] =
435 {
436 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
437 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
438 };
439 static VPU_HWInitFunc stHWInitFunc =
440 {
441 &HAL_MVD_InitHW,
442 &HAL_MVD_DeinitHW,
443 &HAL_HVD_EX_InitHW,
444 &HAL_HVD_EX_DeinitHW,
445 };
446
447 #endif
448
449 #if VPU_ENABLE_EMBEDDED_FW_BINARY
450 static const MS_U8 u8HVD_FW_Binary[] = {
451 #include "fwVPU.dat"
452 };
453
454 #if HVD_ENABLE_RV_FEATURE
455 static const MS_U8 u8HVD_VLC_Binary[] = {
456 #include "fwVPU_VLC.dat"
457 };
458 #endif
459 #endif
460
461
462 #ifdef VDEC3
463 typedef struct
464 {
465 MS_BOOL bTSP;
466 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
467 MS_U32 u32Used;
468 } BBU_STATE;
469
470 typedef struct
471 {
472 MS_BOOL bTSP;
473 MS_BOOL bUsedbyMVD;
474 MS_U32 u32Used;
475 } SLQ_STATE;
476 #endif
477
478 typedef struct
479 {
480 MS_BOOL _bVPUPowered;
481 MS_BOOL _bVPURsted;
482 MS_BOOL _bVPUSingleMode;
483 VPU_EX_DecModCfg _stVPUDecMode;
484 MS_U8 u8TaskCnt;
485 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
486 #ifdef VDEC3
487 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
488 #else
489 VPU_EX_Stream _stVPUStream[2];
490 #endif
491
492 VPU_HWInitFunc stHWInitFunc;
493
494 MS_BOOL bVpuExReloadFW;
495 MS_BOOL bVpuExLoadFWRlt;
496 MS_VIRT u32VPUSHMAddr; //PA
497 MS_BOOL bEnableVPUSecureMode;
498
499 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
500 MS_BOOL bEnableDymanicFBMode;
501 MS_PHY u32DynamicFBAddress;
502 MS_U32 u32DynamicFBSize;
503 #ifdef VDEC3
504 MS_VIRT u32FWCodeAddr;
505 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
506
507 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
508 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
509 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
510
511 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
512 #endif
513 MS_U8 u8ForceRst;
514 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
515 } VPU_Hal_CTX;
516
517 //global variables
518 VPU_Hal_CTX* pVPUHalContext = NULL;
519 VPU_Hal_CTX gVPUHalContext;
520 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
521 MS_BOOL bVPUMbxInitFlag = 0;
522 MS_U8 u8VPUMbxMsgClass = 0;
523 MBX_Msg VPUReeToTeeMbxMsg;
524 MBX_Msg VPUTeeToReeMbxMsg;
525
526 //-------------------------------------------------------------------------------------------------
527 // Debug Functions
528 //-------------------------------------------------------------------------------------------------
529
530
531 //-------------------------------------------------------------------------------------------------
532 // Local Functions
533 //-------------------------------------------------------------------------------------------------
534
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)535 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
536 {
537 #if HVD_ENABLE_RV_FEATURE
538 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
539 {
540 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
541 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
542 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
543
544 if (pVlcCfg->u32BinSize)
545 {
546 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
547
548 MS_U32 u32Start;
549 MS_U32 u32StartOffset;
550 MS_U8 u8MiuSel;
551
552 // Get MIU selection and offset from physical address = 0x30000000
553 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
554
555
556 if(u8MiuSel == E_CHIP_MIU_0)
557 cpyflag = E_SPIDMA_DEV_MIU0;
558 else if(u8MiuSel == E_CHIP_MIU_1)
559 cpyflag = E_SPIDMA_DEV_MIU1;
560 else if(u8MiuSel == E_CHIP_MIU_2)
561 cpyflag = E_SPIDMA_DEV_MIU2;
562
563 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
564 {
565 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
566 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
567
568 return FALSE;
569 }
570 }
571 else
572 {
573 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
574 return FALSE;
575 }
576 #else
577 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
578 return FALSE;
579 #endif
580 }
581 else
582 {
583 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
584 {
585 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
586 {
587 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
588 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
589
590 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
591 BDMA_Result bdmaRlt;
592 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
593
594 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
595 u32SrcAdd = pVlcCfg->u32BinAddr;
596 u32tabsize = pVlcCfg->u32BinSize;
597 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
598 MsOS_FlushMemory();
599 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
600
601 if (E_BDMA_OK != bdmaRlt)
602 {
603 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
604 }
605 #else
606 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
607 #endif
608 }
609 else
610 {
611 VPU_MSG_ERR
612 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
613 return FALSE;
614 }
615 }
616 else
617 {
618 #if VPU_ENABLE_EMBEDDED_FW_BINARY
619 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
620 MS_U8 *pu8HVD_VLC_Binary;
621
622 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
623
624 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
625 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
626 (MS_U32) sizeof(u8HVD_VLC_Binary));
627
628 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
629 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
630 #else
631 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
632 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
633 (MS_U32) sizeof(u8HVD_VLC_Binary));
634
635 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
636 #endif
637 #else
638 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
639 return FALSE;
640 #endif
641 }
642 }
643 #endif
644
645 return TRUE;
646 }
647
648 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)649 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
650 {
651 MS_U8 u8OffsetIdx = 0;
652 MS_U8 u8VSidBaseMask = 0xF0;
653 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
654
655 switch (eVSidBase)
656 {
657 case E_HAL_VPU_MAIN_STREAM_BASE:
658 {
659 u8OffsetIdx = 0;
660 break;
661 }
662 case E_HAL_VPU_SUB_STREAM_BASE:
663 {
664 u8OffsetIdx = 1;
665 break;
666 }
667 case E_HAL_VPU_MVC_STREAM_BASE:
668 {
669 u8OffsetIdx = 0;
670 break;
671 }
672 #ifdef VDEC3
673 case E_HAL_VPU_N_STREAM_BASE:
674 {
675 u8OffsetIdx = u32Id & 0x0F;
676 break;
677 }
678 #endif
679 default:
680 {
681 u8OffsetIdx = 0;
682 break;
683 }
684 }
685
686 /*
687 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
688 u32Id, eVSidBase, u8OffsetIdx);
689 */
690 return u8OffsetIdx;
691 }
692
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)693 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
694 {
695 return _VPU_EX_GetOffsetIdx(u32Id);
696 }
697
_VPU_EX_Context_Init(void)698 static void _VPU_EX_Context_Init(void)
699 {
700 #ifdef VDEC3
701 MS_U8 i;
702
703 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
704 {
705 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
706 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
707 }
708
709 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
710 {
711 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
712 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
713 }
714
715 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
716 {
717 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
718 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
719 }
720
721 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
722 {
723 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
724 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
725 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
726 }
727 #else
728 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
729 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
730 #endif
731 pVPUHalContext->bVpuExReloadFW = TRUE;
732 pVPUHalContext->u8ForceRst = 0;
733 }
734
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)735 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
736 {
737 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
738 MS_U8 u8OffsetIdx = 0;
739
740 if (NULL == pTaskInfo)
741 {
742 return eCmd;
743 }
744
745 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
746
747 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
748 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
749
750 #ifdef VDEC3
751 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
752 {
753 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
754 {
755 eCmd = E_NST_CMD_TASK_MVD_TSP;
756 }
757 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
758 {
759 eCmd = E_NST_CMD_TASK_MVD_SLQ;
760 }
761 }
762 #else
763 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
764 {
765 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
766 {
767 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
768 }
769 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
770 {
771 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
772 }
773 }
774 #endif
775 #ifdef VDEC3
776 #if SUPPORT_G2VP9
777 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
778 #else
779 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
780 #endif
781 {
782 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
783 {
784 eCmd = E_NST_CMD_TASK_HVD_TSP;
785 }
786 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
787 {
788 eCmd = E_NST_CMD_TASK_HVD_BBU;
789 }
790 }
791 #else
792 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
793 {
794 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
795 {
796 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
797 }
798 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
799 {
800 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
801 }
802 }
803 #endif
804
805 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
806 return eCmd;
807 }
808
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)809 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
810 {
811 if (!pTaskInfo)
812 {
813 VPU_MSG_ERR("null input\n");
814 return FALSE;
815 }
816
817 //Check if we need to init MVD HW
818 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
819 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
820 {
821 //Init HW
822 if (FALSE == HAL_VPU_EX_MVDInUsed())
823 {
824 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
825 {
826 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
827 return FALSE;
828 }
829 }
830 else
831 {
832 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
833 }
834 }
835
836 #if 0 // k6 is wbmvop, no need to open hvd clock for sub diu interface
837 //MVD use sub mvop
838 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
839 #ifdef VDEC3
840 (pTaskInfo->u8HalId == 1) )
841 #else
842 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
843 #endif
844 {
845 VPU_MSG_ERR("Force turn on HVD\n");
846 if(!HAL_VPU_EX_HVDInUsed())
847 {
848 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
849 {
850 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
851 {
852 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
853 return FALSE;
854 }
855 }
856 else
857 {
858 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
859 #ifdef CONFIG_MSTAR_CLKM
860 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
861 #else
862 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
863 #endif
864 }
865 }
866 else
867 {
868 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
869 }
870 }
871 #endif
872
873 //Check if we need to init HVD HW
874 #ifdef VDEC3
875 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
876 #else
877 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
878 #endif
879 {
880 if (!HAL_VPU_EX_MVDInUsed())
881 {
882 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
883 {
884 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
885 return FALSE;
886 }
887 }
888
889 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
890 {
891 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
892 return FALSE;
893 }
894 #if SUPPORT_MSVP9
895 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
896 {
897 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
898 }
899 #endif
900 }
901
902 #if SUPPORT_G2VP9 && defined(VDEC3)
903 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
904 {
905 if (!HAL_VPU_EX_MVDInUsed())
906 {
907 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
908 {
909 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
910 return FALSE;
911 }
912 }
913 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
914 {
915 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
916 return FALSE;
917 }
918 }
919 #endif
920
921 return TRUE;
922 }
923
_VPU_EX_InClock(MS_U32 u32type)924 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
925 {
926 switch (u32type)
927 {
928 case VPU_CLOCK_480MHZ:
929 return 480000000UL;
930 case VPU_CLOCK_432MHZ:
931 return 432000000UL;
932 case VPU_CLOCK_384MHZ:
933 return 384000000UL;
934 default:
935 return 480000000UL;
936 }
937 }
938
939
940 //#if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
941 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)942 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
943 {
944 //#ifndef MSOS_TYPE_LINUX_KERNEL
945 #if 1
946 MS_U8 ClassNum = 0;
947 MBX_Result result;
948
949 #if 0
950 if (bVPUMbxInitFlag == TRUE)
951 {
952 return TRUE;
953 }
954 #endif
955
956 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
957 {
958 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
959 return FALSE;
960 }
961 else
962 {
963 MApi_MBX_Enable(TRUE);
964 }
965
966 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
967
968 if (E_MBX_SUCCESS != result)
969 {
970 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
971 return FALSE;
972 }
973
974 result = MApi_MBX_RegisterMSG(ClassNum, 10);
975
976 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
977 {
978 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
979 return FALSE;
980 }
981 else
982 {
983 bVPUMbxInitFlag = TRUE;
984 u8VPUMbxMsgClass = ClassNum;
985 return TRUE;
986 }
987 #else
988 return FALSE;
989 #endif
990 }
991
992 //#ifdef MBX_2K
993 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)994 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
995 {
996 MBX_Result result;
997 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
998
999 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1000 {
1001 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1002 }
1003
1004 if (bVPUMbxInitFlag == FALSE)
1005 {
1006 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1007 }
1008
1009 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1010 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1011 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1012 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1013 VPUReeToTeeMbxMsg.u8Index = msg_type;
1014
1015 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1016 if (E_MBX_SUCCESS != result)
1017 {
1018 VPRINTF("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1019 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1020 }
1021
1022 // Receive Reply ACK from TEE side.
1023 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1024
1025 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1026
1027 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1028 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1029 {
1030 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1031 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1032 }
1033 else
1034 #else
1035 do
1036 {
1037 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1038 } while(E_MBX_SUCCESS != result);
1039 #endif
1040 {
1041 u8Index = VPUTeeToReeMbxMsg.u8Index;
1042 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1043
1044 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1045 {
1046 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1047 }
1048 }
1049
1050 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1051 }
1052 #endif
1053
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1054 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1055 {
1056 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1057 {
1058 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1059 {
1060 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1061 return FALSE;
1062 }
1063 else
1064 {
1065 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1066 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1067 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1068 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1069 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1070 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1071 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1072 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1073
1074 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1075
1076
1077 MS_U32 u32Start;
1078
1079 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1080 {
1081 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1082 pVPUHalContext->u32VPUSHMAddr = u32Start;
1083 }
1084 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1085 {
1086 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1087 pVPUHalContext->u32VPUSHMAddr = u32Start;
1088
1089 }
1090 else // == 0
1091 {
1092 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1093 }
1094 }
1095 }
1096 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1097 {
1098 MS_U32 u32Offset;
1099 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1100 {
1101 u32Offset = u32SHMAddr-u32MIU1Addr;
1102 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1103 }
1104 else
1105 {
1106 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1107 }
1108 }
1109
1110 return TRUE;
1111 }
1112
1113
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1114 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1115 {
1116 bVPUMbxInitFlag = TRUE;
1117 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1118 return TRUE;
1119 }
1120
HAL_VPU_EX_ForceSwRst(void)1121 void HAL_VPU_EX_ForceSwRst(void)
1122 {
1123 pVPUHalContext->u8ForceRst = 1;
1124 }
1125
1126 //#endif
1127
HAL_VPU_EX_GetFWReload(void)1128 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1129 {
1130 return pVPUHalContext->bVpuExReloadFW;
1131 }
1132
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1133 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1134 {
1135 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1136 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1137 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1138 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1139 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1140 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1141 )
1142 {
1143 return FALSE;
1144 }
1145 else
1146 {
1147 return TRUE;
1148 }
1149 }
1150
_VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg * pFWCodeCfg)1151 static MS_BOOL _VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg *pFWCodeCfg)
1152 {
1153
1154
1155 #if 1 // bypass mode for debug
1156
1157 // allow non-secure read access
1158 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1159 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1160
1161 // allow non-secure write access
1162 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1163 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1164
1165 #else
1166 MS_PHY u32fwPAStart = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1167 MS_PHY u32fwPAEnd = u32fwPAStart + pFWCodeCfg->u32DstSize;
1168 MS_PHY u32WriteReplaceAddr = u32fwPAStart + CTL_INFO_ADDR;
1169
1170 // 128 bits align
1171 if((u32fwPAStart & 0xF) || (u32fwPAEnd & 0xF) || (u32WriteReplaceAddr & 0xF))
1172 {
1173 VPU_MSG_ERR("[Error] address need 128 bits align\n");
1174 return FALSE;
1175 }
1176
1177 u32fwPAStart >>= 4;
1178 u32fwPAEnd >>= 4;
1179 u32WriteReplaceAddr >>= 4;
1180
1181 // configure 1st secure range start address
1182 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1183 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1184 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1185
1186 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1187 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1188 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1189
1190 // configure 1st secure range end address
1191 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1192 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1193 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1194
1195 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1196 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1197 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1198
1199 // configure replaced address
1200 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1201 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1202 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1203
1204 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1205 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1206 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1207
1208 // Enable limit write access
1209 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1210
1211 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1212
1213 // Enable 1st limit range
1214 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1215
1216 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1217
1218 // Enable One-way bit
1219 _VPU_WriteWordMask(REG_ONEWAY_B16, ONEWAY_B16, ONEWAY_B16);
1220 _VPU_WriteWordMask(REG_LOCK_ONEWAY_B16, LOCK_ONEWAY_B16, LOCK_ONEWAY_B16);
1221
1222 #endif
1223
1224 return TRUE;
1225 }
1226
1227
1228
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1229 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1230 {
1231 MS_PHY u32fwPA = NULL; //physical address
1232 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_480MHZ;
1233
1234 if (TRUE == HAL_VPU_EX_IsPowered())
1235 {
1236 VPU_MSG_DBG("IsPowered\n");
1237 return TRUE;
1238 }
1239 else
1240 {
1241 //VPU hold
1242 HAL_VPU_EX_SwRst(FALSE);
1243
1244 //VPU clock on
1245 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1246
1247 if (VPU_I_R_ON_MIU0)
1248 VPUInitParams.u8MiuSel = 0;
1249 else if (VPU_I_R_ON_MIU1)
1250 VPUInitParams.u8MiuSel = 1;
1251 // else if (VPU_I_R_ON_MIU2)
1252 // VPUInitParams.u8MiuSel = 2;
1253
1254 HAL_VPU_EX_Init(&VPUInitParams);
1255 }
1256
1257 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1258 VPU_EX_TaskInfo *pTaskInfo = NULL;
1259 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1260
1261 if (pInitPara)
1262 {
1263 pFWCodeCfg = pInitPara->pFWCodeCfg;
1264 pTaskInfo = pInitPara->pTaskInfo;
1265 pVlcCfg = pInitPara->pVLCCfg;
1266
1267 if(_VPU_EX_InitAddressLimiter(pFWCodeCfg) == FALSE)
1268 {
1269 VPU_MSG_ERR("(%d) InitAddressLimiter fail\n", __LINE__);
1270 return FALSE;
1271 }
1272 }
1273 else
1274 {
1275 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1276 return FALSE;
1277 }
1278
1279 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1280 //#ifdef MBX_2K
1281 #if 1
1282 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1283 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1284 {
1285 SYS_TEEINFO teemode;
1286 MDrv_SYS_ReadKernelCmdLine();
1287 MDrv_SYS_GetTEEInfo(&teemode);
1288 VPRINTF("[VDEC][TEE/OPTEE]%s,TEE_type=%d\n",__FUNCTION__,teemode.OsType);
1289 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1290 {
1291 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1292
1293 if (FALSE == HAL_VPU_EX_GetFWReload())
1294 {
1295 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1296 {
1297 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1298 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1299 {
1300 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1301 return FALSE;
1302 }
1303 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1304 }
1305 else
1306 {
1307 //Check f/w prefix "VDEC30"
1308 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1309 {
1310 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1311 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1312 {
1313 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1314 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1315 return FALSE;
1316 }
1317 }
1318 else
1319 {
1320 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1321 }
1322 }
1323 }
1324 else
1325 {
1326 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1327 {
1328 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1329 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1330 return FALSE;
1331 }
1332 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1333 }
1334 }
1335 }
1336 else
1337 #endif
1338 #endif
1339 {
1340 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1341
1342 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1343 {
1344 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1345 return FALSE;
1346 }
1347 }
1348
1349 if (pVlcCfg)
1350 {
1351 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1352 {
1353 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1354 return FALSE;
1355 }
1356 }
1357
1358 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1359 {
1360 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1361 return FALSE;
1362 }
1363
1364 //Init HW
1365 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1366 {
1367 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1368 //_MVD_INIT_FAIL_RET();
1369 return FALSE;
1370 }
1371 else
1372 {
1373 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1374 }
1375
1376 //set vpu clock to FW
1377 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1378 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1379
1380
1381 #if (VPU_ENABLE_IQMEM)
1382 ctl_ptr->bIQmemEnableIfSupport = TRUE;
1383 #endif
1384
1385 ctl_ptr->statue = CTL_STU_NONE;
1386 //notify controller the interface version of VPU driver.
1387 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1388 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1389 MsOS_FlushMemory();
1390 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1391
1392 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1393 if (TRUE == HAL_VPU_EX_IsRsted())
1394 {
1395 VPU_MSG_DBG("VPU_IsRsted\n");
1396 return TRUE;
1397 }
1398 else
1399 {
1400 HAL_VPU_EX_SwRstRelse();
1401 }
1402
1403 return TRUE;
1404 }
1405
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1406 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1407 {
1408 MS_BOOL bRet = FALSE;
1409
1410 #if defined(VDEC3)
1411 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1412 #else
1413 MS_BOOL isEVD = FALSE ;
1414 #endif
1415 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1416 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1417 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1418
1419 if (FALSE == HAL_VPU_EX_MVDInUsed())
1420 {
1421 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1422 }
1423
1424 if (TRUE == isHVD)
1425 {
1426 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1427 }
1428
1429 #if defined(VDEC3)
1430 if (TRUE == isEVD)
1431 {
1432 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1433 }
1434 #endif
1435
1436 #if SUPPORT_G2VP9 && defined(VDEC3)
1437 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1438 {
1439 bRet = HAL_VP9_EX_DeinitHW();
1440 }
1441 #endif
1442 return bRet;
1443 }
1444
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1445 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1446 {
1447 HAL_VPU_EX_SwRst(TRUE);
1448 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1449 HAL_VPU_EX_DeInit();
1450
1451 return TRUE;
1452 }
1453
_VPU_EX_GetActiveCodecCnt(void)1454 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1455 {
1456 MS_U32 i;
1457 MS_U8 u8ActiveCnt = 0;
1458 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1459 {
1460 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1461 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1462 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1463 {
1464 u8ActiveCnt++;
1465 }
1466 }
1467 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1468 {
1469 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1470 }
1471 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1472 return u8ActiveCnt;
1473 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1474 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1475 {
1476 if (TRUE)
1477 {
1478 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1479 }
1480 else
1481 {
1482 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1483 }
1484 }
1485
_VPU_EX_ClockSpeed(MS_U32 u32type)1486 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1487 {
1488 switch (u32type)
1489 {
1490 case VPU_CLOCK_480MHZ:
1491 case VPU_CLOCK_432MHZ:
1492 case VPU_CLOCK_384MHZ:
1493 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1494 break;
1495 default:
1496 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_480MHZ, TOP_CKG_VPU_CLK_MASK);
1497 break;
1498 }
1499 }
1500 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1501 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1502 {
1503 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1504 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1505 {
1506 return TRUE;
1507 }
1508 return FALSE;
1509 }
1510 #endif
1511
1512
1513 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1514 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1515 {
1516 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1517 {
1518 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1519 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1520 ms_VDECDecompressDeInit();
1521 return TRUE;
1522 }
1523 else
1524 {
1525 return FALSE;
1526 }
1527 }
1528 #endif
1529
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1530 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1531 {
1532 MS_BOOL bRet = TRUE;
1533 pVPUHalContext->_bVPUSingleMode = bEnable;
1534 return bRet;
1535 }
1536
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1537 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1538 {
1539 MS_BOOL bRet = TRUE;
1540 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1541 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1542 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1543
1544 return bRet;
1545 }
1546
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1547 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1548 {
1549 MS_BOOL bRet = TRUE;
1550 MS_U8 i=0;
1551 if (pstCfg != NULL)
1552 {
1553 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1554 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1555 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1556 {
1557 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1558 }
1559 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1560 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1561 }
1562 else
1563 {
1564 bRet = FALSE;
1565 }
1566 return bRet;
1567 }
1568
1569 //static MS_BOOL bVpuExReloadFW = TRUE;
1570 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1571 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1572 {
1573 pVPUHalContext->bVpuExReloadFW = bReload;
1574 //VPRINTF("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1575 return TRUE;
1576 }
1577
1578
1579 //-------------------------------------------------------------------------------------------------
1580 // Global Functions
1581 //-------------------------------------------------------------------------------------------------
1582 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1583 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1584 {
1585 #if HVD_ENABLE_RV_FEATURE
1586 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1587 {
1588 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1589 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1590 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1591
1592 if (pVlcCfg->u32BinSize)
1593 {
1594 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1595
1596 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1597 {
1598 cpyflag = E_SPIDMA_DEV_MIU1;
1599 }
1600 else
1601 {
1602 cpyflag = E_SPIDMA_DEV_MIU0;
1603 }
1604
1605 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1606 {
1607 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1608 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1609
1610 return FALSE;
1611 }
1612 }
1613 else
1614 {
1615 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1616 return FALSE;
1617 }
1618 #else
1619 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1620 return FALSE;
1621 #endif
1622 }
1623 else
1624 {
1625 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1626 {
1627 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1628 {
1629 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1630 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1631
1632 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1633 BDMA_Result bdmaRlt;
1634
1635 MsOS_FlushMemory();
1636 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1637
1638 if (E_BDMA_OK != bdmaRlt)
1639 {
1640 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1641 }
1642 #else
1643 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1644 #endif
1645 }
1646 else
1647 {
1648 VPU_MSG_ERR
1649 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1650 return FALSE;
1651 }
1652 }
1653 else
1654 {
1655 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1656 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1657 MS_U8 *pu8HVD_VLC_Binary;
1658
1659 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1660
1661 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1662 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1663 (MS_U32) sizeof(u8HVD_VLC_Binary));
1664
1665 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1666 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1667 #else
1668 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1669 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1670 (MS_U32) sizeof(u8HVD_VLC_Binary));
1671
1672 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1673 #endif
1674 #else
1675 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1676 return FALSE;
1677 #endif
1678 }
1679 }
1680 #endif
1681
1682 return TRUE;
1683 }
1684 #endif
1685
1686
1687 #if (VPU_ENABLE_IQMEM)
HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara * pInitPara)1688 MS_BOOL HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara *pInitPara)
1689 {
1690
1691 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1692 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1693
1694
1695 MS_U32 u32Timeout = 20000;
1696
1697 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_NONE)
1698 {
1699
1700 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1701
1702
1703 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_LOADING;
1704
1705 while (u32Timeout)
1706 {
1707
1708 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_LOADED)
1709 {
1710 break;
1711 }
1712 u32Timeout--;
1713 MsOS_DelayTaskUs(1000);
1714 }
1715
1716 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1717
1718
1719 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_FINISH;
1720
1721 if (u32Timeout==0)
1722 {
1723 HVD_EX_MSG_ERR("Wait E_CTL_IQMEM_INIT_FINISH timeout !!\n");
1724 return FALSE;
1725 }
1726
1727 }
1728 return TRUE;
1729 }
1730
1731 #endif
1732
1733
1734
1735 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1736 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1737 #else
1738 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1739 #endif
1740 {
1741 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1742 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1743 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1744 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1745 MS_U32 u32Arg = 0xFFFFFFFF;
1746 MS_U32 u32Timeout = 0;
1747 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1748 MS_U32 u32CmdArg = 0;
1749 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1750 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1751
1752 _HAL_VPU_Entry();
1753 //Check FW buffer size
1754 if (1 == u8Offset)
1755 {
1756 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1757 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1758
1759 if (u32CurFWBuffSize < u32MinFWBuffSize)
1760 {
1761 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1762 _HAL_VPU_Release();
1763 return FALSE;
1764 }
1765 }
1766
1767 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1768 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1769 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1770 {
1771 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1772 }
1773 #ifdef VDEC3
1774 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1775 #endif
1776
1777 if (0 == pVPUHalContext->u8TaskCnt)
1778 {
1779 //No task is created, need to load f/w, etc.
1780 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1781
1782 if (!_VPU_EX_InitAll(pInitPara))
1783 {
1784 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1785 _HAL_VPU_Release();
1786 return FALSE;
1787 }
1788
1789 //Check if controller finish initialization: clear mailbox, etc.
1790 //Need to check it before sending any controller commands!
1791 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1792 while (CTL_STU_NONE == ctl_ptr->statue)
1793 {
1794 if (HVD_GetSysTime_ms() > u32Timeout)
1795 {
1796 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1797 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1798 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1799 MS_U32 t=0;
1800 for (t=0; t<30; t++)
1801 {
1802 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1803 }
1804 _HAL_VPU_Release();
1805 return FALSE;
1806 }
1807
1808 MsOS_ReadMemory();
1809 }
1810
1811 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1812 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1813
1814 }
1815 else
1816 {
1817 if (pVPUHalContext->_bVPUSingleMode)
1818 {
1819 //Show error message
1820 VPRINTF("This task will use dram instead of sram!!!\n");
1821 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1822 }
1823
1824 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1825 {
1826 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1827 _HAL_VPU_Release();
1828 return FALSE;
1829 }
1830 if (pInitPara->pVLCCfg)
1831 {
1832 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1833 {
1834 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1835 _HAL_VPU_Release();
1836 return FALSE;
1837 }
1838 }
1839 }
1840
1841
1842 #if (VPU_ENABLE_IQMEM)
1843
1844 if( ctl_ptr->bIsIQMEMSupport)
1845 {
1846
1847 HAL_VPU_EX_IQMem_Init(pInitPara);
1848 }
1849 else{
1850 VPU_MSG_ERR("not support IQMEM\n");
1851 }
1852
1853 #endif
1854
1855
1856 #ifdef VDEC3
1857 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1858 {
1859 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1860
1861 memset(pTemp4,0,sizeof(VDEC_VBBU));
1862
1863 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1864
1865 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1866
1867 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1868
1869 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1870
1871 memset(pTemp2,0,sizeof(CMD_QUEUE));
1872
1873 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1874
1875 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1876
1877 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1878
1879 memset(pTemp3,0,0x2000);
1880
1881 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1882
1883 memset((void*)pVersion,0,0x8);
1884
1885 *pVersion = 1; //0:diu, 1:wb
1886 }
1887
1888 #endif
1889
1890 #if 1 // For TEE
1891 #ifdef VDEC3
1892 #if SUPPORT_G2VP9
1893 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1894 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1895 #else
1896 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1897 #endif
1898 #else
1899 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1900 #endif
1901 {
1902 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1903
1904 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1905 {
1906 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1907 }
1908 else
1909 {
1910 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1911 }
1912
1913 MsOS_FlushMemory();
1914 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1915
1916 ///VPRINTF("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1917 ///VPRINTF("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1918 }
1919 #endif
1920
1921 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1922 {
1923 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1924 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1925
1926 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1927
1928 MsOS_FlushMemory();
1929 }
1930
1931 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1932 {
1933 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1934 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1935 {
1936 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1937 }
1938 }
1939
1940 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1941 {
1942 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1943 //arg=1 to get better performance for single task
1944 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1945 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1946 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1947 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1948 {
1949 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1950 }
1951 }
1952 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1953 {
1954 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1955 {
1956 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1957 {
1958 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1959 u32CmdArg = CTL_MODE_3DTV;
1960 break;
1961 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1962 u32CmdArg = CTL_MODE_3DTV_PROG;
1963 break;
1964 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1965 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1966 break;
1967 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1968 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1969 break;
1970 default:
1971 u32CmdArg = CTL_MODE_3DTV;
1972 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1973 break;
1974 }
1975 }
1976 else
1977 {
1978 u32CmdArg = CTL_MODE_3DWMV;
1979 }
1980 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1981 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1982 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1983 {
1984 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1985 }
1986 }
1987 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1988 {
1989 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1990 {
1991 u32CmdArg = CTL_MODE_ONE_STC;
1992 }
1993 else
1994 {
1995 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1996 }
1997 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1998 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1999 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
2000 {
2001 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
2002 }
2003 }
2004
2005 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
2006 #if defined(SUPPORT_NEW_MEM_LAYOUT)
2007 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2008 #ifdef VDEC3
2009 {
2010 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2011 }
2012 #else
2013 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2014 #endif
2015
2016 #ifdef VDEC3
2017 #if SUPPORT_G2VP9
2018 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2019 #else
2020 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2021 #endif
2022 {
2023 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2024 }
2025 #else
2026 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2027 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
2028 #endif
2029 else
2030 {
2031 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2032 _HAL_VPU_Release();
2033 return FALSE;
2034 }
2035 #else
2036 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
2037 #endif
2038
2039 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
2040 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
2041
2042 MsOS_ReadMemory();
2043 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2044 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2045
2046 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2047 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2048 {
2049 if (HVD_GetSysTime_ms() > u32Timeout)
2050 {
2051 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2052 MS_U32 t=0;
2053 for (t=0; t<30; t++)
2054 {
2055 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
2056 }
2057 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2058 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2059 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2060 _HAL_VPU_Release();
2061 return FALSE;
2062 //#endif
2063 }
2064
2065 MsOS_ReadMemory();
2066 }
2067
2068 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2069 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2070
2071 #ifdef VDEC3
2072 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2073 #else
2074 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2075 #endif
2076 {
2077 HAL_HVD_EX_SetNalTblAddr(u32Id);
2078 }
2079
2080 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2081 {
2082 eDecType = E_VPU_EX_DECODER_MVD;
2083 }
2084 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2085 {
2086 eDecType = E_VPU_EX_DECODER_HVD;
2087 }
2088 #ifdef VDEC3
2089 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2090 {
2091 eDecType = E_VPU_EX_DECODER_EVD;
2092 }
2093 #if SUPPORT_G2VP9
2094 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2095 {
2096 eDecType = E_VPU_EX_DECODER_G2VP9;
2097 }
2098 #endif
2099 #endif
2100 else
2101 {
2102 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2103 _HAL_VPU_Release();
2104 return FALSE;
2105 }
2106
2107 #ifdef VDEC3
2108 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
2109 {
2110 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2111 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2112 }
2113 #endif
2114
2115 if (pTaskInfo->eDecType != eDecType)
2116 {
2117 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2118 pTaskInfo->eDecType, eDecType);
2119 }
2120 goto _SAVE_DEC_TYPE;
2121
2122 _SAVE_DEC_TYPE:
2123 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2124 {
2125 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
2126 }
2127 else
2128 {
2129 VPU_MSG_ERR("Cannot save eDecType!!\n");
2130 }
2131
2132 (pVPUHalContext->u8TaskCnt)++;
2133 _HAL_VPU_Release();
2134 return TRUE;
2135 }
2136
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2137 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2138 {
2139 HVD_Return eRet;
2140 #ifdef VDEC3
2141 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2142 #else
2143 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2144 #endif
2145 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2146 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2147
2148 _HAL_VPU_Entry();
2149 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2150
2151 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2152 if(eRet != E_HVD_RETURN_SUCCESS)
2153 {
2154 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2155 }
2156
2157 {
2158 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2159 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2160 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2161
2162 MsOS_ReadMemory();
2163
2164 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2165 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2166
2167 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2168 {
2169 if (HVD_GetSysTime_ms() > u32Timeout)
2170 {
2171 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2172 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2173 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2174
2175 if(pVPUHalContext->u8TaskCnt == 1)
2176 {
2177 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2178 break;
2179 }
2180 else if(pVPUHalContext->u8TaskCnt == 2)
2181 {
2182 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2183 break;
2184 }
2185 else
2186 {
2187 VPU_MSG_ERR("Task number is not correct\n");
2188 _HAL_VPU_Release();
2189 return FALSE;
2190 }
2191 }
2192
2193 MsOS_ReadMemory();
2194 }
2195
2196 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2197 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2198 }
2199 #if SUPPORT_EVD
2200 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2201 {
2202 HAL_EVD_EX_ClearTSPInput(u32Id);
2203 }
2204 #endif
2205
2206 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2207 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2208 {
2209 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2210 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2211 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2212 }
2213
2214 if (pVPUHalContext->u8TaskCnt)
2215 {
2216 (pVPUHalContext->u8TaskCnt)--;
2217 }
2218 else
2219 {
2220 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2221 }
2222
2223 if (0 == pVPUHalContext->u8TaskCnt)
2224 {
2225 int i;
2226 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2227 _VPU_EX_DeinitAll(pInitPara);
2228 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2229 pVPUHalContext->u32VPUSHMAddr = 0;
2230
2231 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2232 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2233 }
2234 else
2235 {
2236 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2237 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2238 }
2239
2240 _HAL_VPU_Release();
2241 return TRUE;
2242 }
2243
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2244 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2245 {
2246 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2247 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2248 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2249 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2250 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2251 #endif
2252
2253 if (FALSE == HAL_VPU_EX_GetFWReload())
2254 {
2255 //VPRINTF("%s bFWReload FALSE!!!\n", __FUNCTION__);
2256 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2257 {
2258 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2259 }
2260 else
2261 {
2262 //Check f/w prefix "VDEC30"
2263 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2264 {
2265 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2266 }
2267 else
2268 {
2269 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2270 return TRUE;
2271 }
2272 }
2273 }
2274
2275 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2276 {
2277 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2278 if (u32Size != 0)
2279 {
2280 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2281
2282
2283 MS_U32 u32Start;
2284 MS_U32 u32StartOffset;
2285 MS_U8 u8MiuSel;
2286
2287 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2288
2289
2290 if(u8MiuSel == E_CHIP_MIU_0)
2291 cpyflag = E_SPIDMA_DEV_MIU0;
2292 else if(u8MiuSel == E_CHIP_MIU_1)
2293 cpyflag = E_SPIDMA_DEV_MIU1;
2294 else if(u8MiuSel == E_CHIP_MIU_2)
2295 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2296
2297 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2298 {
2299 goto _load_code_fail;
2300 }
2301 }
2302 else
2303 {
2304 goto _load_code_fail;
2305 }
2306 #else
2307 goto _load_code_fail;
2308 #endif
2309 }
2310 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2311 {
2312 if (u32BinAddr != 0 && u32Size != 0)
2313 {
2314 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2315 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2316 {
2317 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2318 {
2319 VPU_MSG_INFO("Decompress ok!!!\n");
2320 }
2321 else
2322 {
2323 VPU_MSG_INFO("Decompress fail!!!\n");
2324 }
2325 }
2326 else
2327 #endif
2328 {
2329 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2330 }
2331 }
2332 else
2333 {
2334 goto _load_code_fail;
2335 }
2336 }
2337 else
2338 {
2339 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2340 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2341 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2342 (MS_U32) sizeof(u8HVD_FW_Binary));
2343
2344 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2345 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2346 {
2347 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2348 {
2349 VPU_MSG_INFO("Decompress ok!!!\n");
2350 }
2351 else
2352 {
2353 VPU_MSG_INFO("Decompress fail!!!\n");
2354 }
2355 }
2356 else
2357 #endif
2358 {
2359 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2360 }
2361 #else
2362 goto _load_code_fail;
2363 #endif
2364 }
2365
2366 MAsm_CPU_Sync();
2367 MsOS_FlushMemory();
2368
2369 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2370 {
2371 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2372 goto _load_code_fail;
2373 }
2374
2375 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2376 return TRUE;
2377
2378 _load_code_fail:
2379 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2380 return FALSE;
2381 }
2382
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2383 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2384 {
2385 u32VPURegOSBase = u32RegBase;
2386 }
2387
HAL_VPU_EX_Init_Share_Mem(void)2388 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2389 {
2390 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2391
2392 MS_U32 u32ShmId;
2393 MS_VIRT u32Addr;
2394 MS_U32 u32BufSize;
2395
2396
2397 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2398 sizeof(VPU_Hal_CTX),
2399 &u32ShmId,
2400 &u32Addr,
2401 &u32BufSize,
2402 MSOS_SHM_QUERY))
2403 {
2404 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2405 sizeof(VPU_Hal_CTX),
2406 &u32ShmId,
2407 &u32Addr,
2408 &u32BufSize,
2409 MSOS_SHM_CREATE))
2410 {
2411 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2412 if(pVPUHalContext == NULL)
2413 {
2414 pVPUHalContext = &gVPUHalContext;
2415 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2416 _VPU_EX_Context_Init();
2417 VPRINTF("[%s]Global structure init Success!!!\n",__FUNCTION__);
2418 }
2419 else
2420 {
2421 VPRINTF("[%s]Global structure exists!!!\n",__FUNCTION__);
2422 }
2423 //return FALSE;
2424 }
2425 else
2426 {
2427 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2428 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2429 _VPU_EX_Context_Init();
2430 }
2431 }
2432 else
2433 {
2434 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2435 }
2436 #else
2437 if(pVPUHalContext == NULL)
2438 {
2439 pVPUHalContext = &gVPUHalContext;
2440 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2441 _VPU_EX_Context_Init();
2442 }
2443 #endif
2444
2445 return TRUE;
2446
2447 }
2448
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2449 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2450 {
2451 MS_U32 i = 0;
2452
2453 _HAL_VPU_MutexCreate();
2454
2455 _HAL_VPU_Entry();
2456
2457 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2458 {
2459 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2460 {
2461 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2462 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2463 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2464 _HAL_VPU_Release();
2465 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2466 }
2467 }
2468 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2469 {
2470 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2471 {
2472 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2473 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2474 {
2475 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2476 _HAL_VPU_Release();
2477 return pVPUHalContext->_stVPUStream[i].eStreamId;
2478 }
2479 }
2480 }
2481 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2482 {
2483 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2484 {
2485 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2486 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2487 {
2488 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2489 _HAL_VPU_Release();
2490 return pVPUHalContext->_stVPUStream[i].eStreamId;
2491 }
2492 }
2493 }
2494 #ifdef VDEC3
2495 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2496 {
2497 #if 1 // bound FW task to main/sub stream
2498 i = eStreamType - E_HAL_VPU_N_STREAM;
2499 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2500 {
2501 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2502 _HAL_VPU_Release();
2503 return pVPUHalContext->_stVPUStream[i].eStreamId;
2504 }
2505 #else // dynamic select FW task id
2506 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2507 {
2508 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2509 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2510 {
2511 return pVPUHalContext->_stVPUStream[i].eStreamId;
2512 }
2513 }
2514 #endif
2515 }
2516 #endif
2517
2518 _HAL_VPU_Release();
2519
2520 return E_HAL_VPU_STREAM_NONE;
2521 }
2522
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2523 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2524 {
2525 _HAL_VPU_Entry();
2526
2527 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2528 {
2529 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2530 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2531 }
2532 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2533 {
2534 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2535 }
2536
2537 _HAL_VPU_Release();
2538
2539 return TRUE;
2540 }
2541
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2542 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2543 {
2544 MS_U8 u8Idx = 0;
2545
2546 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2547
2548 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2549 {
2550 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2551 {
2552 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2553 return 0;
2554 }
2555 }
2556 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2557 {
2558 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2559 {
2560 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2561 return 1;
2562 }
2563 }
2564
2565 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2566 {
2567 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2568 break;
2569 }
2570
2571 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2572 {
2573 VPU_MSG_ERR("all vpu free streams are occupied \n");
2574 return 0xFF;
2575 }
2576
2577 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2578 return u8Idx;
2579 }
2580
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2581 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2582 {
2583 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2584
2585 // enable module
2586 _VPU_EX_ClockInv(InitParams->bClockInv);
2587 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2588 HAL_VPU_EX_PowerCtrl(TRUE);
2589
2590 #ifdef CONFIG_MSTAR_CLKM
2591 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2592 #endif
2593
2594 #ifdef CONFIG_MSTAR_SRAMPD
2595 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2596 HVD_Delay_ms(1);
2597 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2598 HVD_Delay_ms(1);
2599 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2600 HVD_Delay_ms(1);
2601 #endif
2602 #if 1 //Create VPU's own mutex
2603 //_HAL_VPU_MutexCreate();
2604 #else
2605 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2606 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2607 #endif
2608
2609 return TRUE;
2610 }
2611
HAL_VPU_EX_DeInit(void)2612 MS_BOOL HAL_VPU_EX_DeInit(void)
2613 {
2614 if (0 != _VPU_EX_GetActiveCodecCnt())
2615 {
2616 VPU_MSG_DBG("do nothing since codec is active.\n");
2617 return TRUE;
2618 }
2619
2620 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2621
2622 #ifdef CONFIG_MSTAR_CLKM
2623 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2624 #else
2625 HAL_VPU_EX_PowerCtrl(FALSE);
2626 #endif
2627
2628 #ifdef CONFIG_MSTAR_SRAMPD
2629 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2630 HVD_Delay_ms(1);
2631 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2632 HVD_Delay_ms(1);
2633 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2634 HVD_Delay_ms(1);
2635 #endif
2636
2637 HAL_VPU_EX_SwRelseMAU();
2638 //_HAL_VPU_MutexDelete();
2639
2640 return TRUE;
2641 }
2642
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2643 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2644 {
2645 if (bEnable)
2646 {
2647 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2648 _VPU_WriteWordMask(REG_TOP_VPU, VPU_ICG_EN, VPU_ICG_EN);
2649 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2650 pVPUHalContext->_bVPUPowered = TRUE;
2651 }
2652 else
2653 {
2654 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2655 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2656 pVPUHalContext->_bVPUPowered = FALSE;
2657 }
2658 }
2659
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2660 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2661 {
2662 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2663 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2664 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2665 VPU_EX_TimerDelayMS(1);
2666 }
2667
2668 ///-----------------------------------------------------------------------------
2669 /// config AVCH264 CPU
2670 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2671 /// @param u8dlend_en \b IN: endian
2672 /// - 1, little endian
2673 /// - 0, big endian
2674 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2675 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2676 {
2677 MS_BOOL bRet = TRUE;
2678 MS_U32 u32Offset = 0;
2679 MS_U16 tempreg = 0;
2680 MS_U8 u8MiuSel;
2681 //MS_U32 u32TmpStartOffset;
2682
2683 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2684
2685 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2686 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2687 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2688 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2689 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2690 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2691 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2692 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2693 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2694 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2695
2696 #if (VPU_ENABLE_IQMEM)
2697 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2698 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2699 #endif
2700
2701 #if (VPU_FORCE_MIU_MODE)
2702 // Data sram base Unit: byte address
2703 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2704 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2705 // Instruction sram base Unit: byte address
2706 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2707 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2708
2709 #ifndef HAL_FEATURE_MAU
2710 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2711 #endif
2712 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2713
2714 //use force miu mode
2715 if(u8MiuSel == E_CHIP_MIU_0)
2716 {
2717 #ifdef HAL_FEATURE_MAU
2718 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2719 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2720 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2721 #else
2722 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2723 #endif
2724 }
2725 else if(u8MiuSel == E_CHIP_MIU_1)
2726 {
2727 #ifdef HAL_FEATURE_MAU
2728 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2729 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2730 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2731 #else
2732 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2733 #endif
2734 }
2735 else //miu 2
2736 {
2737 #ifdef HAL_FEATURE_MAU
2738 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2739 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2740 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2741 #else
2742 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2743 #endif
2744 }
2745 #else
2746 ///TODO:
2747 #endif
2748
2749
2750 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2751 tempreg |= VPU_REG_IO2_EN;
2752 tempreg |= VPU_REG_QMEM_SPACE_EN;
2753 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2754
2755 return bRet;
2756 }
2757
2758 ///-----------------------------------------------------------------------------
2759 /// Set IQMem data access mode or instruction fetch mode
2760 /// @param u8dlend_en \b IN: endian
2761 /// - 1, switch to data access mode
2762 /// - 0, switch to instruction fetch mode
2763 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2764 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2765 {
2766
2767 if(bEnable){
2768
2769 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2770 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)|0x20);
2771
2772 }
2773 else{
2774
2775 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& (~0x10));
2776 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)& (~0x20));
2777 }
2778 }
2779
2780 ///-----------------------------------------------------------------------------
2781 /// H.264 SW reset
2782 /// @return TRUE or FALSE
2783 /// - TRUE, Success
2784 /// - FALSE, Failed
2785 ///-----------------------------------------------------------------------------
2786
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2787 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2788 {
2789 MS_U16 tempreg = 0, tempreg1 = 0;
2790 MS_U16 idle_cnt;
2791 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2792 tempreg |= VPU_REG_CPU_STALL_EN;
2793 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2794
2795 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2796 // 0xf means VPU is not stalled
2797 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2798 pVPUHalContext->u8ForceRst = 0;
2799 // write R2 RIU registers to select DCU/ICU debug data
2800 // Writing these registers here provides enough time for them to
2801 // take effect.
2802 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2803 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2804 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2805 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2806
2807 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2808 // This step is important because in the next step we want to make
2809 // sure "DCU is not replaying when R2 is stalled".
2810 idle_cnt = 100;
2811 do
2812 {
2813 if (--idle_cnt == 0)
2814 {
2815 VPRINTF("VPU_REG_CPU_STALL_EN is not set\n");
2816 break;
2817 }
2818 MsOS_DelayTask(1);
2819 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2820 // check CPU status: DCU should NOT be replaying
2821 // If R2 has been stalled, we can guarantee that if we found DCU is
2822 // NOT replaying, it will NOT replay later even CPU is going to issue
2823 // a load/store instruction.
2824 idle_cnt = 100;
2825 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2826 {
2827 if (--idle_cnt == 0)
2828 {
2829 VPRINTF("DCU is replaying\n");
2830 break;
2831 }
2832 MsOS_DelayTask(1);
2833 }
2834 // wait 1ms to prevent race condition between (1) DCU is not
2835 // replaying, and (2) BIU start to doing new job or ICU start to
2836 // fetch new instruction
2837 MsOS_DelayTask(1);
2838
2839 // check BIU should be empty
2840 idle_cnt = 100;
2841 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2842 {
2843 if (--idle_cnt == 0)
2844 {
2845 VPRINTF("BIU DCU idle time out~~~~~\n");
2846 break;
2847 }
2848 MsOS_DelayTask(1);
2849 }
2850
2851 // check CPU is not requesting ICU
2852 idle_cnt = 100;
2853 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2854 {
2855 if (--idle_cnt == 0)
2856 {
2857 VPRINTF("CPU keeps requesting ICU\n");
2858 break;
2859 }
2860 MsOS_DelayTask(1);
2861 }
2862
2863 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2864 // (2) ISB start to fetch
2865 MsOS_DelayTask(1);
2866
2867 // check ISB should be idle
2868 idle_cnt = 100;
2869 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2870 {
2871 if (--idle_cnt == 0)
2872 {
2873 VPRINTF("ISB is busy\n");
2874 break;
2875 }
2876 MsOS_DelayTask(1);
2877 }
2878 }
2879 #ifdef HAL_FEATURE_MAU
2880 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2881 if (bCheckMauIdle)
2882 {
2883 MS_U32 mau_idle_cnt = 100;// ms
2884 while (mau_idle_cnt)
2885 {
2886 if (TRUE == _VPU_EX_MAU_IDLE())
2887 {
2888 break;
2889 }
2890 mau_idle_cnt--;
2891 MsOS_DelayTask(1);
2892 }
2893
2894 if (mau_idle_cnt == 0)
2895 {
2896 VPRINTF("MAU idle time out~~~~~\n");
2897 }
2898 }
2899 #endif
2900
2901 // this command set MIU to block R2 (does not ack R2's request)
2902 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2903
2904 #ifdef HAL_FEATURE_MAU
2905 // reset MAU
2906 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2907 tempreg1 |= MAU1_REG_SW_RESET;
2908 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2909 #if defined(UDMA_FPGA_ENVI)
2910 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2911 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2912 #endif
2913 #endif
2914
2915 // reset R2
2916 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2917 // by the same RIU write, the R2 reset signal may reach afifo eralier
2918 // than MIU reset and afifo write pointer will be reset to position 0.
2919 // In this case, afifo consider it is not empty because read/write
2920 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2921 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2922 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2923 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2924 VPU_EX_TimerDelayMS(1);
2925 tempreg &= ~VPU_REG_CPU_R2_EN;
2926 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2927 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2928
2929 VPU_EX_TimerDelayMS(1);
2930
2931 // this command set MIU to accept R2 (can ack R2's request)
2932 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2933
2934 pVPUHalContext->_bVPURsted = FALSE;
2935 return TRUE;
2936 }
2937
2938 /*
2939 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2940 {
2941 MS_U16 tempreg = 0, tempreg1 = 0;
2942 #ifndef HAL_FEATURE_MAU
2943 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2944 tempreg |= VPU_REG_CPU_STALL_EN;
2945 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2946
2947 MS_U32 idle_cnt = 100;// ms
2948 while (idle_cnt)
2949 {
2950 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2951 {
2952 break;
2953 }
2954 idle_cnt--;
2955 MsOS_DelayTask(1);
2956 }
2957
2958 if (idle_cnt == 0)
2959 {
2960 VPRINTF("ISB ICU idle time out~~~~~\n");
2961 }
2962
2963 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2964 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2965 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2966 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2967
2968 MS_U32 idle_cnt_1 = 100;// ms
2969 while (idle_cnt_1)
2970 {
2971 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2972 {
2973 break;
2974 }
2975 idle_cnt_1--;
2976 MsOS_DelayTask(1);
2977 }
2978
2979 if (idle_cnt_1 == 0)
2980 {
2981 VPRINTF("BIU DCU idle time out~~~~~\n");
2982 }
2983
2984 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2985 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2986 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2987 VPU_EX_TimerDelayMS(1);
2988 tempreg &= ~VPU_REG_CPU_R2_EN;
2989 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2990 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2991
2992 #else
2993 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2994
2995 if (bCheckMauIdle)
2996 {
2997 MS_U32 mau_idle_cnt = 100;// ms
2998 while (mau_idle_cnt)
2999 {
3000 if (TRUE == _VPU_EX_MAU_IDLE())
3001 {
3002 break;
3003 }
3004 mau_idle_cnt--;
3005 MsOS_DelayTask(1);
3006 }
3007
3008 if (mau_idle_cnt == 0)
3009 {
3010 VPRINTF("MAU idle time out~~~~~\n");
3011 }
3012 }
3013
3014
3015 HAL_VPU_EX_MIU_RW_Protect(TRUE);
3016
3017 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3018 tempreg1 |= MAU1_REG_SW_RESET;
3019 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3020
3021 #if defined(UDMA_FPGA_ENVI)
3022 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3023 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3024 #endif
3025
3026 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3027 tempreg &= ~VPU_REG_CPU_R2_EN;
3028 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3029 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3030 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3031 #endif
3032 VPU_EX_TimerDelayMS(1);
3033 HAL_VPU_EX_MIU_RW_Protect(FALSE);
3034
3035 pVPUHalContext->_bVPURsted = FALSE;
3036 return TRUE;
3037 }
3038 */
3039 ///-----------------------------------------------------------------------------
3040 /// CPU reset release
3041 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)3042 void HAL_VPU_EX_SwRstRelse(void)
3043 {
3044 MS_U16 tempreg = 0;
3045
3046 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
3047 tempreg &= ~VPU_REG_CPU_STALL_EN;
3048 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
3049
3050 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3051 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3052 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3053 VPU_EX_TimerDelayMS(1);
3054 tempreg |= VPU_REG_CPU_SW_RSTZ;
3055 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3056 VPU_EX_TimerDelayMS(1);
3057 tempreg |= VPU_REG_CPU_R2_EN;
3058 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3059 #ifdef HAL_FEATURE_MAU
3060 MS_U16 tempreg1 = 0;
3061 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3062 tempreg1 &= ~MAU1_REG_SW_RESET;
3063 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3064 #endif
3065 pVPUHalContext->_bVPURsted = TRUE;
3066 }
3067
HAL_VPU_EX_SwRelseMAU(void)3068 void HAL_VPU_EX_SwRelseMAU(void)
3069 {
3070
3071 #ifdef HAL_FEATURE_MAU
3072 MS_U16 tempreg = 0;
3073 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
3074 tempreg &= ~MAU1_REG_SW_RESET;
3075 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
3076 #endif
3077 }
3078
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3079 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3080 {
3081 MS_U32 u32value = 0;
3082
3083 return u32value;
3084 }
3085
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3086 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3087 {
3088 MS_BOOL bRet = TRUE;
3089
3090 return bRet;
3091 }
3092
3093 ///-----------------------------------------------------------------------------
3094 /// Check AVCH264 Ready or not
3095 /// @return TRUE or FALSE
3096 /// - TRUE, MailBox is free
3097 /// - FALSE, MailBox is busy
3098 /// @param u8MBox \b IN: MailBox to check
3099 /// - AVCH264_HI_MBOX0,
3100 /// - AVCH264_HI_MBOX1,
3101 /// - AVCH264_RISC_MBOX0,
3102 /// - AVCH264_RISC_MBOX1,
3103 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)3104 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
3105 {
3106 MS_BOOL bResult = FALSE;
3107
3108 switch (u32type)
3109 {
3110 case VPU_HI_MBOX0:
3111 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3112 break;
3113 case VPU_HI_MBOX1:
3114 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3115 break;
3116 case VPU_RISC_MBOX0:
3117 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3118 break;
3119 case VPU_RISC_MBOX1:
3120 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3121 break;
3122 default:
3123 break;
3124 }
3125 return bResult;
3126 }
3127
3128
3129 ///-----------------------------------------------------------------------------
3130 /// Read message from AVCH264
3131 /// @return TRUE or FALSE
3132 /// - TRUE, success
3133 /// - FALSE, failed
3134 /// @param u8MBox \b IN: MailBox to read
3135 /// - AVCH264_RISC_MBOX0
3136 /// - AVCH264_RISC_MBOX1
3137 /// @param u32Msg \b OUT: message read
3138 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)3139 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
3140 {
3141 MS_BOOL bResult = TRUE;
3142
3143 switch (u32type)
3144 {
3145 case VPU_HI_MBOX0:
3146 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3147 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3148 break;
3149 case VPU_HI_MBOX1:
3150 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3151 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3152 break;
3153 case VPU_RISC_MBOX0:
3154 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3155 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3156 break;
3157 case VPU_RISC_MBOX1:
3158 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3159 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3160 break;
3161 default:
3162 *u32Msg = 0;
3163 bResult = FALSE;
3164 break;
3165 }
3166 return bResult;
3167 }
3168
3169 ///-----------------------------------------------------------------------------
3170 /// Mailbox from AVCH264 clear bit resest
3171 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3172 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3173 {
3174 switch (u32type)
3175 {
3176 case VPU_RISC_MBOX0:
3177 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3178 break;
3179 case VPU_RISC_MBOX1:
3180 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3181 break;
3182 default:
3183 break;
3184 }
3185 }
3186
3187 ///-----------------------------------------------------------------------------
3188 /// Send message to AVCH264
3189 /// @return TRUE or FALSE
3190 /// - TRUE, Success
3191 /// - FALSE, Failed
3192 /// @param u8MBox \b IN: MailBox
3193 /// - AVCH264_HI_MBOX0,
3194 /// - AVCH264_HI_MBOX1,
3195 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3196 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3197 {
3198 MS_BOOL bResult = TRUE;
3199
3200 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3201
3202 switch (u32type)
3203 {
3204 case VPU_HI_MBOX0:
3205 {
3206 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3207 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3208 break;
3209 }
3210 case VPU_HI_MBOX1:
3211 {
3212 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3213 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3214 break;
3215 }
3216 default:
3217 {
3218 bResult = FALSE;
3219 break;
3220 }
3221 }
3222
3223 return bResult;
3224 }
3225
HAL_VPU_EX_GetProgCnt(void)3226 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3227 {
3228
3229 MS_U16 expc_l=0;
3230 MS_U16 expc_h=0;
3231 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3232 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3233 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3234 }
3235
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3236 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3237 {
3238 return _VPU_EX_GetOffsetIdx(u32Id);
3239 }
3240
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3241 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3242 {
3243 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3244
3245 if (u32ShmAddr == 0)
3246 {
3247 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3248 }
3249 else
3250 {
3251 if (u8Offset == 0)
3252 {
3253 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3254 }
3255 else if (u8Offset == 1)
3256 {
3257 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3258 }
3259 }
3260
3261 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3262 return;
3263 }
3264
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3265 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3266 {
3267 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3268
3269 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3270 }
3271
3272 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3273 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3274 {
3275 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3276 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3277 MS_VIRT VsyncBridgeOffset = 0;
3278
3279 if (VPUSHMAddr != 0) // TEE project
3280 {
3281 if ((u8Offset == 0) || (u8Offset == 1))
3282 {
3283 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3284 }
3285 else
3286 {
3287 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3288 }
3289 }
3290 else // normal project
3291 {
3292 if ((u8Offset == 0) || (u8Offset == 1))
3293 {
3294 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3295 }
3296 else
3297 {
3298 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3299 }
3300 }
3301
3302 return VsyncBridgeOffset;
3303 }
3304
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3305 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3306 {
3307 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3308 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3309 MS_VIRT VsyncBridgeExtOffset = 0;
3310
3311 if (VPUSHMAddr != 0) // TEE project
3312 {
3313 if ((u8Offset == 0) || (u8Offset == 1))
3314 {
3315 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3316 }
3317 else
3318 {
3319 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3320 }
3321 }
3322 else // normal project
3323 {
3324 if ((u8Offset == 0) || (u8Offset == 1))
3325 {
3326 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3327 }
3328 else
3329 {
3330 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3331 }
3332 }
3333
3334 return VsyncBridgeExtOffset;
3335 }
3336 #endif
3337
HAL_VPU_EX_IsPowered(void)3338 MS_BOOL HAL_VPU_EX_IsPowered(void)
3339 {
3340 return pVPUHalContext->_bVPUPowered;
3341 }
3342
HAL_VPU_EX_IsRsted(void)3343 MS_BOOL HAL_VPU_EX_IsRsted(void)
3344 {
3345 return pVPUHalContext->_bVPURsted;
3346 }
3347
HAL_VPU_EX_IsEVDR2(void)3348 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3349 {
3350 #ifdef EVDR2
3351 return TRUE;
3352 #else
3353 return FALSE;
3354 #endif
3355 }
3356
HAL_VPU_EX_MVDInUsed(void)3357 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3358 {
3359 //MVD is in used for MVD or HVD_TSP mode.
3360 MS_U8 i;
3361 MS_U8 u8UseCnt = 0;
3362
3363 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3364 {
3365 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3366 #ifdef VDEC3
3367 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3368 #endif
3369 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3370 {
3371 u8UseCnt++;
3372 }
3373 }
3374
3375 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3376
3377 if (u8UseCnt != 0)
3378 {
3379 return TRUE;
3380 }
3381 else
3382 {
3383 return FALSE;
3384 }
3385 }
3386
HAL_VPU_EX_HVDInUsed(void)3387 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3388 {
3389 //HVD is in used for HVD or MVD in sub stream.
3390 MS_U8 i;
3391 MS_U8 u8UseCnt = 0;
3392 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3393 {
3394
3395 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype))
3396 {
3397 u8UseCnt++;
3398 }
3399 }
3400
3401 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3402
3403 if (u8UseCnt != 0)
3404 {
3405 return TRUE;
3406 }
3407 else
3408 {
3409 return FALSE;
3410 }
3411 }
3412
HAL_VPU_EX_Mutex_Lock(void)3413 void HAL_VPU_EX_Mutex_Lock(void)
3414 {
3415 _HAL_VPU_Entry();
3416 }
3417
HAL_VPU_EX_Mutex_UnLock(void)3418 void HAL_VPU_EX_Mutex_UnLock(void)
3419 {
3420 _HAL_VPU_Release();
3421 }
3422
3423 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3424 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3425 {
3426 MS_U8 i;
3427 MS_U8 u8UseCnt = 0;
3428
3429 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3430 {
3431 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3432 {
3433 u8UseCnt++;
3434 }
3435 }
3436
3437 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3438
3439 if (u8UseCnt != 0)
3440 {
3441 return TRUE;
3442 }
3443 else
3444 {
3445 return FALSE;
3446 }
3447 }
3448
3449 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3450 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3451 {
3452 MS_U8 i;
3453 MS_U8 u8UseCnt = 0;
3454
3455 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3456 {
3457 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3458 {
3459 u8UseCnt++;
3460 }
3461 }
3462
3463 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3464
3465 if (u8UseCnt != 0)
3466 {
3467 return TRUE;
3468 }
3469 else
3470 {
3471 return FALSE;
3472 }
3473 }
3474 #endif
3475 #endif
3476
3477 //-----------------------------------------------------------------------------
3478 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3479 /// @brief \b Function \b Description: Set debug level
3480 /// @param -elevel \b IN : debug level
3481 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3482 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3483 {
3484 VPRINTF("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3485
3486 switch (eLevel)
3487 {
3488 case E_VPU_EX_UART_LEVEL_ERR:
3489 {
3490 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3491 break;
3492 }
3493 case E_VPU_EX_UART_LEVEL_INFO:
3494 {
3495 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3496 break;
3497 }
3498 case E_VPU_EX_UART_LEVEL_DBG:
3499 {
3500 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3501 break;
3502 }
3503 case E_VPU_EX_UART_LEVEL_TRACE:
3504 {
3505 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3506 break;
3507 }
3508 case E_VPU_EX_UART_LEVEL_FW:
3509 {
3510 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3511 break;
3512 }
3513 default:
3514 {
3515 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3516 break;
3517 }
3518 }
3519 }
3520
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3521 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3522 {
3523 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3524 MS_U32 u32CmdArg = (MS_U32)eVerType;
3525 MS_U32 u32Version = 0xFFFFFFFF;
3526 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3527 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3528 {
3529 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3530 return u32Version;
3531 }
3532
3533 MS_BOOL bRet = false;
3534 MS_U32 u32TimeOut = 0xFFFFFFFF;
3535
3536 while(--u32TimeOut)
3537 {
3538 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3539 {
3540 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3541 if (false == bRet)
3542 {
3543 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3544 return u32Version;
3545 }
3546
3547 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3548 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3549 return u32Version;
3550 }
3551 }
3552
3553 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3554
3555 return u32Version;
3556 }
3557
HAL_VPU_EX_NotSupportDS(void)3558 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3559 {
3560 return FALSE;// maserati disable SN DS
3561 }
3562
3563 //-----------------------------------------------------------------------------
3564 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3565 /// @brief \b Function \b Description: Get VPU MIU base address
3566 /// @return - vpu MIU1 base
3567 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3568 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3569 {
3570 return VPU_MIU1BASE_ADDR;
3571 }
3572
3573
HAL_VPU_EX_GetSHMAddr(void)3574 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3575 {
3576 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3577 {
3578 return 0;
3579 }
3580 return pVPUHalContext->u32VPUSHMAddr;
3581 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3582 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3583 {
3584 pVPUHalContext->bEnableVPUSecureMode = enable;
3585 return TRUE;
3586 }
3587
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3588 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3589 {
3590 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3591
3592 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3593 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3594 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3595 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3596 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3597 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3598 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3599 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3600
3601 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3602 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3603 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3604 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3605 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3606 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3607 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3608 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3609 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3610 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3611
3612 return TRUE;
3613 }
3614
3615 //-----------------------------------------------------------------------------
3616 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3617 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3618 /// @return - success/fail
3619 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3620 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3621 {
3622 #define MAX_CAPABILITY_INFO_NUM 8
3623 #define MAX_CODEC_TYPE_NUM 18
3624
3625 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3626 {
3627 //width, height , frmrate, profile, level, version bit rate reserved2
3628 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3629 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3630 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3631 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3632 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3633 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3634 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3635 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3636 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3637 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3638 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3639 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3640 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3641 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3642 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3643 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3644 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3645 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3646 };
3647
3648 if(eCodecType < MAX_CODEC_TYPE_NUM)
3649 {
3650 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3651 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3652 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3653 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3654 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3655 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3656 return TRUE;
3657 }
3658 else
3659 {
3660 return FALSE;
3661 }
3662 }
3663
3664 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3665 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3666 {
3667 (void) u32Id;
3668 BBU_STATE *bbu_state;
3669
3670 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3671 || (eDecType == E_VPU_EX_DECODER_VP8)
3672 #if SUPPORT_G2VP9
3673 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3674 #endif
3675 )
3676 {
3677 // MVD should not call this function.
3678 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3679 return;
3680 }
3681
3682 switch (eDecType)
3683 {
3684 case E_VPU_EX_DECODER_EVD:
3685 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3686 break;
3687 case E_VPU_EX_DECODER_HVD:
3688 case E_VPU_EX_DECODER_RVD:
3689 case E_VPU_EX_DECODER_MVC:
3690 default:
3691 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3692 break;
3693 }
3694
3695 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3696 return;
3697 }
3698
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3699 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3700 {
3701 (void) u32Id;
3702 BBU_STATE *bbu_state;
3703
3704 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3705 || (eDecType == E_VPU_EX_DECODER_VP8)
3706 #if SUPPORT_G2VP9
3707 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3708 #endif
3709 )
3710 {
3711 // MVD should not call this function.
3712 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3713 return TRUE;
3714 }
3715
3716 switch (eDecType)
3717 {
3718 case E_VPU_EX_DECODER_EVD:
3719 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3720 break;
3721 case E_VPU_EX_DECODER_HVD:
3722 case E_VPU_EX_DECODER_RVD:
3723 case E_VPU_EX_DECODER_MVC:
3724 default:
3725 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3726 break;
3727 }
3728
3729 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3730 }
3731
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3732 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3733 {
3734 (void) u32Id;
3735 BBU_STATE *bbu_state;
3736
3737 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3738 || (eDecType == E_VPU_EX_DECODER_VP8)
3739 #if SUPPORT_G2VP9
3740 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3741 #endif
3742 )
3743 {
3744 // MVD should not call this function.
3745 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3746 return;
3747 }
3748
3749 switch (eDecType)
3750 {
3751 case E_VPU_EX_DECODER_EVD:
3752 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3753 break;
3754 case E_VPU_EX_DECODER_HVD:
3755 case E_VPU_EX_DECODER_RVD:
3756 case E_VPU_EX_DECODER_MVC:
3757 default:
3758 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3759 break;
3760 }
3761
3762 if (bbu_state[u32BBUId].u32Used == 0)
3763 {
3764 bbu_state[u32BBUId].u8RegSetting = 0;
3765 }
3766
3767 return;
3768 }
3769
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3770 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3771 {
3772 MS_U32 i, max_bbu_cnt;
3773 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3774
3775 if(pTaskInfo == NULL)
3776 return retBBUId;
3777
3778 BBU_STATE *bbu_state;
3779 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3780 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3781
3782 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3783
3784 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3785
3786 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3787 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3788 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3789
3790 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3791 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3792
3793 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3794 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3795 */
3796 #if 1
3797 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3798 {
3799 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3800 if (bTSP)
3801 {
3802 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3803 {
3804 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3805 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3806 slq_state[u8TaskId].bTSP = TRUE;
3807 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3808 return u8TaskId;
3809 }
3810 }
3811 else
3812 {
3813 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3814 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3815 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3816 {
3817 if (slq_state[i].u32Used != 0)
3818 {
3819 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3820 {
3821 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3822 }
3823 }
3824 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3825 {
3826 avaliable_bbu_idx = i; // recored the first empty bbu
3827 }
3828 }
3829
3830 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3831
3832 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3833 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3834 slq_state[shared_bbu_idx].bTSP = FALSE;
3835 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3836 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3837 return shared_bbu_idx;
3838 }
3839 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3840 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3841 slq_state[u8TaskId].bTSP = FALSE;
3842 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3843
3844 if (bShareBBU == FALSE)
3845 {
3846 slq_state[u8TaskId].bTSP = TRUE;
3847 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3848 }
3849 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3850 return u8TaskId;
3851 }
3852 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3853 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3854 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3855 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3856
3857 if (bShareBBU == FALSE)
3858 {
3859 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3860 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3861 }
3862 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3863 return avaliable_bbu_idx;
3864 }
3865 else {
3866 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3867 }
3868 }
3869 }
3870 #if SUPPORT_G2VP9
3871 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3872 {
3873 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3874 // Don't care the return value, G2_VP9 will not use it.
3875 return 0;
3876 }
3877 #endif
3878 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3879 {
3880 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3881 // Don't care the return value, VP8 will not use it.
3882 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3883 return u8Offset;
3884 //return 0;
3885 }
3886 else
3887 {
3888 switch (pTaskInfo->eDecType)
3889 {
3890 case E_VPU_EX_DECODER_EVD:
3891 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3892 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3893 break;
3894 case E_VPU_EX_DECODER_HVD:
3895 case E_VPU_EX_DECODER_RVD:
3896 case E_VPU_EX_DECODER_MVC:
3897 default:
3898 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3899 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3900 break;
3901 }
3902
3903 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3904 if (bTSP)
3905 {
3906 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3907 {
3908 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3909 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3910 bbu_state[u8TaskId].bTSP = TRUE;
3911 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3912 slq_state[u8TaskId].bTSP = TRUE;
3913 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3914 return u8TaskId;
3915 }
3916 }
3917 else
3918 {
3919 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3920 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3921 for (i = 0; i < max_bbu_cnt; i++)
3922 {
3923 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3924 {
3925 if (bbu_state[i].bTSP == FALSE)
3926 {
3927 shared_bbu_idx = i;
3928 }
3929 }
3930 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3931 {
3932 avaliable_bbu_idx = i;
3933 }
3934 }
3935
3936 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3937
3938 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3939 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3940 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3941 return shared_bbu_idx;
3942 }
3943 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3944 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3945
3946 if (bShareBBU == FALSE)
3947 {
3948 bbu_state[u8TaskId].bTSP = TRUE;
3949 VPRINTF("[NDec] occupy one BBU_ID \n");
3950 }
3951 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3952 return u8TaskId;
3953 }
3954 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3955 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3956
3957 if (bShareBBU == FALSE)
3958 {
3959 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3960 VPRINTF("[NDec] occupy one BBU_ID \n");
3961 }
3962 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3963 return avaliable_bbu_idx;
3964 }
3965 else {
3966 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3967 }
3968 }
3969 }
3970 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3971 MS_U32 j;
3972 MS_BOOL Got = FALSE;
3973 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3974 {
3975 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3976 {
3977 if(slq_state[i].u32Used != 0)
3978 {
3979 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3980 {
3981 retBBUId = i;
3982 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3983 slq_state[retBBUId].bTSP = bTSP;
3984 slq_state[retBBUId].bUsedbyMVD = TRUE;
3985 return retBBUId;
3986 }
3987 }
3988 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3989 {
3990 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3991 {
3992 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3993 {
3994 Got = TRUE;
3995 retBBUId = i;
3996 }
3997 }
3998
3999 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
4000 {
4001 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
4002 {
4003 Got = TRUE;
4004 retBBUId = i;
4005 }
4006 }
4007
4008 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
4009 retBBUId = i;
4010 }
4011 }
4012 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4013 {
4014 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4015 slq_state[retBBUId].bTSP = bTSP;
4016 slq_state[retBBUId].bUsedbyMVD = TRUE;
4017 }
4018 }
4019 #if SUPPORT_G2VP9
4020 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4021 {
4022 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4023 // Don't care the return value, G2_VP9 will not use it.
4024 return 0;
4025 }
4026 #endif
4027 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4028 {
4029 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4030 // Don't care the return value, VP8 will not use it.
4031 return 0;
4032 }
4033 else // HVD/EVD case
4034 {
4035 switch (pTaskInfo->eDecType)
4036 {
4037 case E_VPU_EX_DECODER_EVD:
4038 case E_VPU_EX_DECODER_G2VP9:
4039 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4040 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4041 break;
4042 case E_VPU_EX_DECODER_HVD:
4043 case E_VPU_EX_DECODER_RVD:
4044 case E_VPU_EX_DECODER_MVC:
4045 default:
4046 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4047 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4048 break;
4049 }
4050
4051 for (i = 0; i < max_bbu_cnt; i++)
4052 {
4053 if(bbu_state[i].u32Used != 0)
4054 {
4055 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
4056 {
4057 retBBUId = i;
4058 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4059 bbu_state[retBBUId].bTSP = bTSP;
4060 return retBBUId;
4061 }
4062 }
4063 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
4064 {
4065 if(i < MAX_MVD_SLQ_COUNT)
4066 {
4067 if(!bTSP) //HVD/EVD first MM case
4068 {
4069 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
4070 {
4071 retBBUId = i;
4072 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4073 bbu_state[retBBUId].bTSP = bTSP;
4074 return retBBUId;
4075 }
4076
4077 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
4078 retBBUId = i;
4079 }
4080 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
4081 {
4082 retBBUId = i;
4083 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4084 bbu_state[retBBUId].bTSP = bTSP;
4085 slq_state[retBBUId].bUsedbyMVD = FALSE;
4086 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4087 slq_state[retBBUId].bTSP = bTSP;
4088 return retBBUId;
4089 }
4090 }
4091 }
4092 }
4093 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4094 {
4095 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4096 bbu_state[retBBUId].bTSP = bTSP;
4097 if(bTSP)
4098 {
4099 slq_state[retBBUId].bUsedbyMVD = FALSE;
4100 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4101 slq_state[retBBUId].bTSP = bTSP;
4102 }
4103 }
4104 }
4105 #endif
4106 return retBBUId;
4107 }
4108
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)4109 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
4110 {
4111 MS_U32 max_bbu_cnt;
4112 BBU_STATE *bbu_state;
4113 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
4114
4115 if(pTaskInfo == NULL)
4116 return FALSE;
4117 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4118 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4119
4120 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4121 /* MS_U32 i;
4122 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4123 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4124
4125 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4126 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
4127
4128 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4129 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
4130 */
4131 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4132 {
4133 // TO DO
4134 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4135 {
4136 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4137 slq_state[u32BBUId].bTSP = FALSE;
4138 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4139 return TRUE;
4140 }
4141 }
4142 #if SUPPORT_G2VP9
4143 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4144 {
4145 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4146 return TRUE;
4147 }
4148 #endif
4149 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4150 {
4151 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4152 return TRUE;
4153 }
4154 else
4155 {
4156 switch (pTaskInfo->eDecType)
4157 {
4158 case E_VPU_EX_DECODER_EVD:
4159 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4160 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4161 break;
4162 case E_VPU_EX_DECODER_HVD:
4163 case E_VPU_EX_DECODER_RVD:
4164 case E_VPU_EX_DECODER_MVC:
4165 default:
4166 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4167 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4168 break;
4169 }
4170
4171 if (u32BBUId < max_bbu_cnt)
4172 {
4173 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4174 bbu_state[u32BBUId].bTSP = FALSE;
4175
4176 if (bTSP)
4177 {
4178 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4179 slq_state[u32BBUId].bTSP = FALSE;
4180 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4181 }
4182
4183 #if 1
4184 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4185 #else
4186 if (bbu_state[u32BBUId].u32Used == 0)
4187 {
4188 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4189 }
4190 #endif
4191
4192 return TRUE;
4193 }
4194 }
4195 return FALSE;
4196 }
4197
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4198 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4199 {
4200 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4201
4202 if (CHECK_NULL_PTR(pstVBBU))
4203 return 0;
4204 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4205 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4206 MS_U32 u32Vacancy = 0;
4207
4208 if (u32WrPtr == u32RdPtr)
4209 {
4210 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4211 }
4212 else if (u32WrPtr > u32RdPtr)
4213 {
4214 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4215 }
4216 else
4217 {
4218 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4219 }
4220
4221 return u32Vacancy;
4222 }
4223
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4224 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4225 {
4226 return MAX_VDEC_VBBU_ENTRY_COUNT;
4227 }
4228
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4229 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4230 {
4231 return pVPUHalContext->u32FWCodeAddr;
4232 }
4233
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4234 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4235 {
4236 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4237 #if SUPPORT_G2VP9
4238 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4239 #endif
4240
4241 if (CHECK_NULL_PTR(pstVBBU))
4242 return FALSE;
4243 MsOS_ReadMemory();
4244 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4245
4246 if(NULL == stEntry)
4247 {
4248 return 0;
4249 }
4250
4251 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4252 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4253 {
4254 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4255 }
4256 else
4257 {
4258 #if SUPPORT_G2VP9
4259 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4260 {
4261 if (stEntry->u32Offset == 0)
4262 return 0;
4263 else
4264 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4265 }
4266 else
4267 #endif
4268 {
4269 return stEntry->u32Offset;
4270 }
4271 }
4272 }
4273
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4274 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4275 {
4276 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4277 VDEC_VBBU_Entry *stEntry;
4278 #if SUPPORT_G2VP9
4279 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4280 #endif
4281
4282 MsOS_ReadMemory();
4283 if (CHECK_NULL_PTR(pstVBBU))
4284 return 0;
4285 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4286
4287 if (u32WrPtr == 0)
4288 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4289 else
4290 u32WrPtr--;
4291
4292 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4293
4294 if(NULL == stEntry)
4295 {
4296 return 0;
4297 }
4298
4299 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4300 #if SUPPORT_G2VP9
4301 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4302 {
4303 if (stEntry->u32Offset == 0)
4304 return 0;
4305 else
4306 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4307 }
4308 else
4309 #endif
4310 {
4311 return stEntry->u32Offset + stEntry->u32Length;
4312 }
4313 }
4314
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4315 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4316 {
4317 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4318 #if SUPPORT_G2VP9
4319 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4320 #endif
4321
4322 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4323 return FALSE;
4324 MsOS_ReadMemory();
4325 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4326 MS_U32 u32NewWrPtr;
4327
4328 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4329 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4330 {
4331 u32NewWrPtr = 0;
4332 }
4333
4334 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4335
4336 stEntry->u32Offset = stVpuPkt->u32Offset;
4337
4338 #if SUPPORT_G2VP9
4339 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4340 {
4341 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4342 }
4343 #endif
4344
4345 stEntry->u32Length = stVpuPkt->u32Length;
4346 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4347 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4348 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4349
4350 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4351
4352 pstVBBU->u32WrPtr = u32NewWrPtr;
4353
4354 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4355
4356 MsOS_FlushMemory();
4357
4358 return TRUE;
4359 }
4360
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4361 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4362 {
4363 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4364
4365 if (CHECK_NULL_PTR(pstVBBU))
4366 return FALSE;
4367 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4368 }
4369
4370 ///-----------------------------------------------------------------------------
4371 /// specify the command send to Mail box or DRAM
4372 /// @return TRUE or FALSE
4373 /// - TRUE, Mail box
4374 /// - FALSE, Dram
4375 /// @param u32Cmd \b IN: Command is going to be sned
4376 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4377 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4378 {
4379 MS_BOOL bResult = TRUE;
4380
4381 switch (u32Cmd)
4382 {
4383 // *********** Runtime action Command
4384 /* case E_HVD_CMD_RELEASE_DISPQ:
4385 case E_HVD_CMD_UPDATE_DISPQ:
4386 case E_HVD_CMD_FLUSH_DEC_Q:
4387 case E_HVD_CMD_FLUSH:
4388 case E_HVD_CMD_PLAY:
4389 case E_HVD_CMD_PAUSE:
4390 case E_HVD_CMD_STOP:
4391 case E_HVD_CMD_STEP_DECODE:
4392 case E_HVD_CMD_SKIP_DEC:
4393 case E_HVD_CMD_DISP_I_DIRECT:*/
4394 // *********** Dual-Stream Create Task Command
4395 case E_DUAL_CMD_TASK0_HVD_BBU:
4396 case E_DUAL_CMD_TASK0_HVD_TSP:
4397 case E_DUAL_CMD_TASK0_MVD_SLQ:
4398 case E_DUAL_CMD_TASK0_MVD_TSP:
4399 case E_DUAL_CMD_TASK1_HVD_BBU:
4400 case E_DUAL_CMD_TASK1_HVD_TSP:
4401 case E_DUAL_CMD_MODE:
4402 #ifndef _WIN32
4403 case E_DUAL_CMD_TASK1_MVD_SLQ:
4404 case E_DUAL_CMD_TASK1_MVD_TSP:
4405 #endif
4406 case E_DUAL_CMD_DEL_TASK:
4407 case E_DUAL_CMD_SINGLE_TASK:
4408 case E_DUAL_VERSION:
4409 case E_DUAL_R2_CMD_EXIT:
4410 case E_DUAL_CMD_STC_MODE:
4411 #ifdef VDEC3
4412 case E_DUAL_R2_CMD_FBADDR:
4413 case E_DUAL_R2_CMD_FBSIZE:
4414 // *********** N-Streams
4415 case E_NST_CMD_TASK_HVD_TSP:
4416 case E_NST_CMD_TASK_HVD_BBU:
4417 case E_NST_CMD_TASK_MVD_TSP:
4418 case E_NST_CMD_TASK_MVD_SLQ:
4419 case E_NST_CMD_DEL_TASK:
4420 case E_NST_CMD_COMMON_MASK:
4421 case E_NST_CMD_COMMON_CMD1:
4422 #endif
4423 case E_DUAL_CMD_COMMON:
4424 {
4425 bResult = TRUE;
4426 }
4427 break;
4428 default:
4429 {
4430 bResult = FALSE;
4431 }
4432 break;
4433 }
4434
4435 return bResult;
4436 }
4437
4438 ///-----------------------------------------------------------------------------
4439 /// specify the command send to Mail box or DRAM
4440 /// @return TRUE or FALSE
4441 /// - TRUE, Mail box
4442 /// - FALSE, Dram
4443 /// @param u32Cmd \b IN: Command is going to be sned
4444 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4445 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4446 {
4447 MS_BOOL bResult = TRUE;
4448
4449 switch (u32Cmd)
4450 {
4451 // *********** Runtime action Command
4452 case E_HVD_CMD_RELEASE_DISPQ:
4453 case E_HVD_CMD_UPDATE_DISPQ:
4454 case E_HVD_CMD_FLUSH_DEC_Q:
4455 case E_HVD_CMD_PAUSE:
4456 case E_HVD_CMD_FLUSH:
4457 case E_HVD_CMD_PLAY:
4458 case E_HVD_CMD_STOP:
4459 case E_HVD_CMD_SKIP_DEC:
4460 case E_HVD_CMD_DISP_I_DIRECT:
4461 case E_HVD_CMD_STEP_DECODE:
4462 case E_HVD_CMD_INC_DISPQ_NUM:
4463 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4464 {
4465 bResult = TRUE;
4466 }
4467 break;
4468 default:
4469 {
4470 bResult = FALSE;
4471 }
4472 break;
4473 }
4474
4475 return bResult;
4476 }
4477
4478 ///-----------------------------------------------------------------------------
4479 /// Send message to HVD stream command queue
4480 /// @return TRUE or FALSE
4481 /// - TRUE, Success
4482 /// - FALSE, Failed
4483 /// @param u32DramAddr \b IN: address to be writen
4484 /// @param u32Msg \b IN: data to be writen
4485 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4486 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4487 {
4488 MS_BOOL bResult = TRUE;
4489
4490 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4491
4492 WRITE_LONG(u32DramAddr,u32Msg);
4493
4494 return bResult;
4495 }
4496
4497 ///-----------------------------------------------------------------------------
4498 /// Read task share memory to specify that task command queue is empty or not
4499 /// @return TRUE or FALSE
4500 /// - TRUE, Empty
4501 /// - FALSE, Non empty
4502 /// @param u32Id \b IN: Task information
4503 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4504 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4505 {
4506 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4507 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4508 if (!cmd_q)
4509 {
4510 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4511 return FALSE;
4512 }
4513
4514 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4515 }
4516
4517 ///-----------------------------------------------------------------------------
4518 /// Read task share memory to specify that task command queue is full or not
4519 /// @return TRUE or FALSE
4520 /// - TRUE, Full
4521 /// - FALSE, Non full
4522 /// @param u32Id \b IN: Task information
4523 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4524 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4525 {
4526 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4527 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4528 if (!cmd_q)
4529 {
4530 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4531 return TRUE;
4532 }
4533 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4534
4535 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4536 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4537
4538 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4539 }
4540
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4541 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4542 {
4543 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4544 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4545 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4546
4547 #if HVD_ENABLE_MVC
4548 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4549 {
4550 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4551 }
4552 #endif
4553
4554 if (CHECK_NULL_PTR(cmd_q))
4555 {
4556 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4557 return bResult;
4558 }
4559 MS_VIRT u32CmdQWdPtr;
4560
4561 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4562 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4563
4564 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4565 return E_HVD_COMMAND_QUEUE_FULL;
4566 else
4567 {
4568 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4569 }
4570
4571 switch (u8CmdType)
4572 {
4573 case E_HVD_CMDQ_CMD:
4574 {
4575 u32Msg |= (u8TaskID << 24);
4576 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4577
4578 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4579
4580 if (bResult)
4581 {
4582 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4583
4584 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4585 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4586
4587 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4588 }
4589 break;
4590 }
4591 case E_HVD_CMDQ_ARG:
4592 {
4593 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4594 if (bResult)
4595 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4596 break;
4597 }
4598 default:
4599 {
4600 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4601 break;
4602 }
4603 }
4604
4605 MsOS_FlushMemory();
4606
4607 return bResult;
4608 }
4609
4610 ///-----------------------------------------------------------------------------
4611 /// Read task share memory to specify that task display command queue is empty or not
4612 /// @return TRUE or FALSE
4613 /// - TRUE, Empty
4614 /// - FALSE, Non empty
4615 /// @param u32Id \b IN: Task information
4616 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4617 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4618 {
4619 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4620 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4621 if (!cmd_q)
4622 {
4623 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4624 return FALSE;
4625 }
4626
4627 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4628 }
4629
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4630 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4631 {
4632 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4633 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4634 if (!cmd_q)
4635 {
4636 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4637 return TRUE;
4638 }
4639
4640 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4641
4642 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4643 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4644
4645 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4646 }
4647
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4648 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4649 {
4650 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4651 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4652 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4653
4654 #if HVD_ENABLE_MVC
4655 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4656 {
4657 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4658 }
4659 #endif
4660
4661 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4662 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4663
4664 if (CHECK_NULL_PTR(cmd_q))
4665 {
4666 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4667 return bResult;
4668 }
4669
4670 MS_VIRT u32DISPCMDQWdPtr;
4671
4672 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4673 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4674
4675 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4676 return E_HVD_COMMAND_QUEUE_FULL;
4677 else
4678 {
4679 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4680 }
4681
4682 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4683
4684 switch (u8CmdType)
4685 {
4686 case E_HVD_CMDQ_CMD:
4687 {
4688 u32Msg |= (u8TaskID << 24);
4689 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4690
4691 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4692
4693 if (bResult)
4694 {
4695 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4696
4697 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4698 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4699
4700 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4701 }
4702 break;
4703 }
4704 case E_HVD_CMDQ_ARG:
4705 {
4706 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4707 if (bResult)
4708 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4709 break;
4710 }
4711 default:
4712 {
4713 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4714 break;
4715 }
4716 }
4717
4718 MsOS_FlushMemory();
4719
4720 return bResult;
4721 }
4722
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4723 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4724 {
4725 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4726 MS_U32 u32StAddr;
4727 MS_U8 u8TmpMiuSel;
4728
4729 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4730
4731 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4732
4733 return TRUE;
4734 }
4735 #endif
4736
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4737 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4738 {
4739 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4740
4741 if(u32address >= HAL_MIU1_BASE)
4742 {
4743 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4744 }
4745 else
4746 {
4747 pVPUHalContext->u32DynamicFBAddress = u32address;
4748 }
4749
4750 pVPUHalContext->u32DynamicFBSize = u32Size;
4751 }
4752 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4753 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4754 {
4755 MS_S32 handle;
4756 switch(eClkPortType)
4757 {
4758 case E_VPU_EX_CLKPORT_MVD:
4759 {
4760 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4761 if(bEnable)
4762 {
4763 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4764 }
4765 else
4766 {
4767 Drv_Clkm_Clk_Gate_Disable(handle);
4768 }
4769 break;
4770 }
4771 case E_VPU_EX_CLKPORT_MVD_CORE:
4772 {
4773 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4774 if(bEnable)
4775 {
4776 Drv_Clkm_Set_Clk_Source(handle, "");
4777 }
4778 else
4779 {
4780 Drv_Clkm_Clk_Gate_Disable(handle);
4781 }
4782 break;
4783 }
4784 case E_VPU_EX_CLKPORT_MVD_PAS:
4785 {
4786 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4787 if(bEnable)
4788 {
4789 Drv_Clkm_Set_Clk_Source(handle, "");
4790 }
4791 else
4792 {
4793 Drv_Clkm_Clk_Gate_Disable(handle);
4794 }
4795 break;
4796 }
4797 case E_VPU_EX_CLKPORT_HVD:
4798 {
4799 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4800 if(bEnable)
4801 {
4802 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4803 }
4804 else
4805 {
4806 Drv_Clkm_Clk_Gate_Disable(handle);
4807 }
4808 break;
4809 }
4810 case E_VPU_EX_CLKPORT_HVD_IDB:
4811 {
4812 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4813 if(bEnable)
4814 {
4815 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4816 }
4817 else
4818 {
4819 Drv_Clkm_Clk_Gate_Disable(handle);
4820 }
4821 break;
4822 }
4823 case E_VPU_EX_CLKPORT_HVD_AEC:
4824 {
4825 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4826 if(bEnable)
4827 {
4828 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4829 }
4830 else
4831 {
4832 Drv_Clkm_Clk_Gate_Disable(handle);
4833 }
4834 break;
4835 }
4836 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4837 {
4838 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4839 if(bEnable)
4840 {
4841 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4842 }
4843 else
4844 {
4845 Drv_Clkm_Clk_Gate_Disable(handle);
4846 }
4847 break;
4848 }
4849 case E_VPU_EX_CLKPORT_VP8:
4850 {
4851 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4852 if(bEnable)
4853 {
4854 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4855 }
4856 else
4857 {
4858 Drv_Clkm_Clk_Gate_Disable(handle);
4859 }
4860 break;
4861 }
4862 case E_VPU_EX_CLKPORT_EVD:
4863 {
4864 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4865 if(bEnable)
4866 {
4867 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4868 }
4869 else
4870 {
4871 Drv_Clkm_Clk_Gate_Disable(handle);
4872 }
4873 break;
4874 }
4875 case E_VPU_EX_CLKPORT_EVD_PPU:
4876 {
4877 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4878 if(bEnable)
4879 {
4880 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4881 }
4882 else
4883 {
4884 Drv_Clkm_Clk_Gate_Disable(handle);
4885 }
4886 break;
4887 }
4888 case E_VPU_EX_CLKPORT_EVD_LITE:
4889 {
4890 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4891 if(bEnable)
4892 {
4893 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4894 }
4895 else
4896 {
4897 Drv_Clkm_Clk_Gate_Disable(handle);
4898 }
4899 break;
4900 }
4901 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4902 {
4903 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4904 if(bEnable)
4905 {
4906 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4907 }
4908 else
4909 {
4910 Drv_Clkm_Clk_Gate_Disable(handle);
4911 }
4912 break;
4913 }
4914 case E_VPU_EX_CLKPORT_VD_MHEG5:
4915 {
4916 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4917 if(bEnable)
4918 {
4919 Drv_Clkm_Set_Clk_Source(handle, "");
4920 }
4921 else
4922 {
4923 Drv_Clkm_Clk_Gate_Disable(handle);
4924 }
4925 break;
4926 }
4927 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4928 {
4929 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4930 if(bEnable)
4931 {
4932 Drv_Clkm_Set_Clk_Source(handle, "");
4933 }
4934 else
4935 {
4936 Drv_Clkm_Clk_Gate_Disable(handle);
4937 }
4938 break;
4939 }
4940 }
4941 }
4942 #endif //#ifdef CONFIG_MSTAR_CLKM
4943
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4944 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4945 {
4946 MS_SIZE FrameBufferSize = 0;
4947
4948 switch(eCodecType)
4949 {
4950 case E_VPU_EX_CODEC_TYPE_MPEG2:
4951 case E_VPU_EX_CODEC_TYPE_H263:
4952 case E_VPU_EX_CODEC_TYPE_MPEG4:
4953 case E_VPU_EX_CODEC_TYPE_DIVX311:
4954 case E_VPU_EX_CODEC_TYPE_DIVX412:
4955 case E_VPU_EX_CODEC_TYPE_FLV:
4956 FrameBufferSize = 0x1E00000;
4957 break;
4958 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4959 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4960 FrameBufferSize = 0x6C00000;
4961 break;
4962 case E_VPU_EX_CODEC_TYPE_RV8:
4963 case E_VPU_EX_CODEC_TYPE_RV9:
4964 FrameBufferSize = 0x1B00000;
4965 break;
4966 case E_VPU_EX_CODEC_TYPE_VP8:
4967 FrameBufferSize = 0x1500000;
4968 break;
4969 case E_VPU_EX_CODEC_TYPE_H264:
4970 FrameBufferSize = 0x8200000;
4971 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4972 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4973 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4974 break;
4975 case E_VPU_EX_CODEC_TYPE_AVS:
4976 FrameBufferSize = 0x1B00000;
4977 break;
4978 case E_VPU_EX_CODEC_TYPE_MJPEG:
4979 FrameBufferSize = 0x2800000;
4980 break;
4981 case E_VPU_EX_CODEC_TYPE_MVC:
4982 FrameBufferSize = 0x4200000;
4983 break;
4984 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4985 FrameBufferSize = 0xB000000;
4986 break;
4987 case E_VPU_EX_CODEC_TYPE_HEVC:
4988 #if SUPPORT_MSVP9
4989 case E_VPU_EX_CODEC_TYPE_VP9:
4990 #endif
4991 FrameBufferSize = 0xA000000;
4992 break;
4993 #if !SUPPORT_MSVP9
4994 case E_VPU_EX_CODEC_TYPE_VP9:
4995 FrameBufferSize = 0x7800000;
4996 break;
4997 #endif
4998 default:
4999 FrameBufferSize = 0;
5000 break;
5001 }
5002
5003 return FrameBufferSize;
5004 }
5005
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)5006 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
5007 {
5008 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5009 }
5010
5011 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)5012 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
5013 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
5014 {
5015 MS_SIZE FrameBufferSize = 0;
5016
5017 if (!offset || !length)
5018 return FALSE;
5019
5020 total_length -= unUseSize;
5021 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
5022 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
5023
5024 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5025
5026 if(FrameBufferSize == 0)
5027 {
5028 return FALSE;
5029 }
5030 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
5031 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
5032 if (total_length < FrameBufferSize)
5033 {
5034 *offset = unUseSize;
5035 *length = total_length;
5036 }
5037 else // todo, dual decode case
5038 {
5039 *offset = unUseSize;
5040 *length = FrameBufferSize;
5041 }
5042 return TRUE;
5043 }
5044
HAL_VPU_EX_strcmp(const char * string1,const char * string2)5045 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
5046 {
5047 int iRet, i;
5048
5049 i = 0;
5050 while(string1[i] || string2[i])
5051 {
5052 iRet = string1[i] - string2[i];
5053 if(iRet)
5054 {
5055 return iRet;
5056 }
5057 i++;
5058 }
5059 return 0;
5060 }
5061
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)5062 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
5063 {
5064 typedef enum
5065 {
5066 E_CAP_NDEC_FB_MIU_SELECT,
5067 E_CAP_NDEC_NSTREAM_FB_SIZE,
5068 E_CAP_NDEC_NSTREAM_BS_SIZE,
5069 E_CAP_NDEC_SUPPORT_SHAREBBU,
5070 E_CAP_SUPPORT_ALLOCATOR,
5071
5072 } VPU_EX_GetCapabilityCmdId;
5073
5074 typedef struct
5075 {
5076 VPU_EX_GetCapabilityCmdId eCmdId;
5077 MS_U8 u8CmdName[32];
5078
5079 } VPU_EX_GetCapabilityCmd;
5080
5081 static VPU_EX_GetCapabilityCmd stCapCmd[] =
5082 {
5083 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
5084 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
5085 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
5086 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
5087 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
5088 };
5089
5090 MS_U32 bRet = FALSE;
5091 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
5092 MS_U32 u32CmdCnt;
5093
5094 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
5095 {
5096 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
5097 {
5098 bRet = TRUE;
5099 switch(stCapCmd[u32CmdCnt].eCmdId)
5100 {
5101 case E_CAP_NDEC_FB_MIU_SELECT:
5102 {
5103 VPU_EX_CodecType eCodecType = *((VPU_EX_CodecType *)pParamIn);
5104 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5105 if(eCodecType == E_VPU_EX_CODEC_TYPE_MJPEG ||
5106 eCodecType == E_VPU_EX_CODEC_TYPE_VP8)
5107 {
5108 *pSupport = FALSE;
5109 VPU_MSG_ERR("[NDec][ALLOC] Not support frame buffer at different MIU: VP8, MJPEG\n");
5110 }
5111 else
5112 {
5113 *pSupport = TRUE;
5114 }
5115 }
5116 break;
5117
5118 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
5119 case E_CAP_NDEC_NSTREAM_FB_SIZE:
5120 {
5121 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5122 *pSize = 0x3500000; // 53M
5123 }
5124 break;
5125
5126 // FIXME: Patch for waiting dynamic bitstream buffer
5127 case E_CAP_NDEC_NSTREAM_BS_SIZE:
5128 {
5129 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5130 *pSize = 0x400000; // 4M
5131 }
5132 break;
5133
5134 case E_CAP_NDEC_SUPPORT_SHAREBBU:
5135 {
5136 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
5137 *pbSupportShareBBU = TRUE;
5138 }
5139 break;
5140
5141 case E_CAP_SUPPORT_ALLOCATOR:
5142 {
5143 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5144 *pSupport = TRUE;
5145 }
5146 break;
5147
5148 default:
5149 bRet = FALSE;
5150 break;
5151 }
5152 }
5153 }
5154
5155 return bRet;
5156 }
5157
5158 #else
5159 #include "halVPU_EX.h"
5160 #include "drvMMIO.h"
5161 #include "../hvd_v3/regHVD_EX.h"
5162 #include "halCHIP.h"
5163
5164 #if defined(MSOS_TYPE_NUTTX)
5165 extern int lib_lowprintf(const char *fmt, ...);
5166 #define PRINTF lib_lowprintf
5167 #elif defined(MSOS_TYPE_OPTEE)
5168 #define PRINTF printf
5169 #endif
5170
5171 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5172 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5173
5174 MS_U8 u8FW_Binary[] = {
5175 #include "fwVPU.dat"
5176 };
5177
5178 MS_U32 u32HVDRegOSBase;
5179
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5180 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5181 {
5182 //PRINTF("do load code,u32DestAddr %x\n",addr);
5183 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5184 MAsm_CPU_Sync();
5185 MsOS_FlushMemory();
5186
5187 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5188 {
5189 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5190 return FALSE;
5191 }
5192 return TRUE;
5193 }
5194
HAL_VPU_EX_SetLockDownRegister(void * param)5195 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5196 {
5197 #if 1
5198 MS_PHY u32StAddr_main;
5199 MS_PHY u32StAddr_sub;
5200 MS_U32 u32NonPMBankSize = 0;
5201 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5202
5203 if(param == NULL)
5204 {
5205 return FALSE;
5206 }
5207
5208 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5209
5210 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5211
5212 // ES buffer
5213 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5214 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5215
5216
5217 MS_PHY u32StartOffset;
5218 MS_U8 u8MiuSel;
5219
5220 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5221 u32StAddr_main = u32StartOffset;
5222
5223 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5224 u32StAddr_sub = u32StartOffset;
5225
5226 //Lock down register
5227 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5228 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5229
5230 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
5231 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
5232 //~
5233
5234 // Lock Down
5235 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5236 //~
5237 #endif
5238 return TRUE;
5239 }
5240
5241 #endif
5242