1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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11 //
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 4 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 4 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 4
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216 typedef struct
217 {
218 MS_BOOL bSTCSetMode;
219 MS_U32 u32STCIndex;
220 } VPU_EX_STC;
221
222 #define VPU_MSG_ERR(format, args...) \
223 do \
224 { \
225 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
226 { \
227 printf("[VPU][ERR]%s:", __FUNCTION__); \
228 printf(format, ##args); \
229 } \
230 } while (0)
231
232 #define VPU_MSG_DBG(format, args...) \
233 do \
234 { \
235 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
236 { \
237 printf("[VPU][DBG]%s:", __FUNCTION__); \
238 printf(format, ##args); \
239 } \
240 } while (0)
241
242 #define VPU_MSG_INFO(format, args...) \
243 do \
244 { \
245 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
246 { \
247 printf("[VPU][INF]%s:", __FUNCTION__); \
248 printf(format, ##args); \
249 } \
250 } while (0)
251
252 //------------------------------ MIU SETTINGS ----------------------------------
253 //#ifdef EVDR2
254 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
255 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5))
256 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(3))
257
258 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
259 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
260 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(3))
261
262
263
264 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
265 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) )
266 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) ) //g03
267 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
268 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) )
269 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == BIT(3)) ) //g03
270
271 //#endif
272
273
274
275 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
276 do \
277 { \
278 if (miu_clients##_ON_MIU0 == 1) \
279 { \
280 _MaskMiuReq_##miu_clients(mask); \
281 } \
282 else \
283 { \
284 if (miu_clients##_ON_MIU1 == 1) \
285 { \
286 _MaskMiu1Req_##miu_clients(mask); \
287 } \
288 \
289 } \
290 } while(0)
291
292
293
294
295 #if ENABLE_VPU_MUTEX_PROTECTION
296 MS_S32 s32VPUMutexID = -1;
297 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
298
299 #define _HAL_VPU_MutexCreate() \
300 if (s32VPUMutexID < 0) \
301 { \
302 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
303 }
304
305 #define _HAL_VPU_MutexDelete() \
306 if (s32VPUMutexID >= 0) \
307 { \
308 MsOS_DeleteMutex(s32VPUMutexID); \
309 s32VPUMutexID = -1; \
310 }
311
312 #define _HAL_VPU_Entry() \
313 if (s32VPUMutexID >= 0) \
314 { \
315 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
316 { \
317 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
318 } \
319 }
320
321 #define _HAL_VPU_Return(_ret) \
322 { \
323 if (s32VPUMutexID >= 0) \
324 { \
325 MsOS_ReleaseMutex(s32VPUMutexID); \
326 } \
327 return _ret; \
328 }
329
330 #define _HAL_VPU_Release() \
331 { \
332 if (s32VPUMutexID >= 0) \
333 { \
334 MsOS_ReleaseMutex(s32VPUMutexID); \
335 } \
336 }
337 #else
338 #define _HAL_VPU_MutexCreate()
339 #define _HAL_VPU_MutexDelete()
340 #define _HAL_VPU_Entry()
341 #define _HAL_VPU_Return(_ret) {return _ret;}
342 #define _HAL_VPU_Release()
343 #endif
344
345 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
346 #define VPU_CMD_TIMEOUT 1000 // 1 sec
347
348 //-------------------------------------------------------------------------------------------------
349 // Local Structures
350 //-------------------------------------------------------------------------------------------------
351 typedef struct _VPU_HWInitFunc
352 {
353 MS_BOOL (*pfMVDHW_Init)(void);
354 MS_BOOL (*pfMVDHW_Deinit)(void);
355 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
356 MS_BOOL (*pfHVDHW_Deinit)(void);
357 } VPU_HWInitFunc;
358
359 typedef struct
360 {
361 MS_U32 u32ApiHW_Version; //<Version of current structure>
362 MS_U16 u16ApiHW_Length; //<Length of this structure>
363
364 MS_U8 u8Cap_Support_Decoder_Num;
365
366 MS_BOOL bCap_Support_MPEG2;
367 MS_BOOL bCap_Support_H263;
368 MS_BOOL bCap_Support_MPEG4;
369 MS_BOOL bCap_Support_DIVX311;
370 MS_BOOL bCap_Support_DIVX412;
371 MS_BOOL bCap_Support_FLV;
372 MS_BOOL bCap_Support_VC1ADV;
373 MS_BOOL bCap_Support_VC1MAIN;
374
375 MS_BOOL bCap_Support_RV8;
376 MS_BOOL bCap_Support_RV9;
377 MS_BOOL bCap_Support_H264;
378 MS_BOOL bCap_Support_AVS;
379 MS_BOOL bCap_Support_AVS_PLUS;
380 MS_BOOL bCap_Support_MJPEG;
381 MS_BOOL bCap_Support_MVC;
382 MS_BOOL bCap_Support_VP8;
383 MS_BOOL bCap_Support_VP9;
384 MS_BOOL bCap_Support_HEVC;
385
386 /*New HW Cap and Feature add in struct at the end*/
387 }VDEC_HwCap;
388
389 //-------------------------------------------------------------------------------------------------
390 // Local Functions Prototype
391 //-------------------------------------------------------------------------------------------------
392 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
393 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
394 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
395
396 //-------------------------------------------------------------------------------------------------
397 // Global Variables
398 //-------------------------------------------------------------------------------------------------
399 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
400 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
401 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
402 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
403 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
404 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
405 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
406 #if SUPPORT_G2VP9 && defined(VDEC3)
407 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
408 #endif
409 #if defined (__aeon__)
410 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
411 #else
412 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
413 #endif
414
415 //-------------------------------------------------------------------------------------------------
416 // Local Variables
417 //-------------------------------------------------------------------------------------------------
418 #if 0
419
420 static MS_BOOL _bVPUPowered = FALSE;
421 static MS_BOOL _bVPURsted = FALSE;
422 static MS_BOOL _bVPUSingleMode = FALSE;
423 static VPU_EX_DecModCfg _stVPUDecMode;
424
425 static MS_U8 u8TaskCnt = 0;
426
427 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
428
429 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
430 static VPU_EX_Stream _stVPUStream[] =
431 {
432 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
433 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
434 };
435 static VPU_HWInitFunc stHWInitFunc =
436 {
437 &HAL_MVD_InitHW,
438 &HAL_MVD_DeinitHW,
439 &HAL_HVD_EX_InitHW,
440 &HAL_HVD_EX_DeinitHW,
441 };
442
443 #endif
444
445 #if VPU_ENABLE_EMBEDDED_FW_BINARY
446 static const MS_U8 u8HVD_FW_Binary[] = {
447 #include "fwVPU.dat"
448 };
449
450 #if HVD_ENABLE_RV_FEATURE
451 static const MS_U8 u8HVD_VLC_Binary[] = {
452 #include "fwVPU_VLC.dat"
453 };
454 #endif
455 #endif
456
457
458 #ifdef VDEC3
459 typedef struct
460 {
461 MS_BOOL bTSP;
462 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
463 MS_U32 u32Used;
464 } BBU_STATE;
465
466 typedef struct
467 {
468 MS_BOOL bTSP;
469 MS_BOOL bUsedbyMVD;
470 MS_U32 u32Used;
471 } SLQ_STATE;
472 #endif
473
474 typedef struct
475 {
476 MS_BOOL _bVPUPowered;
477 MS_BOOL _bVPURsted;
478 MS_BOOL _bVPUSingleMode;
479 VPU_EX_DecModCfg _stVPUDecMode;
480 MS_U8 u8TaskCnt;
481 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
482 #ifdef VDEC3
483 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
484 #else
485 VPU_EX_Stream _stVPUStream[2];
486 #endif
487
488 VPU_HWInitFunc stHWInitFunc;
489
490 MS_BOOL bVpuExReloadFW;
491 MS_BOOL bVpuExLoadFWRlt;
492 MS_VIRT u32VPUSHMAddr; //PA
493 MS_BOOL bEnableVPUSecureMode;
494
495 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
496 MS_BOOL bEnableDymanicFBMode;
497 MS_PHY u32DynamicFBAddress;
498 MS_U32 u32DynamicFBSize;
499 #ifdef VDEC3
500 MS_VIRT u32FWCodeAddr;
501 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
502
503 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
504 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
505 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
506
507 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
508 #endif
509 MS_U8 u8ForceRst;
510 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
511 } VPU_Hal_CTX;
512
513 //global variables
514 VPU_Hal_CTX* pVPUHalContext = NULL;
515 VPU_Hal_CTX gVPUHalContext;
516 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
517 MS_BOOL bVPUMbxInitFlag = 0;
518 MS_U8 u8VPUMbxMsgClass = 0;
519 MBX_Msg VPUReeToTeeMbxMsg;
520 MBX_Msg VPUTeeToReeMbxMsg;
521
522 //-------------------------------------------------------------------------------------------------
523 // Debug Functions
524 //-------------------------------------------------------------------------------------------------
525
526
527 //-------------------------------------------------------------------------------------------------
528 // Local Functions
529 //-------------------------------------------------------------------------------------------------
530
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)531 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
532 {
533 #if HVD_ENABLE_RV_FEATURE
534 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
535 {
536 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
537 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
538 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
539
540 if (pVlcCfg->u32BinSize)
541 {
542 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
543
544 MS_U32 u32Start;
545 MS_U32 u32StartOffset;
546 MS_U8 u8MiuSel;
547
548 // Get MIU selection and offset from physical address = 0x30000000
549 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
550
551
552 if(u8MiuSel == E_CHIP_MIU_0)
553 cpyflag = E_SPIDMA_DEV_MIU0;
554 else if(u8MiuSel == E_CHIP_MIU_1)
555 cpyflag = E_SPIDMA_DEV_MIU1;
556 else if(u8MiuSel == E_CHIP_MIU_2)
557 cpyflag = E_SPIDMA_DEV_MIU2;
558
559 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
560 {
561 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
562 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
563
564 return FALSE;
565 }
566 }
567 else
568 {
569 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
570 return FALSE;
571 }
572 #else
573 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
574 return FALSE;
575 #endif
576 }
577 else
578 {
579 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
580 {
581 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
582 {
583 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
584 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
585
586 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
587 BDMA_Result bdmaRlt;
588 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
589
590 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
591 u32SrcAdd = pVlcCfg->u32BinAddr;
592 u32tabsize = pVlcCfg->u32BinSize;
593 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
594 MsOS_FlushMemory();
595 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
596
597 if (E_BDMA_OK != bdmaRlt)
598 {
599 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
600 }
601 #else
602 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
603 #endif
604 }
605 else
606 {
607 VPU_MSG_ERR
608 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
609 return FALSE;
610 }
611 }
612 else
613 {
614 #if VPU_ENABLE_EMBEDDED_FW_BINARY
615 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
616 MS_U8 *pu8HVD_VLC_Binary;
617
618 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
619
620 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
621 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
622 (MS_U32) sizeof(u8HVD_VLC_Binary));
623
624 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
625 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
626 #else
627 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
628 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
629 (MS_U32) sizeof(u8HVD_VLC_Binary));
630
631 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
632 #endif
633 #else
634 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
635 return FALSE;
636 #endif
637 }
638 }
639 #endif
640
641 return TRUE;
642 }
643
644 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)645 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
646 {
647 MS_U8 u8OffsetIdx = 0;
648 MS_U8 u8VSidBaseMask = 0xF0;
649 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
650
651 switch (eVSidBase)
652 {
653 case E_HAL_VPU_MAIN_STREAM_BASE:
654 {
655 u8OffsetIdx = 0;
656 break;
657 }
658 case E_HAL_VPU_SUB_STREAM_BASE:
659 {
660 u8OffsetIdx = 1;
661 break;
662 }
663 case E_HAL_VPU_MVC_STREAM_BASE:
664 {
665 u8OffsetIdx = 0;
666 break;
667 }
668 #ifdef VDEC3
669 case E_HAL_VPU_N_STREAM_BASE:
670 {
671 u8OffsetIdx = u32Id & 0x0F;
672 break;
673 }
674 #endif
675 default:
676 {
677 u8OffsetIdx = 0;
678 break;
679 }
680 }
681
682 /*
683 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
684 u32Id, eVSidBase, u8OffsetIdx);
685 */
686 return u8OffsetIdx;
687 }
688
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)689 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
690 {
691 return _VPU_EX_GetOffsetIdx(u32Id);
692 }
693
_VPU_EX_Context_Init(void)694 static void _VPU_EX_Context_Init(void)
695 {
696 #ifdef VDEC3
697 MS_U8 i;
698
699 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
700 {
701 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
702 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
703 }
704
705 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
706 {
707 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
708 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
709 }
710
711 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
712 {
713 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
714 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
715 }
716
717 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
718 {
719 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
720 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
721 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
722 }
723 #else
724 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
725 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
726 #endif
727 pVPUHalContext->bVpuExReloadFW = TRUE;
728 pVPUHalContext->u8ForceRst = 0;
729 }
730
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)731 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
732 {
733 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
734 MS_U8 u8OffsetIdx = 0;
735
736 if (NULL == pTaskInfo)
737 {
738 return eCmd;
739 }
740
741 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
742
743 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
744 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
745
746 #ifdef VDEC3
747 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
748 {
749 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
750 {
751 eCmd = E_NST_CMD_TASK_MVD_TSP;
752 }
753 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
754 {
755 eCmd = E_NST_CMD_TASK_MVD_SLQ;
756 }
757 }
758 #else
759 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
760 {
761 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
762 {
763 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
764 }
765 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
766 {
767 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
768 }
769 }
770 #endif
771 #ifdef VDEC3
772 #if SUPPORT_G2VP9
773 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
774 #else
775 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
776 #endif
777 {
778 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
779 {
780 eCmd = E_NST_CMD_TASK_HVD_TSP;
781 }
782 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
783 {
784 eCmd = E_NST_CMD_TASK_HVD_BBU;
785 }
786 }
787 #else
788 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
789 {
790 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
791 {
792 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
793 }
794 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
795 {
796 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
797 }
798 }
799 #endif
800
801 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
802 return eCmd;
803 }
804
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)805 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
806 {
807 if (!pTaskInfo)
808 {
809 VPU_MSG_ERR("null input\n");
810 return FALSE;
811 }
812
813 //Check if we need to init MVD HW
814 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
815 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
816 {
817 //Init HW
818 if (FALSE == HAL_VPU_EX_MVDInUsed())
819 {
820 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
821 {
822 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
823 return FALSE;
824 }
825 }
826 else
827 {
828 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
829 }
830 }
831
832 #if 0 // k6 is wbmvop, no need to open hvd clock for sub diu interface
833 //MVD use sub mvop
834 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
835 #ifdef VDEC3
836 (pTaskInfo->u8HalId == 1) )
837 #else
838 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
839 #endif
840 {
841 VPU_MSG_ERR("Force turn on HVD\n");
842 if(!HAL_VPU_EX_HVDInUsed())
843 {
844 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
845 {
846 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
847 {
848 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
849 return FALSE;
850 }
851 }
852 else
853 {
854 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
855 #ifdef CONFIG_MSTAR_CLKM
856 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
857 #else
858 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
859 #endif
860 }
861 }
862 else
863 {
864 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
865 }
866 }
867 #endif
868
869 //Check if we need to init HVD HW
870 #ifdef VDEC3
871 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
872 #else
873 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
874 #endif
875 {
876 if (!HAL_VPU_EX_MVDInUsed())
877 {
878 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
879 {
880 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
881 return FALSE;
882 }
883 }
884
885 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
886 {
887 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
888 return FALSE;
889 }
890 #if SUPPORT_MSVP9
891 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
892 {
893 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
894 }
895 #endif
896 }
897
898 #if SUPPORT_G2VP9 && defined(VDEC3)
899 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
900 {
901 if (!HAL_VPU_EX_MVDInUsed())
902 {
903 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
904 {
905 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
906 return FALSE;
907 }
908 }
909 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
910 {
911 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
912 return FALSE;
913 }
914 }
915 #endif
916
917 return TRUE;
918 }
919
_VPU_EX_InClock(MS_U32 u32type)920 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
921 {
922 switch (u32type)
923 {
924 case VPU_CLOCK_480MHZ:
925 return 480000000UL;
926 case VPU_CLOCK_432MHZ:
927 return 432000000UL;
928 case VPU_CLOCK_384MHZ:
929 return 384000000UL;
930 default:
931 return 480000000UL;
932 }
933 }
934
935
936 //#if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
937 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)938 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
939 {
940 //#ifndef MSOS_TYPE_LINUX_KERNEL
941 #if 1
942 MS_U8 ClassNum = 0;
943 MBX_Result result;
944
945 #if 0
946 if (bVPUMbxInitFlag == TRUE)
947 {
948 return TRUE;
949 }
950 #endif
951
952 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
953 {
954 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
955 return FALSE;
956 }
957 else
958 {
959 MApi_MBX_Enable(TRUE);
960 }
961
962 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
963
964 if (E_MBX_SUCCESS != result)
965 {
966 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
967 return FALSE;
968 }
969
970 result = MApi_MBX_RegisterMSG(ClassNum, 10);
971
972 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
973 {
974 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
975 return FALSE;
976 }
977 else
978 {
979 bVPUMbxInitFlag = TRUE;
980 u8VPUMbxMsgClass = ClassNum;
981 return TRUE;
982 }
983 #else
984 return FALSE;
985 #endif
986 }
987
988 //#ifdef MBX_2K
989 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)990 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
991 {
992 MBX_Result result;
993 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
994
995 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
996 {
997 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
998 }
999
1000 if (bVPUMbxInitFlag == FALSE)
1001 {
1002 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1003 }
1004
1005 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1006 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1007 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1008 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1009 VPUReeToTeeMbxMsg.u8Index = msg_type;
1010
1011 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1012 if (E_MBX_SUCCESS != result)
1013 {
1014 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1015 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1016 }
1017
1018 // Receive Reply ACK from TEE side.
1019 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1020
1021 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1022
1023 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1024 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1025 {
1026 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1027 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1028 }
1029 else
1030 #else
1031 do
1032 {
1033 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1034 } while(E_MBX_SUCCESS != result);
1035 #endif
1036 {
1037 u8Index = VPUTeeToReeMbxMsg.u8Index;
1038 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1039
1040 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1041 {
1042 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1043 }
1044 }
1045
1046 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1047 }
1048 #endif
1049
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1050 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1051 {
1052 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1053 {
1054 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1055 {
1056 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1057 return FALSE;
1058 }
1059 else
1060 {
1061 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1062 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1063 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1064 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1065 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1066 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1067 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1068 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1069
1070 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1071
1072
1073 MS_U32 u32Start;
1074
1075 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1076 {
1077 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1078 pVPUHalContext->u32VPUSHMAddr = u32Start;
1079 }
1080 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1081 {
1082 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1083 pVPUHalContext->u32VPUSHMAddr = u32Start;
1084
1085 }
1086 else // == 0
1087 {
1088 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1089 }
1090 }
1091 }
1092 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1093 {
1094 MS_U32 u32Offset;
1095 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1096 {
1097 u32Offset = u32SHMAddr-u32MIU1Addr;
1098 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1099 }
1100 else
1101 {
1102 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1103 }
1104 }
1105
1106 return TRUE;
1107 }
1108
1109
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1110 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1111 {
1112 bVPUMbxInitFlag = TRUE;
1113 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1114 return TRUE;
1115 }
1116
HAL_VPU_EX_ForceSwRst(void)1117 void HAL_VPU_EX_ForceSwRst(void)
1118 {
1119 pVPUHalContext->u8ForceRst = 1;
1120 }
1121
1122 //#endif
1123
HAL_VPU_EX_GetFWReload(void)1124 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1125 {
1126 return pVPUHalContext->bVpuExReloadFW;
1127 }
1128
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1129 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1130 {
1131 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1132 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1133 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1134 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1135 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1136 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1137 )
1138 {
1139 return FALSE;
1140 }
1141 else
1142 {
1143 return TRUE;
1144 }
1145 }
1146
_VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg * pFWCodeCfg)1147 static MS_BOOL _VPU_EX_InitAddressLimiter(VPU_EX_FWCodeCfg *pFWCodeCfg)
1148 {
1149
1150
1151 #if 1 // bypass mode for debug
1152
1153 // allow non-secure read access
1154 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1155 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_I_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR);
1156
1157 // allow non-secure write access
1158 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1159 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR);
1160
1161 #else
1162 MS_PHY u32fwPAStart = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1163 MS_PHY u32fwPAEnd = u32fwPAStart + pFWCodeCfg->u32DstSize;
1164 MS_PHY u32WriteReplaceAddr = u32fwPAStart + CTL_INFO_ADDR;
1165
1166 // 128 bits align
1167 if((u32fwPAStart & 0xF) || (u32fwPAEnd & 0xF) || (u32WriteReplaceAddr & 0xF))
1168 {
1169 VPU_MSG_ERR("[Error] address need 128 bits align\n");
1170 return FALSE;
1171 }
1172
1173 u32fwPAStart >>= 4;
1174 u32fwPAEnd >>= 4;
1175 u32WriteReplaceAddr >>= 4;
1176
1177 // configure 1st secure range start address
1178 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1179 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1180 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1181
1182 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAStart & 0xFFFF));
1183 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAStart >> 16));
1184 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1185
1186 // configure 1st secure range end address
1187 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1188 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1189 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1190
1191 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32fwPAEnd & 0xFFFF));
1192 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32fwPAEnd >> 16));
1193 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1194
1195 // configure replaced address
1196 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1197 _VPU_Write2Byte(REG_VDR2_D_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1198 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1199
1200 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_L, (MS_U16)(u32WriteReplaceAddr & 0xFFFF));
1201 _VPU_Write2Byte(REG_VDR2_I_ACCESS_RANGE_ADDR_H, (MS_U16)(u32WriteReplaceAddr >> 16));
1202 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_I_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK);
1203
1204 // Enable limit write access
1205 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1206
1207 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR, VDR2_I_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_ADDR);
1208
1209 // Enable 1st limit range
1210 _VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1211
1212 _VPU_WriteWordMask(REG_VDR2_I_ACCESS_RANGE0_CFG, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_I_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN);
1213
1214 // Enable One-way bit
1215 _VPU_WriteWordMask(REG_ONEWAY_B16, ONEWAY_B16, ONEWAY_B16);
1216 _VPU_WriteWordMask(REG_LOCK_ONEWAY_B16, LOCK_ONEWAY_B16, LOCK_ONEWAY_B16);
1217
1218 #endif
1219
1220 return TRUE;
1221 }
1222
1223
1224
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1225 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1226 {
1227 MS_PHY u32fwPA = NULL; //physical address
1228 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_480MHZ;
1229
1230 if (TRUE == HAL_VPU_EX_IsPowered())
1231 {
1232 VPU_MSG_DBG("IsPowered\n");
1233 return TRUE;
1234 }
1235 else
1236 {
1237 //VPU hold
1238 HAL_VPU_EX_SwRst(FALSE);
1239
1240 //VPU clock on
1241 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1242
1243 if (VPU_I_R_ON_MIU0)
1244 VPUInitParams.u8MiuSel = 0;
1245 else if (VPU_I_R_ON_MIU1)
1246 VPUInitParams.u8MiuSel = 1;
1247 // else if (VPU_I_R_ON_MIU2)
1248 // VPUInitParams.u8MiuSel = 2;
1249
1250 HAL_VPU_EX_Init(&VPUInitParams);
1251 }
1252
1253 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1254 VPU_EX_TaskInfo *pTaskInfo = NULL;
1255 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1256
1257 if (pInitPara)
1258 {
1259 pFWCodeCfg = pInitPara->pFWCodeCfg;
1260 pTaskInfo = pInitPara->pTaskInfo;
1261 pVlcCfg = pInitPara->pVLCCfg;
1262
1263 if(_VPU_EX_InitAddressLimiter(pFWCodeCfg) == FALSE)
1264 {
1265 VPU_MSG_ERR("(%d) InitAddressLimiter fail\n", __LINE__);
1266 return FALSE;
1267 }
1268 }
1269 else
1270 {
1271 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1272 return FALSE;
1273 }
1274
1275 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1276 //#ifdef MBX_2K
1277 #if 1
1278 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1279 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1280 {
1281 SYS_TEEINFO teemode;
1282 MDrv_SYS_ReadKernelCmdLine();
1283 MDrv_SYS_GetTEEInfo(&teemode);
1284 VPRINTF("[VDEC][TEE/OPTEE]%s,TEE_type=%d\n",__FUNCTION__,teemode.OsType);
1285 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1286 {
1287 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1288
1289 if (FALSE == HAL_VPU_EX_GetFWReload())
1290 {
1291 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1292 {
1293 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1294 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1295 {
1296 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1297 return FALSE;
1298 }
1299 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1300 }
1301 else
1302 {
1303 //Check f/w prefix "VDEC30"
1304 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1305 {
1306 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1307 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1308 {
1309 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1310 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1311 return FALSE;
1312 }
1313 }
1314 else
1315 {
1316 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1317 }
1318 }
1319 }
1320 else
1321 {
1322 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1323 {
1324 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1325 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1326 return FALSE;
1327 }
1328 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1329 }
1330 }
1331 }
1332 else
1333 #endif
1334 #endif
1335 {
1336 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1337
1338 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1339 {
1340 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1341 return FALSE;
1342 }
1343 }
1344
1345 if (pVlcCfg)
1346 {
1347 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1348 {
1349 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1350 return FALSE;
1351 }
1352 }
1353
1354 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1355 {
1356 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1357 return FALSE;
1358 }
1359
1360 //Init HW
1361 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1362 {
1363 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1364 //_MVD_INIT_FAIL_RET();
1365 return FALSE;
1366 }
1367 else
1368 {
1369 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1370 }
1371
1372 //set vpu clock to FW
1373 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1374 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1375
1376
1377 #if (VPU_ENABLE_IQMEM)
1378 ctl_ptr->bIQmemEnableIfSupport = TRUE;
1379 #endif
1380
1381 ctl_ptr->statue = CTL_STU_NONE;
1382 //notify controller the interface version of VPU driver.
1383 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1384 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1385 MsOS_FlushMemory();
1386 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1387
1388 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1389 if (TRUE == HAL_VPU_EX_IsRsted())
1390 {
1391 VPU_MSG_DBG("VPU_IsRsted\n");
1392 return TRUE;
1393 }
1394 else
1395 {
1396 HAL_VPU_EX_SwRstRelse();
1397 }
1398
1399 return TRUE;
1400 }
1401
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1402 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1403 {
1404 MS_BOOL bRet = FALSE;
1405
1406 #if defined(VDEC3)
1407 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1408 #else
1409 MS_BOOL isEVD = FALSE ;
1410 #endif
1411 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1412 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1413 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1414
1415 if (FALSE == HAL_VPU_EX_MVDInUsed())
1416 {
1417 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1418 }
1419
1420 if (TRUE == isHVD)
1421 {
1422 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1423 }
1424
1425 #if defined(VDEC3)
1426 if (TRUE == isEVD)
1427 {
1428 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1429 }
1430 #endif
1431
1432 #if SUPPORT_G2VP9 && defined(VDEC3)
1433 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1434 {
1435 bRet = HAL_VP9_EX_DeinitHW();
1436 }
1437 #endif
1438 return bRet;
1439 }
1440
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1441 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1442 {
1443 HAL_VPU_EX_SwRst(TRUE);
1444 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1445 HAL_VPU_EX_DeInit();
1446
1447 return TRUE;
1448 }
1449
_VPU_EX_GetActiveCodecCnt(void)1450 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1451 {
1452 MS_U32 i;
1453 MS_U8 u8ActiveCnt = 0;
1454 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1455 {
1456 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1457 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1458 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1459 {
1460 u8ActiveCnt++;
1461 }
1462 }
1463 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1464 {
1465 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1466 }
1467 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1468 return u8ActiveCnt;
1469 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1470 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1471 {
1472 if (TRUE)
1473 {
1474 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1475 }
1476 else
1477 {
1478 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1479 }
1480 }
1481
_VPU_EX_ClockSpeed(MS_U32 u32type)1482 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1483 {
1484 switch (u32type)
1485 {
1486 case VPU_CLOCK_480MHZ:
1487 case VPU_CLOCK_432MHZ:
1488 case VPU_CLOCK_384MHZ:
1489 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1490 break;
1491 default:
1492 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_480MHZ, TOP_CKG_VPU_CLK_MASK);
1493 break;
1494 }
1495 }
1496 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1497 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1498 {
1499 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1500 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1501 {
1502 return TRUE;
1503 }
1504 return FALSE;
1505 }
1506 #endif
1507
1508
1509 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1510 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1511 {
1512 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1513 {
1514 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1515 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1516 ms_VDECDecompressDeInit();
1517 return TRUE;
1518 }
1519 else
1520 {
1521 return FALSE;
1522 }
1523 }
1524 #endif
1525
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1526 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1527 {
1528 MS_BOOL bRet = TRUE;
1529 pVPUHalContext->_bVPUSingleMode = bEnable;
1530 return bRet;
1531 }
1532
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1533 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1534 {
1535 MS_BOOL bRet = TRUE;
1536 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1537 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1538 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1539
1540 return bRet;
1541 }
1542
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1543 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1544 {
1545 MS_BOOL bRet = TRUE;
1546 MS_U8 i=0;
1547 if (pstCfg != NULL)
1548 {
1549 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1550 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1551 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1552 {
1553 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1554 }
1555 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1556 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1557 }
1558 else
1559 {
1560 bRet = FALSE;
1561 }
1562 return bRet;
1563 }
1564
1565 //static MS_BOOL bVpuExReloadFW = TRUE;
1566 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1567 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1568 {
1569 pVPUHalContext->bVpuExReloadFW = bReload;
1570 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1571 return TRUE;
1572 }
1573
1574
1575 //-------------------------------------------------------------------------------------------------
1576 // Global Functions
1577 //-------------------------------------------------------------------------------------------------
1578 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1579 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1580 {
1581 #if HVD_ENABLE_RV_FEATURE
1582 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1583 {
1584 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1585 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1586 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1587
1588 if (pVlcCfg->u32BinSize)
1589 {
1590 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1591
1592 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1593 {
1594 cpyflag = E_SPIDMA_DEV_MIU1;
1595 }
1596 else
1597 {
1598 cpyflag = E_SPIDMA_DEV_MIU0;
1599 }
1600
1601 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1602 {
1603 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1604 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1605
1606 return FALSE;
1607 }
1608 }
1609 else
1610 {
1611 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1612 return FALSE;
1613 }
1614 #else
1615 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1616 return FALSE;
1617 #endif
1618 }
1619 else
1620 {
1621 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1622 {
1623 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1624 {
1625 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1626 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1627
1628 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1629 BDMA_Result bdmaRlt;
1630
1631 MsOS_FlushMemory();
1632 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1633
1634 if (E_BDMA_OK != bdmaRlt)
1635 {
1636 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1637 }
1638 #else
1639 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1640 #endif
1641 }
1642 else
1643 {
1644 VPU_MSG_ERR
1645 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1646 return FALSE;
1647 }
1648 }
1649 else
1650 {
1651 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1652 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1653 MS_U8 *pu8HVD_VLC_Binary;
1654
1655 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1656
1657 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1658 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1659 (MS_U32) sizeof(u8HVD_VLC_Binary));
1660
1661 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1662 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1663 #else
1664 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1665 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1666 (MS_U32) sizeof(u8HVD_VLC_Binary));
1667
1668 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1669 #endif
1670 #else
1671 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1672 return FALSE;
1673 #endif
1674 }
1675 }
1676 #endif
1677
1678 return TRUE;
1679 }
1680 #endif
1681
1682
1683 #if (VPU_ENABLE_IQMEM)
HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara * pInitPara)1684 MS_BOOL HAL_VPU_EX_IQMem_Init(VPU_EX_NDecInitPara *pInitPara)
1685 {
1686
1687 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1688 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1689
1690
1691 MS_U32 u32Timeout = 20000;
1692
1693 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_NONE)
1694 {
1695
1696 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1697
1698
1699 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_LOADING;
1700
1701 while (u32Timeout)
1702 {
1703
1704 if (ctl_ptr->u8IQmemCtrl == E_CTL_IQMEM_INIT_LOADED)
1705 {
1706 break;
1707 }
1708 u32Timeout--;
1709 MsOS_DelayTaskUs(1000);
1710 }
1711
1712 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1713
1714
1715 ctl_ptr->u8IQmemCtrl = E_CTL_IQMEM_INIT_FINISH;
1716
1717 if (u32Timeout==0)
1718 {
1719 HVD_EX_MSG_ERR("Wait E_CTL_IQMEM_INIT_FINISH timeout !!\n");
1720 return FALSE;
1721 }
1722
1723 }
1724 return TRUE;
1725 }
1726
1727 #endif
1728
1729
1730
1731 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1732 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1733 #else
1734 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1735 #endif
1736 {
1737 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1738 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1739 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1740 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1741 MS_U32 u32Arg = 0xFFFFFFFF;
1742 MS_U32 u32Timeout = 0;
1743 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1744 MS_U32 u32CmdArg = 0;
1745 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1746 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1747
1748 _HAL_VPU_Entry();
1749 //Check FW buffer size
1750 if (1 == u8Offset)
1751 {
1752 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1753 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1754
1755 if (u32CurFWBuffSize < u32MinFWBuffSize)
1756 {
1757 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1758 _HAL_VPU_Release();
1759 return FALSE;
1760 }
1761 }
1762
1763 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1764 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1765 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1766 {
1767 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1768 }
1769 #ifdef VDEC3
1770 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1771 #endif
1772
1773 if (0 == pVPUHalContext->u8TaskCnt)
1774 {
1775 //No task is created, need to load f/w, etc.
1776 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1777
1778 if (!_VPU_EX_InitAll(pInitPara))
1779 {
1780 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1781 _HAL_VPU_Release();
1782 return FALSE;
1783 }
1784
1785 //Check if controller finish initialization: clear mailbox, etc.
1786 //Need to check it before sending any controller commands!
1787 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1788 while (CTL_STU_NONE == ctl_ptr->statue)
1789 {
1790 if (HVD_GetSysTime_ms() > u32Timeout)
1791 {
1792 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1793 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1794 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1795 MS_U32 t=0;
1796 for (t=0; t<30; t++)
1797 {
1798 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1799 }
1800 _HAL_VPU_Release();
1801 return FALSE;
1802 }
1803
1804 MsOS_ReadMemory();
1805 }
1806
1807 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1808 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1809
1810 }
1811 else
1812 {
1813 if (pVPUHalContext->_bVPUSingleMode)
1814 {
1815 //Show error message
1816 printf("This task will use dram instead of sram!!!\n");
1817 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1818 }
1819
1820 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1821 {
1822 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1823 _HAL_VPU_Release();
1824 return FALSE;
1825 }
1826 if (pInitPara->pVLCCfg)
1827 {
1828 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1829 {
1830 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1831 _HAL_VPU_Release();
1832 return FALSE;
1833 }
1834 }
1835 }
1836
1837
1838 #if (VPU_ENABLE_IQMEM)
1839
1840 if( ctl_ptr->bIsIQMEMSupport)
1841 {
1842
1843 HAL_VPU_EX_IQMem_Init(pInitPara);
1844 }
1845 else{
1846 VPU_MSG_ERR("not support IQMEM\n");
1847 }
1848
1849 #endif
1850
1851
1852 #ifdef VDEC3
1853 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1854 {
1855 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1856
1857 memset(pTemp4,0,sizeof(VDEC_VBBU));
1858
1859 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1860
1861 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1862
1863 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1864
1865 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1866
1867 memset(pTemp2,0,sizeof(CMD_QUEUE));
1868
1869 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1870
1871 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1872
1873 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1874
1875 memset(pTemp3,0,0x2000);
1876
1877 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1878
1879 memset((void*)pVersion,0,0x8);
1880
1881 *pVersion = 1; //0:diu, 1:wb
1882 }
1883
1884 #endif
1885
1886 #if 1 // For TEE
1887 #ifdef VDEC3
1888 #if SUPPORT_G2VP9
1889 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1890 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1891 #else
1892 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1893 #endif
1894 #else
1895 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1896 #endif
1897 {
1898 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1899
1900 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1901 {
1902 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1903 }
1904 else
1905 {
1906 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1907 }
1908
1909 MsOS_FlushMemory();
1910 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1911
1912 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1913 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1914 }
1915 #endif
1916
1917 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1918 {
1919 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1920 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1921
1922 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1923
1924 MsOS_FlushMemory();
1925 }
1926
1927 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1928 {
1929 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1930 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1931 {
1932 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1933 }
1934 }
1935
1936 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1937 {
1938 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1939 //arg=1 to get better performance for single task
1940 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1941 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1942 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1943 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1944 {
1945 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1946 }
1947 }
1948 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1949 {
1950 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1951 {
1952 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1953 {
1954 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1955 u32CmdArg = CTL_MODE_3DTV;
1956 break;
1957 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1958 u32CmdArg = CTL_MODE_3DTV_PROG;
1959 break;
1960 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1961 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1962 break;
1963 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1964 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1965 break;
1966 default:
1967 u32CmdArg = CTL_MODE_3DTV;
1968 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1969 break;
1970 }
1971 }
1972 else
1973 {
1974 u32CmdArg = CTL_MODE_3DWMV;
1975 }
1976 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1977 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1978 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1979 {
1980 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1981 }
1982 }
1983 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1984 {
1985 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1986 {
1987 u32CmdArg = CTL_MODE_ONE_STC;
1988 }
1989 else
1990 {
1991 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1992 }
1993 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1994 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1995 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1996 {
1997 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1998 }
1999 }
2000
2001 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
2002 #if defined(SUPPORT_NEW_MEM_LAYOUT)
2003 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2004 #ifdef VDEC3
2005 {
2006 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2007 }
2008 #else
2009 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2010 #endif
2011
2012 #ifdef VDEC3
2013 #if SUPPORT_G2VP9
2014 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2015 #else
2016 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2017 #endif
2018 {
2019 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2020 }
2021 #else
2022 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2023 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
2024 #endif
2025 else
2026 {
2027 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2028 _HAL_VPU_Release();
2029 return FALSE;
2030 }
2031 #else
2032 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
2033 #endif
2034
2035 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
2036 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
2037
2038 MsOS_ReadMemory();
2039 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2040 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2041
2042 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2043 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2044 {
2045 if (HVD_GetSysTime_ms() > u32Timeout)
2046 {
2047 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2048 MS_U32 t=0;
2049 for (t=0; t<30; t++)
2050 {
2051 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
2052 }
2053 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2054 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2055 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2056 _HAL_VPU_Release();
2057 return FALSE;
2058 //#endif
2059 }
2060
2061 MsOS_ReadMemory();
2062 }
2063
2064 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2065 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2066
2067 #ifdef VDEC3
2068 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2069 #else
2070 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2071 #endif
2072 {
2073 HAL_HVD_EX_SetNalTblAddr(u32Id);
2074 }
2075
2076 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2077 {
2078 eDecType = E_VPU_EX_DECODER_MVD;
2079 }
2080 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2081 {
2082 eDecType = E_VPU_EX_DECODER_HVD;
2083 }
2084 #ifdef VDEC3
2085 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2086 {
2087 eDecType = E_VPU_EX_DECODER_EVD;
2088 }
2089 #if SUPPORT_G2VP9
2090 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2091 {
2092 eDecType = E_VPU_EX_DECODER_G2VP9;
2093 }
2094 #endif
2095 #endif
2096 else
2097 {
2098 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2099 _HAL_VPU_Release();
2100 return FALSE;
2101 }
2102
2103 #ifdef VDEC3
2104 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
2105 {
2106 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2107 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2108 }
2109 #endif
2110
2111 if (pTaskInfo->eDecType != eDecType)
2112 {
2113 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2114 pTaskInfo->eDecType, eDecType);
2115 }
2116 goto _SAVE_DEC_TYPE;
2117
2118 _SAVE_DEC_TYPE:
2119 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2120 {
2121 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
2122 }
2123 else
2124 {
2125 VPU_MSG_ERR("Cannot save eDecType!!\n");
2126 }
2127
2128 (pVPUHalContext->u8TaskCnt)++;
2129 _HAL_VPU_Release();
2130 return TRUE;
2131 }
2132
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2133 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2134 {
2135 HVD_Return eRet;
2136 #ifdef VDEC3
2137 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2138 #else
2139 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2140 #endif
2141 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2142 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2143
2144 _HAL_VPU_Entry();
2145 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2146
2147 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2148 if(eRet != E_HVD_RETURN_SUCCESS)
2149 {
2150 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2151 }
2152
2153 {
2154 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2155 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2156 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2157
2158 MsOS_ReadMemory();
2159
2160 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2161 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2162
2163 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2164 {
2165 if (HVD_GetSysTime_ms() > u32Timeout)
2166 {
2167 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2168 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2169 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2170
2171 if(pVPUHalContext->u8TaskCnt == 1)
2172 {
2173 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2174 break;
2175 }
2176 else if(pVPUHalContext->u8TaskCnt == 2)
2177 {
2178 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2179 break;
2180 }
2181 else
2182 {
2183 VPU_MSG_ERR("Task number is not correct\n");
2184 _HAL_VPU_Release();
2185 return FALSE;
2186 }
2187 }
2188
2189 MsOS_ReadMemory();
2190 }
2191
2192 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2193 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2194 }
2195 #if SUPPORT_EVD
2196 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2197 {
2198 HAL_EVD_EX_ClearTSPInput(u32Id);
2199 }
2200 #endif
2201
2202 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2203 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2204 {
2205 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2206 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2207 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2208 }
2209
2210 if (pVPUHalContext->u8TaskCnt)
2211 {
2212 (pVPUHalContext->u8TaskCnt)--;
2213 }
2214 else
2215 {
2216 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2217 }
2218
2219 if (0 == pVPUHalContext->u8TaskCnt)
2220 {
2221 int i;
2222 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2223 _VPU_EX_DeinitAll(pInitPara);
2224 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2225 pVPUHalContext->u32VPUSHMAddr = 0;
2226
2227 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2228 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2229 }
2230 else
2231 {
2232 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2233 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2234 }
2235
2236 _HAL_VPU_Release();
2237 return TRUE;
2238 }
2239
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2240 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2241 {
2242 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2243 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2244 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2245 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2246 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2247 #endif
2248
2249 if (FALSE == HAL_VPU_EX_GetFWReload())
2250 {
2251 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2252 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2253 {
2254 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2255 }
2256 else
2257 {
2258 //Check f/w prefix "VDEC30"
2259 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2260 {
2261 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2262 }
2263 else
2264 {
2265 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2266 return TRUE;
2267 }
2268 }
2269 }
2270
2271 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2272 {
2273 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2274 if (u32Size != 0)
2275 {
2276 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2277
2278
2279 MS_U32 u32Start;
2280 MS_U32 u32StartOffset;
2281 MS_U8 u8MiuSel;
2282
2283 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2284
2285
2286 if(u8MiuSel == E_CHIP_MIU_0)
2287 cpyflag = E_SPIDMA_DEV_MIU0;
2288 else if(u8MiuSel == E_CHIP_MIU_1)
2289 cpyflag = E_SPIDMA_DEV_MIU1;
2290 else if(u8MiuSel == E_CHIP_MIU_2)
2291 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2292
2293 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2294 {
2295 goto _load_code_fail;
2296 }
2297 }
2298 else
2299 {
2300 goto _load_code_fail;
2301 }
2302 #else
2303 goto _load_code_fail;
2304 #endif
2305 }
2306 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2307 {
2308 if (u32BinAddr != 0 && u32Size != 0)
2309 {
2310 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2311 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2312 {
2313 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2314 {
2315 VPU_MSG_INFO("Decompress ok!!!\n");
2316 }
2317 else
2318 {
2319 VPU_MSG_INFO("Decompress fail!!!\n");
2320 }
2321 }
2322 else
2323 #endif
2324 {
2325 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2326 }
2327 }
2328 else
2329 {
2330 goto _load_code_fail;
2331 }
2332 }
2333 else
2334 {
2335 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2336 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2337 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2338 (MS_U32) sizeof(u8HVD_FW_Binary));
2339
2340 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2341 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2342 {
2343 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2344 {
2345 VPU_MSG_INFO("Decompress ok!!!\n");
2346 }
2347 else
2348 {
2349 VPU_MSG_INFO("Decompress fail!!!\n");
2350 }
2351 }
2352 else
2353 #endif
2354 {
2355 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2356 }
2357 #else
2358 goto _load_code_fail;
2359 #endif
2360 }
2361
2362 MAsm_CPU_Sync();
2363 MsOS_FlushMemory();
2364
2365 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2366 {
2367 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2368 goto _load_code_fail;
2369 }
2370
2371 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2372 return TRUE;
2373
2374 _load_code_fail:
2375 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2376 return FALSE;
2377 }
2378
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2379 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2380 {
2381 u32VPURegOSBase = u32RegBase;
2382 }
2383
HAL_VPU_EX_Init_Share_Mem(void)2384 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2385 {
2386 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2387
2388 MS_U32 u32ShmId;
2389 MS_VIRT u32Addr;
2390 MS_U32 u32BufSize;
2391
2392
2393 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2394 sizeof(VPU_Hal_CTX),
2395 &u32ShmId,
2396 &u32Addr,
2397 &u32BufSize,
2398 MSOS_SHM_QUERY))
2399 {
2400 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2401 sizeof(VPU_Hal_CTX),
2402 &u32ShmId,
2403 &u32Addr,
2404 &u32BufSize,
2405 MSOS_SHM_CREATE))
2406 {
2407 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2408 if(pVPUHalContext == NULL)
2409 {
2410 pVPUHalContext = &gVPUHalContext;
2411 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2412 _VPU_EX_Context_Init();
2413 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2414 }
2415 else
2416 {
2417 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2418 }
2419 //return FALSE;
2420 }
2421 else
2422 {
2423 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2424 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2425 _VPU_EX_Context_Init();
2426 }
2427 }
2428 else
2429 {
2430 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2431 }
2432 #else
2433 if(pVPUHalContext == NULL)
2434 {
2435 pVPUHalContext = &gVPUHalContext;
2436 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2437 _VPU_EX_Context_Init();
2438 }
2439 #endif
2440
2441 return TRUE;
2442
2443 }
2444
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2445 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2446 {
2447 MS_U32 i = 0;
2448
2449 _HAL_VPU_MutexCreate();
2450
2451 _HAL_VPU_Entry();
2452
2453 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2454 {
2455 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2456 {
2457 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2458 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2459 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2460 _HAL_VPU_Release();
2461 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2462 }
2463 }
2464 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2465 {
2466 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2467 {
2468 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2469 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2470 {
2471 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2472 _HAL_VPU_Release();
2473 return pVPUHalContext->_stVPUStream[i].eStreamId;
2474 }
2475 }
2476 }
2477 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2478 {
2479 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2480 {
2481 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2482 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2483 {
2484 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2485 _HAL_VPU_Release();
2486 return pVPUHalContext->_stVPUStream[i].eStreamId;
2487 }
2488 }
2489 }
2490 #ifdef VDEC3
2491 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2492 {
2493 #if 1 // bound FW task to main/sub stream
2494 i = eStreamType - E_HAL_VPU_N_STREAM;
2495 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2496 {
2497 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2498 _HAL_VPU_Release();
2499 return pVPUHalContext->_stVPUStream[i].eStreamId;
2500 }
2501 #else // dynamic select FW task id
2502 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2503 {
2504 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2505 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2506 {
2507 return pVPUHalContext->_stVPUStream[i].eStreamId;
2508 }
2509 }
2510 #endif
2511 }
2512 #endif
2513
2514 _HAL_VPU_Release();
2515
2516 return E_HAL_VPU_STREAM_NONE;
2517 }
2518
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2519 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2520 {
2521 _HAL_VPU_Entry();
2522
2523 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2524 {
2525 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2526 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2527 }
2528 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2529 {
2530 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2531 }
2532
2533 _HAL_VPU_Release();
2534
2535 return TRUE;
2536 }
2537
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2538 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2539 {
2540 MS_U8 u8Idx = 0;
2541
2542 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2543
2544 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2545 {
2546 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2547 {
2548 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2549 return 0;
2550 }
2551 }
2552 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2553 {
2554 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2555 {
2556 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2557 return 1;
2558 }
2559 }
2560
2561 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2562 {
2563 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2564 break;
2565 }
2566
2567 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2568 {
2569 VPU_MSG_ERR("all vpu free streams are occupied \n");
2570 return -1;
2571 }
2572
2573 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2574 return u8Idx;
2575 }
2576
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2577 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2578 {
2579 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2580
2581 // enable module
2582 _VPU_EX_ClockInv(InitParams->bClockInv);
2583 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2584 HAL_VPU_EX_PowerCtrl(TRUE);
2585
2586 #ifdef CONFIG_MSTAR_CLKM
2587 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2588 #endif
2589
2590 #ifdef CONFIG_MSTAR_SRAMPD
2591 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2592 HVD_Delay_ms(1);
2593 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2594 HVD_Delay_ms(1);
2595 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2596 HVD_Delay_ms(1);
2597 #endif
2598 #if 1 //Create VPU's own mutex
2599 //_HAL_VPU_MutexCreate();
2600 #else
2601 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2602 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2603 #endif
2604
2605 return TRUE;
2606 }
2607
HAL_VPU_EX_DeInit(void)2608 MS_BOOL HAL_VPU_EX_DeInit(void)
2609 {
2610 if (0 != _VPU_EX_GetActiveCodecCnt())
2611 {
2612 VPU_MSG_DBG("do nothing since codec is active.\n");
2613 return TRUE;
2614 }
2615
2616 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2617
2618 #ifdef CONFIG_MSTAR_CLKM
2619 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2620 #else
2621 HAL_VPU_EX_PowerCtrl(FALSE);
2622 #endif
2623
2624 #ifdef CONFIG_MSTAR_SRAMPD
2625 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2626 HVD_Delay_ms(1);
2627 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2628 HVD_Delay_ms(1);
2629 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2630 HVD_Delay_ms(1);
2631 #endif
2632
2633 HAL_VPU_EX_SwRelseMAU();
2634 //_HAL_VPU_MutexDelete();
2635
2636 return TRUE;
2637 }
2638
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2639 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2640 {
2641 if (bEnable)
2642 {
2643 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2644 _VPU_WriteWordMask(REG_TOP_VPU, VPU_ICG_EN, VPU_ICG_EN);
2645 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2646 pVPUHalContext->_bVPUPowered = TRUE;
2647 }
2648 else
2649 {
2650 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2651 //_VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2652 pVPUHalContext->_bVPUPowered = FALSE;
2653 }
2654 }
2655
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2656 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2657 {
2658 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2659 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2660 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2661 VPU_EX_TimerDelayMS(1);
2662 }
2663
2664 ///-----------------------------------------------------------------------------
2665 /// config AVCH264 CPU
2666 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2667 /// @param u8dlend_en \b IN: endian
2668 /// - 1, little endian
2669 /// - 0, big endian
2670 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2671 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2672 {
2673 MS_BOOL bRet = TRUE;
2674 MS_U32 u32Offset = 0;
2675 MS_U16 tempreg = 0;
2676 MS_U8 u8MiuSel;
2677 //MS_U32 u32TmpStartOffset;
2678
2679 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2680
2681 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2682 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2683 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2684 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2685 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2686 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2687 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2688 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2689 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2690 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2691
2692 #if (VPU_ENABLE_IQMEM)
2693 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2694 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2695 #endif
2696
2697 #if (VPU_FORCE_MIU_MODE)
2698 // Data sram base Unit: byte address
2699 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2700 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2701 // Instruction sram base Unit: byte address
2702 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2703 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2704
2705 #ifndef HAL_FEATURE_MAU
2706 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2707 #endif
2708 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2709
2710 //use force miu mode
2711 if(u8MiuSel == E_CHIP_MIU_0)
2712 {
2713 #ifdef HAL_FEATURE_MAU
2714 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2715 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2716 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2717 #else
2718 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2719 #endif
2720 }
2721 else if(u8MiuSel == E_CHIP_MIU_1)
2722 {
2723 #ifdef HAL_FEATURE_MAU
2724 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2725 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2726 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2727 #else
2728 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2729 #endif
2730 }
2731 else //miu 2
2732 {
2733 #ifdef HAL_FEATURE_MAU
2734 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2735 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2736 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2737 #else
2738 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2739 #endif
2740 }
2741 #else
2742 ///TODO:
2743 #endif
2744
2745
2746 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2747 tempreg |= VPU_REG_IO2_EN;
2748 tempreg |= VPU_REG_QMEM_SPACE_EN;
2749 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2750
2751 return bRet;
2752 }
2753
2754 ///-----------------------------------------------------------------------------
2755 /// Set IQMem data access mode or instruction fetch mode
2756 /// @param u8dlend_en \b IN: endian
2757 /// - 1, switch to data access mode
2758 /// - 0, switch to instruction fetch mode
2759 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2760 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2761 {
2762
2763 if(bEnable){
2764
2765 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2766 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)|0x20);
2767
2768 }
2769 else{
2770
2771 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& (~0x10));
2772 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)& (~0x20));
2773 }
2774 }
2775
2776 ///-----------------------------------------------------------------------------
2777 /// H.264 SW reset
2778 /// @return TRUE or FALSE
2779 /// - TRUE, Success
2780 /// - FALSE, Failed
2781 ///-----------------------------------------------------------------------------
2782
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2783 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2784 {
2785 MS_U16 tempreg = 0, tempreg1 = 0;
2786 MS_U16 idle_cnt;
2787 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2788 tempreg |= VPU_REG_CPU_STALL_EN;
2789 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2790
2791 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2792 // 0xf means VPU is not stalled
2793 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2794 pVPUHalContext->u8ForceRst = 0;
2795 // write R2 RIU registers to select DCU/ICU debug data
2796 // Writing these registers here provides enough time for them to
2797 // take effect.
2798 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2799 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2800 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2801 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2802
2803 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2804 // This step is important because in the next step we want to make
2805 // sure "DCU is not replaying when R2 is stalled".
2806 idle_cnt = 100;
2807 do
2808 {
2809 if (--idle_cnt == 0)
2810 {
2811 printf("VPU_REG_CPU_STALL_EN is not set\n");
2812 break;
2813 }
2814 MsOS_DelayTask(1);
2815 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2816 // check CPU status: DCU should NOT be replaying
2817 // If R2 has been stalled, we can guarantee that if we found DCU is
2818 // NOT replaying, it will NOT replay later even CPU is going to issue
2819 // a load/store instruction.
2820 idle_cnt = 100;
2821 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2822 {
2823 if (--idle_cnt == 0)
2824 {
2825 printf("DCU is replaying\n");
2826 break;
2827 }
2828 MsOS_DelayTask(1);
2829 }
2830 // wait 1ms to prevent race condition between (1) DCU is not
2831 // replaying, and (2) BIU start to doing new job or ICU start to
2832 // fetch new instruction
2833 MsOS_DelayTask(1);
2834
2835 // check BIU should be empty
2836 idle_cnt = 100;
2837 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2838 {
2839 if (--idle_cnt == 0)
2840 {
2841 printf("BIU DCU idle time out~~~~~\n");
2842 break;
2843 }
2844 MsOS_DelayTask(1);
2845 }
2846
2847 // check CPU is not requesting ICU
2848 idle_cnt = 100;
2849 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2850 {
2851 if (--idle_cnt == 0)
2852 {
2853 printf("CPU keeps requesting ICU\n");
2854 break;
2855 }
2856 MsOS_DelayTask(1);
2857 }
2858
2859 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2860 // (2) ISB start to fetch
2861 MsOS_DelayTask(1);
2862
2863 // check ISB should be idle
2864 idle_cnt = 100;
2865 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2866 {
2867 if (--idle_cnt == 0)
2868 {
2869 printf("ISB is busy\n");
2870 break;
2871 }
2872 MsOS_DelayTask(1);
2873 }
2874 }
2875 #ifdef HAL_FEATURE_MAU
2876 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2877 if (bCheckMauIdle)
2878 {
2879 MS_U32 mau_idle_cnt = 100;// ms
2880 while (mau_idle_cnt)
2881 {
2882 if (TRUE == _VPU_EX_MAU_IDLE())
2883 {
2884 break;
2885 }
2886 mau_idle_cnt--;
2887 MsOS_DelayTask(1);
2888 }
2889
2890 if (mau_idle_cnt == 0)
2891 {
2892 printf("MAU idle time out~~~~~\n");
2893 }
2894 }
2895 #endif
2896
2897 // this command set MIU to block R2 (does not ack R2's request)
2898 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2899
2900 #ifdef HAL_FEATURE_MAU
2901 // reset MAU
2902 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2903 tempreg1 |= MAU1_REG_SW_RESET;
2904 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2905 #if defined(UDMA_FPGA_ENVI)
2906 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2907 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2908 #endif
2909 #endif
2910
2911 // reset R2
2912 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2913 // by the same RIU write, the R2 reset signal may reach afifo eralier
2914 // than MIU reset and afifo write pointer will be reset to position 0.
2915 // In this case, afifo consider it is not empty because read/write
2916 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2917 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2918 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2919 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2920 VPU_EX_TimerDelayMS(1);
2921 tempreg &= ~VPU_REG_CPU_R2_EN;
2922 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2923 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2924
2925 VPU_EX_TimerDelayMS(1);
2926
2927 // this command set MIU to accept R2 (can ack R2's request)
2928 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2929
2930 pVPUHalContext->_bVPURsted = FALSE;
2931 return TRUE;
2932 }
2933
2934 /*
2935 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2936 {
2937 MS_U16 tempreg = 0, tempreg1 = 0;
2938 #ifndef HAL_FEATURE_MAU
2939 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2940 tempreg |= VPU_REG_CPU_STALL_EN;
2941 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2942
2943 MS_U32 idle_cnt = 100;// ms
2944 while (idle_cnt)
2945 {
2946 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2947 {
2948 break;
2949 }
2950 idle_cnt--;
2951 MsOS_DelayTask(1);
2952 }
2953
2954 if (idle_cnt == 0)
2955 {
2956 printf("ISB ICU idle time out~~~~~\n");
2957 }
2958
2959 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2960 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2961 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2962 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2963
2964 MS_U32 idle_cnt_1 = 100;// ms
2965 while (idle_cnt_1)
2966 {
2967 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2968 {
2969 break;
2970 }
2971 idle_cnt_1--;
2972 MsOS_DelayTask(1);
2973 }
2974
2975 if (idle_cnt_1 == 0)
2976 {
2977 printf("BIU DCU idle time out~~~~~\n");
2978 }
2979
2980 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2981 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2982 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2983 VPU_EX_TimerDelayMS(1);
2984 tempreg &= ~VPU_REG_CPU_R2_EN;
2985 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2986 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2987
2988 #else
2989 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2990
2991 if (bCheckMauIdle)
2992 {
2993 MS_U32 mau_idle_cnt = 100;// ms
2994 while (mau_idle_cnt)
2995 {
2996 if (TRUE == _VPU_EX_MAU_IDLE())
2997 {
2998 break;
2999 }
3000 mau_idle_cnt--;
3001 MsOS_DelayTask(1);
3002 }
3003
3004 if (mau_idle_cnt == 0)
3005 {
3006 printf("MAU idle time out~~~~~\n");
3007 }
3008 }
3009
3010
3011 HAL_VPU_EX_MIU_RW_Protect(TRUE);
3012
3013 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3014 tempreg1 |= MAU1_REG_SW_RESET;
3015 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3016
3017 #if defined(UDMA_FPGA_ENVI)
3018 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3019 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3020 #endif
3021
3022 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3023 tempreg &= ~VPU_REG_CPU_R2_EN;
3024 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3025 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3026 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3027 #endif
3028 VPU_EX_TimerDelayMS(1);
3029 HAL_VPU_EX_MIU_RW_Protect(FALSE);
3030
3031 pVPUHalContext->_bVPURsted = FALSE;
3032 return TRUE;
3033 }
3034 */
3035 ///-----------------------------------------------------------------------------
3036 /// CPU reset release
3037 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)3038 void HAL_VPU_EX_SwRstRelse(void)
3039 {
3040 MS_U16 tempreg = 0;
3041
3042 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
3043 tempreg &= ~VPU_REG_CPU_STALL_EN;
3044 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
3045
3046 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
3047 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3048 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3049 VPU_EX_TimerDelayMS(1);
3050 tempreg |= VPU_REG_CPU_SW_RSTZ;
3051 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3052 VPU_EX_TimerDelayMS(1);
3053 tempreg |= VPU_REG_CPU_R2_EN;
3054 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
3055 #ifdef HAL_FEATURE_MAU
3056 MS_U16 tempreg1 = 0;
3057 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
3058 tempreg1 &= ~MAU1_REG_SW_RESET;
3059 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
3060 #endif
3061 pVPUHalContext->_bVPURsted = TRUE;
3062 }
3063
HAL_VPU_EX_SwRelseMAU(void)3064 void HAL_VPU_EX_SwRelseMAU(void)
3065 {
3066
3067 #ifdef HAL_FEATURE_MAU
3068 MS_U16 tempreg = 0;
3069 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
3070 tempreg &= ~MAU1_REG_SW_RESET;
3071 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
3072 #endif
3073 }
3074
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3075 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3076 {
3077 MS_U32 u32value = 0;
3078
3079 return u32value;
3080 }
3081
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3082 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3083 {
3084 MS_BOOL bRet = TRUE;
3085
3086 return bRet;
3087 }
3088
3089 ///-----------------------------------------------------------------------------
3090 /// Check AVCH264 Ready or not
3091 /// @return TRUE or FALSE
3092 /// - TRUE, MailBox is free
3093 /// - FALSE, MailBox is busy
3094 /// @param u8MBox \b IN: MailBox to check
3095 /// - AVCH264_HI_MBOX0,
3096 /// - AVCH264_HI_MBOX1,
3097 /// - AVCH264_RISC_MBOX0,
3098 /// - AVCH264_RISC_MBOX1,
3099 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)3100 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
3101 {
3102 MS_BOOL bResult = FALSE;
3103
3104 switch (u32type)
3105 {
3106 case VPU_HI_MBOX0:
3107 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3108 break;
3109 case VPU_HI_MBOX1:
3110 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3111 break;
3112 case VPU_RISC_MBOX0:
3113 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3114 break;
3115 case VPU_RISC_MBOX1:
3116 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3117 break;
3118 default:
3119 break;
3120 }
3121 return bResult;
3122 }
3123
3124
3125 ///-----------------------------------------------------------------------------
3126 /// Read message from AVCH264
3127 /// @return TRUE or FALSE
3128 /// - TRUE, success
3129 /// - FALSE, failed
3130 /// @param u8MBox \b IN: MailBox to read
3131 /// - AVCH264_RISC_MBOX0
3132 /// - AVCH264_RISC_MBOX1
3133 /// @param u32Msg \b OUT: message read
3134 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)3135 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
3136 {
3137 MS_BOOL bResult = TRUE;
3138
3139 switch (u32type)
3140 {
3141 case VPU_HI_MBOX0:
3142 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3143 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3144 break;
3145 case VPU_HI_MBOX1:
3146 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3147 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3148 break;
3149 case VPU_RISC_MBOX0:
3150 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3151 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3152 break;
3153 case VPU_RISC_MBOX1:
3154 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3155 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3156 break;
3157 default:
3158 *u32Msg = 0;
3159 bResult = FALSE;
3160 break;
3161 }
3162 return bResult;
3163 }
3164
3165 ///-----------------------------------------------------------------------------
3166 /// Mailbox from AVCH264 clear bit resest
3167 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3168 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3169 {
3170 switch (u32type)
3171 {
3172 case VPU_RISC_MBOX0:
3173 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3174 break;
3175 case VPU_RISC_MBOX1:
3176 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3177 break;
3178 default:
3179 break;
3180 }
3181 }
3182
3183 ///-----------------------------------------------------------------------------
3184 /// Send message to AVCH264
3185 /// @return TRUE or FALSE
3186 /// - TRUE, Success
3187 /// - FALSE, Failed
3188 /// @param u8MBox \b IN: MailBox
3189 /// - AVCH264_HI_MBOX0,
3190 /// - AVCH264_HI_MBOX1,
3191 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3192 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3193 {
3194 MS_BOOL bResult = TRUE;
3195
3196 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3197
3198 switch (u32type)
3199 {
3200 case VPU_HI_MBOX0:
3201 {
3202 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3203 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3204 break;
3205 }
3206 case VPU_HI_MBOX1:
3207 {
3208 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3209 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3210 break;
3211 }
3212 default:
3213 {
3214 bResult = FALSE;
3215 break;
3216 }
3217 }
3218
3219 return bResult;
3220 }
3221
HAL_VPU_EX_GetProgCnt(void)3222 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3223 {
3224
3225 MS_U16 expc_l=0;
3226 MS_U16 expc_h=0;
3227 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3228 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3229 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3230 }
3231
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3232 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3233 {
3234 return _VPU_EX_GetOffsetIdx(u32Id);
3235 }
3236
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3237 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3238 {
3239 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3240
3241 if (u32ShmAddr == 0)
3242 {
3243 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3244 }
3245 else
3246 {
3247 if (u8Offset == 0)
3248 {
3249 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3250 }
3251 else if (u8Offset == 1)
3252 {
3253 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3254 }
3255 }
3256
3257 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3258 return;
3259 }
3260
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3261 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3262 {
3263 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3264
3265 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3266 }
3267
3268 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3269 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3270 {
3271 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3272 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3273 MS_VIRT VsyncBridgeOffset = 0;
3274
3275 if (VPUSHMAddr != 0) // TEE project
3276 {
3277 if ((u8Offset == 0) || (u8Offset == 1))
3278 {
3279 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3280 }
3281 else
3282 {
3283 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3284 }
3285 }
3286 else // normal project
3287 {
3288 if ((u8Offset == 0) || (u8Offset == 1))
3289 {
3290 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3291 }
3292 else
3293 {
3294 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3295 }
3296 }
3297
3298 return VsyncBridgeOffset;
3299 }
3300
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3301 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3302 {
3303 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3304 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3305 MS_VIRT VsyncBridgeExtOffset = 0;
3306
3307 if (VPUSHMAddr != 0) // TEE project
3308 {
3309 if ((u8Offset == 0) || (u8Offset == 1))
3310 {
3311 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3312 }
3313 else
3314 {
3315 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3316 }
3317 }
3318 else // normal project
3319 {
3320 if ((u8Offset == 0) || (u8Offset == 1))
3321 {
3322 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3323 }
3324 else
3325 {
3326 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3327 }
3328 }
3329
3330 return VsyncBridgeExtOffset;
3331 }
3332 #endif
3333
HAL_VPU_EX_IsPowered(void)3334 MS_BOOL HAL_VPU_EX_IsPowered(void)
3335 {
3336 return pVPUHalContext->_bVPUPowered;
3337 }
3338
HAL_VPU_EX_IsRsted(void)3339 MS_BOOL HAL_VPU_EX_IsRsted(void)
3340 {
3341 return pVPUHalContext->_bVPURsted;
3342 }
3343
HAL_VPU_EX_IsEVDR2(void)3344 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3345 {
3346 #ifdef EVDR2
3347 return TRUE;
3348 #else
3349 return FALSE;
3350 #endif
3351 }
3352
HAL_VPU_EX_MVDInUsed(void)3353 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3354 {
3355 //MVD is in used for MVD or HVD_TSP mode.
3356 MS_U8 i;
3357 MS_U8 u8UseCnt = 0;
3358
3359 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3360 {
3361 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3362 #ifdef VDEC3
3363 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3364 #endif
3365 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3366 {
3367 u8UseCnt++;
3368 }
3369 }
3370
3371 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3372
3373 if (u8UseCnt != 0)
3374 {
3375 return TRUE;
3376 }
3377 else
3378 {
3379 return FALSE;
3380 }
3381 }
3382
HAL_VPU_EX_HVDInUsed(void)3383 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3384 {
3385 //HVD is in used for HVD or MVD in sub stream.
3386 MS_U8 i;
3387 MS_U8 u8UseCnt = 0;
3388 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3389 {
3390
3391 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype))
3392 {
3393 u8UseCnt++;
3394 }
3395 }
3396
3397 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3398
3399 if (u8UseCnt != 0)
3400 {
3401 return TRUE;
3402 }
3403 else
3404 {
3405 return FALSE;
3406 }
3407 }
3408
HAL_VPU_EX_Mutex_Lock(void)3409 void HAL_VPU_EX_Mutex_Lock(void)
3410 {
3411 _HAL_VPU_Entry();
3412 }
3413
HAL_VPU_EX_Mutex_UnLock(void)3414 void HAL_VPU_EX_Mutex_UnLock(void)
3415 {
3416 _HAL_VPU_Release();
3417 }
3418
3419 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3420 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3421 {
3422 MS_U8 i;
3423 MS_U8 u8UseCnt = 0;
3424
3425 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3426 {
3427 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3428 {
3429 u8UseCnt++;
3430 }
3431 }
3432
3433 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3434
3435 if (u8UseCnt != 0)
3436 {
3437 return TRUE;
3438 }
3439 else
3440 {
3441 return FALSE;
3442 }
3443 }
3444
3445 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3446 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3447 {
3448 MS_U8 i;
3449 MS_U8 u8UseCnt = 0;
3450
3451 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3452 {
3453 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3454 {
3455 u8UseCnt++;
3456 }
3457 }
3458
3459 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3460
3461 if (u8UseCnt != 0)
3462 {
3463 return TRUE;
3464 }
3465 else
3466 {
3467 return FALSE;
3468 }
3469 }
3470 #endif
3471 #endif
3472
3473 //-----------------------------------------------------------------------------
3474 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3475 /// @brief \b Function \b Description: Set debug level
3476 /// @param -elevel \b IN : debug level
3477 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3478 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3479 {
3480 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3481
3482 switch (eLevel)
3483 {
3484 case E_VPU_EX_UART_LEVEL_ERR:
3485 {
3486 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3487 break;
3488 }
3489 case E_VPU_EX_UART_LEVEL_INFO:
3490 {
3491 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3492 break;
3493 }
3494 case E_VPU_EX_UART_LEVEL_DBG:
3495 {
3496 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3497 break;
3498 }
3499 case E_VPU_EX_UART_LEVEL_TRACE:
3500 {
3501 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3502 break;
3503 }
3504 case E_VPU_EX_UART_LEVEL_FW:
3505 {
3506 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3507 break;
3508 }
3509 default:
3510 {
3511 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3512 break;
3513 }
3514 }
3515 }
3516
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3517 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3518 {
3519 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3520 MS_U32 u32CmdArg = (MS_U32)eVerType;
3521 MS_U32 u32Version = 0xFFFFFFFF;
3522 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3523 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3524 {
3525 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3526 return u32Version;
3527 }
3528
3529 MS_BOOL bRet = false;
3530 MS_U32 u32TimeOut = 0xFFFFFFFF;
3531
3532 while(--u32TimeOut)
3533 {
3534 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3535 {
3536 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3537 if (false == bRet)
3538 {
3539 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3540 return u32Version;
3541 }
3542
3543 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3544 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3545 return u32Version;
3546 }
3547 }
3548
3549 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3550
3551 return u32Version;
3552 }
3553
HAL_VPU_EX_NotSupportDS(void)3554 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3555 {
3556 return FALSE;// maserati disable SN DS
3557 }
3558
3559 //-----------------------------------------------------------------------------
3560 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3561 /// @brief \b Function \b Description: Get VPU MIU base address
3562 /// @return - vpu MIU1 base
3563 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3564 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3565 {
3566 return VPU_MIU1BASE_ADDR;
3567 }
3568
3569
HAL_VPU_EX_GetSHMAddr(void)3570 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3571 {
3572 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3573 {
3574 return 0;
3575 }
3576 return pVPUHalContext->u32VPUSHMAddr;
3577 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3578 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3579 {
3580 pVPUHalContext->bEnableVPUSecureMode = enable;
3581 return TRUE;
3582 }
3583
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3584 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3585 {
3586 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3587
3588 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3589 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3590 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3591 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3592 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3593 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3594 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3595 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3596
3597 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3598 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3599 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3600 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3601 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3602 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3603 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3604 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3605 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3606 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3607
3608 return TRUE;
3609 }
3610
3611 //-----------------------------------------------------------------------------
3612 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3613 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3614 /// @return - success/fail
3615 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3616 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3617 {
3618 #define MAX_CAPABILITY_INFO_NUM 8
3619 #define MAX_CODEC_TYPE_NUM 18
3620
3621 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3622 {
3623 //width, height , frmrate, profile, level, version bit rate reserved2
3624 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3625 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3626 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3627 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3628 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3629 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3630 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3631 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3632 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3633 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3634 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3635 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3636 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3637 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3638 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3639 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3640 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3641 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3642 };
3643
3644 if(eCodecType < MAX_CODEC_TYPE_NUM)
3645 {
3646 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3647 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3648 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3649 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3650 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3651 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3652 return TRUE;
3653 }
3654 else
3655 {
3656 return FALSE;
3657 }
3658 }
3659
3660 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3661 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3662 {
3663 (void) u32Id;
3664 BBU_STATE *bbu_state;
3665
3666 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3667 || (eDecType == E_VPU_EX_DECODER_VP8)
3668 #if SUPPORT_G2VP9
3669 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3670 #endif
3671 )
3672 {
3673 // MVD should not call this function.
3674 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3675 return;
3676 }
3677
3678 switch (eDecType)
3679 {
3680 case E_VPU_EX_DECODER_EVD:
3681 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3682 break;
3683 case E_VPU_EX_DECODER_HVD:
3684 case E_VPU_EX_DECODER_RVD:
3685 case E_VPU_EX_DECODER_MVC:
3686 default:
3687 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3688 break;
3689 }
3690
3691 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3692 return;
3693 }
3694
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3695 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3696 {
3697 (void) u32Id;
3698 BBU_STATE *bbu_state;
3699
3700 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3701 || (eDecType == E_VPU_EX_DECODER_VP8)
3702 #if SUPPORT_G2VP9
3703 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3704 #endif
3705 )
3706 {
3707 // MVD should not call this function.
3708 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3709 return TRUE;
3710 }
3711
3712 switch (eDecType)
3713 {
3714 case E_VPU_EX_DECODER_EVD:
3715 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3716 break;
3717 case E_VPU_EX_DECODER_HVD:
3718 case E_VPU_EX_DECODER_RVD:
3719 case E_VPU_EX_DECODER_MVC:
3720 default:
3721 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3722 break;
3723 }
3724
3725 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3726 }
3727
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3728 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3729 {
3730 (void) u32Id;
3731 BBU_STATE *bbu_state;
3732
3733 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3734 || (eDecType == E_VPU_EX_DECODER_VP8)
3735 #if SUPPORT_G2VP9
3736 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3737 #endif
3738 )
3739 {
3740 // MVD should not call this function.
3741 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3742 return;
3743 }
3744
3745 switch (eDecType)
3746 {
3747 case E_VPU_EX_DECODER_EVD:
3748 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3749 break;
3750 case E_VPU_EX_DECODER_HVD:
3751 case E_VPU_EX_DECODER_RVD:
3752 case E_VPU_EX_DECODER_MVC:
3753 default:
3754 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3755 break;
3756 }
3757
3758 if (bbu_state[u32BBUId].u32Used == 0)
3759 {
3760 bbu_state[u32BBUId].u8RegSetting = 0;
3761 }
3762
3763 return;
3764 }
3765
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3766 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3767 {
3768 MS_U32 i, max_bbu_cnt;
3769 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3770
3771 if(pTaskInfo == NULL)
3772 return retBBUId;
3773
3774 BBU_STATE *bbu_state;
3775 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3776 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3777
3778 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3779
3780 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3781
3782 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3783 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3784 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3785
3786 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3787 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3788
3789 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3790 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3791 */
3792 #if 1
3793 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3794 {
3795 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3796 if (bTSP)
3797 {
3798 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3799 {
3800 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3801 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3802 slq_state[u8TaskId].bTSP = TRUE;
3803 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3804 return u8TaskId;
3805 }
3806 }
3807 else
3808 {
3809 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3810 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3811 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3812 {
3813 if (slq_state[i].u32Used != 0)
3814 {
3815 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3816 {
3817 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3818 }
3819 }
3820 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3821 {
3822 avaliable_bbu_idx = i; // recored the first empty bbu
3823 }
3824 }
3825
3826 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3827
3828 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3829 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3830 slq_state[shared_bbu_idx].bTSP = FALSE;
3831 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3832 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3833 return shared_bbu_idx;
3834 }
3835 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3836 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3837 slq_state[u8TaskId].bTSP = FALSE;
3838 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3839
3840 if (bShareBBU == FALSE)
3841 {
3842 slq_state[u8TaskId].bTSP = TRUE;
3843 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3844 }
3845 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3846 return u8TaskId;
3847 }
3848 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3849 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3850 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3851 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3852
3853 if (bShareBBU == FALSE)
3854 {
3855 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3856 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3857 }
3858 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3859 return avaliable_bbu_idx;
3860 }
3861 else {
3862 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3863 }
3864 }
3865 }
3866 #if SUPPORT_G2VP9
3867 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3868 {
3869 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3870 // Don't care the return value, G2_VP9 will not use it.
3871 return 0;
3872 }
3873 #endif
3874 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3875 {
3876 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3877 // Don't care the return value, VP8 will not use it.
3878 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3879 return u8Offset;
3880 //return 0;
3881 }
3882 else
3883 {
3884 switch (pTaskInfo->eDecType)
3885 {
3886 case E_VPU_EX_DECODER_EVD:
3887 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3888 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3889 break;
3890 case E_VPU_EX_DECODER_HVD:
3891 case E_VPU_EX_DECODER_RVD:
3892 case E_VPU_EX_DECODER_MVC:
3893 default:
3894 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3895 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3896 break;
3897 }
3898
3899 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3900 if (bTSP)
3901 {
3902 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3903 {
3904 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3905 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3906 bbu_state[u8TaskId].bTSP = TRUE;
3907 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3908 slq_state[u8TaskId].bTSP = TRUE;
3909 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3910 return u8TaskId;
3911 }
3912 }
3913 else
3914 {
3915 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3916 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3917 for (i = 0; i < max_bbu_cnt; i++)
3918 {
3919 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3920 {
3921 if (bbu_state[i].bTSP == FALSE)
3922 {
3923 shared_bbu_idx = i;
3924 }
3925 }
3926 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3927 {
3928 avaliable_bbu_idx = i;
3929 }
3930 }
3931
3932 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3933
3934 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3935 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3936 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3937 return shared_bbu_idx;
3938 }
3939 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3940 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3941
3942 if (bShareBBU == FALSE)
3943 {
3944 bbu_state[u8TaskId].bTSP = TRUE;
3945 VPRINTF("[NDec] occupy one BBU_ID \n");
3946 }
3947 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3948 return u8TaskId;
3949 }
3950 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3951 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3952
3953 if (bShareBBU == FALSE)
3954 {
3955 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3956 VPRINTF("[NDec] occupy one BBU_ID \n");
3957 }
3958 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3959 return avaliable_bbu_idx;
3960 }
3961 else {
3962 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3963 }
3964 }
3965 }
3966 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3967 MS_U32 j;
3968 MS_BOOL Got = FALSE;
3969 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3970 {
3971 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3972 {
3973 if(slq_state[i].u32Used != 0)
3974 {
3975 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3976 {
3977 retBBUId = i;
3978 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3979 slq_state[retBBUId].bTSP = bTSP;
3980 slq_state[retBBUId].bUsedbyMVD = TRUE;
3981 return retBBUId;
3982 }
3983 }
3984 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3985 {
3986 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3987 {
3988 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3989 {
3990 Got = TRUE;
3991 retBBUId = i;
3992 }
3993 }
3994
3995 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3996 {
3997 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3998 {
3999 Got = TRUE;
4000 retBBUId = i;
4001 }
4002 }
4003
4004 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
4005 retBBUId = i;
4006 }
4007 }
4008 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4009 {
4010 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4011 slq_state[retBBUId].bTSP = bTSP;
4012 slq_state[retBBUId].bUsedbyMVD = TRUE;
4013 }
4014 }
4015 #if SUPPORT_G2VP9
4016 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4017 {
4018 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4019 // Don't care the return value, G2_VP9 will not use it.
4020 return 0;
4021 }
4022 #endif
4023 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4024 {
4025 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4026 // Don't care the return value, VP8 will not use it.
4027 return 0;
4028 }
4029 else // HVD/EVD case
4030 {
4031 switch (pTaskInfo->eDecType)
4032 {
4033 case E_VPU_EX_DECODER_EVD:
4034 case E_VPU_EX_DECODER_G2VP9:
4035 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4036 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4037 break;
4038 case E_VPU_EX_DECODER_HVD:
4039 case E_VPU_EX_DECODER_RVD:
4040 case E_VPU_EX_DECODER_MVC:
4041 default:
4042 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4043 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4044 break;
4045 }
4046
4047 for (i = 0; i < max_bbu_cnt; i++)
4048 {
4049 if(bbu_state[i].u32Used != 0)
4050 {
4051 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
4052 {
4053 retBBUId = i;
4054 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4055 bbu_state[retBBUId].bTSP = bTSP;
4056 return retBBUId;
4057 }
4058 }
4059 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
4060 {
4061 if(i < MAX_MVD_SLQ_COUNT)
4062 {
4063 if(!bTSP) //HVD/EVD first MM case
4064 {
4065 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
4066 {
4067 retBBUId = i;
4068 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4069 bbu_state[retBBUId].bTSP = bTSP;
4070 return retBBUId;
4071 }
4072
4073 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
4074 retBBUId = i;
4075 }
4076 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
4077 {
4078 retBBUId = i;
4079 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4080 bbu_state[retBBUId].bTSP = bTSP;
4081 slq_state[retBBUId].bUsedbyMVD = FALSE;
4082 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4083 slq_state[retBBUId].bTSP = bTSP;
4084 return retBBUId;
4085 }
4086 }
4087 }
4088 }
4089 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
4090 {
4091 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
4092 bbu_state[retBBUId].bTSP = bTSP;
4093 if(bTSP)
4094 {
4095 slq_state[retBBUId].bUsedbyMVD = FALSE;
4096 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
4097 slq_state[retBBUId].bTSP = bTSP;
4098 }
4099 }
4100 }
4101 #endif
4102 return retBBUId;
4103 }
4104
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)4105 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
4106 {
4107 MS_U32 max_bbu_cnt;
4108 BBU_STATE *bbu_state;
4109 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
4110
4111 if(pTaskInfo == NULL)
4112 return FALSE;
4113 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4114 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4115
4116 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4117 /* MS_U32 i;
4118 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4119 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4120
4121 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4122 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
4123
4124 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4125 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
4126 */
4127 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4128 {
4129 // TO DO
4130 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4131 {
4132 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4133 slq_state[u32BBUId].bTSP = FALSE;
4134 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4135 return TRUE;
4136 }
4137 }
4138 #if SUPPORT_G2VP9
4139 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4140 {
4141 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4142 return TRUE;
4143 }
4144 #endif
4145 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4146 {
4147 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4148 return TRUE;
4149 }
4150 else
4151 {
4152 switch (pTaskInfo->eDecType)
4153 {
4154 case E_VPU_EX_DECODER_EVD:
4155 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4156 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4157 break;
4158 case E_VPU_EX_DECODER_HVD:
4159 case E_VPU_EX_DECODER_RVD:
4160 case E_VPU_EX_DECODER_MVC:
4161 default:
4162 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4163 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4164 break;
4165 }
4166
4167 if (u32BBUId < max_bbu_cnt)
4168 {
4169 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4170 bbu_state[u32BBUId].bTSP = FALSE;
4171
4172 if (bTSP)
4173 {
4174 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4175 slq_state[u32BBUId].bTSP = FALSE;
4176 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4177 }
4178
4179 #if 1
4180 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4181 #else
4182 if (bbu_state[u32BBUId].u32Used == 0)
4183 {
4184 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4185 }
4186 #endif
4187
4188 return TRUE;
4189 }
4190 }
4191 return FALSE;
4192 }
4193
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4194 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4195 {
4196 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4197
4198 if (CHECK_NULL_PTR(pstVBBU))
4199 return 0;
4200 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4201 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4202 MS_U32 u32Vacancy = 0;
4203
4204 if (u32WrPtr == u32RdPtr)
4205 {
4206 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4207 }
4208 else if (u32WrPtr > u32RdPtr)
4209 {
4210 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4211 }
4212 else
4213 {
4214 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4215 }
4216
4217 return u32Vacancy;
4218 }
4219
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4220 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4221 {
4222 return MAX_VDEC_VBBU_ENTRY_COUNT;
4223 }
4224
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4225 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4226 {
4227 return pVPUHalContext->u32FWCodeAddr;
4228 }
4229
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4230 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4231 {
4232 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4233 #if SUPPORT_G2VP9
4234 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4235 #endif
4236
4237 if (CHECK_NULL_PTR(pstVBBU))
4238 return FALSE;
4239 MsOS_ReadMemory();
4240 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4241
4242 if(NULL == stEntry)
4243 {
4244 return 0;
4245 }
4246
4247 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4248 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4249 {
4250 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4251 }
4252 else
4253 {
4254 #if SUPPORT_G2VP9
4255 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4256 {
4257 if (stEntry->u32Offset == 0)
4258 return 0;
4259 else
4260 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4261 }
4262 else
4263 #endif
4264 {
4265 return stEntry->u32Offset;
4266 }
4267 }
4268 }
4269
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4270 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4271 {
4272 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4273 VDEC_VBBU_Entry *stEntry;
4274 #if SUPPORT_G2VP9
4275 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4276 #endif
4277
4278 MsOS_ReadMemory();
4279 if (CHECK_NULL_PTR(pstVBBU))
4280 return 0;
4281 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4282
4283 if (u32WrPtr == 0)
4284 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4285 else
4286 u32WrPtr--;
4287
4288 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4289
4290 if(NULL == stEntry)
4291 {
4292 return 0;
4293 }
4294
4295 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4296 #if SUPPORT_G2VP9
4297 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4298 {
4299 if (stEntry->u32Offset == 0)
4300 return 0;
4301 else
4302 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4303 }
4304 else
4305 #endif
4306 {
4307 return stEntry->u32Offset + stEntry->u32Length;
4308 }
4309 }
4310
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4311 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4312 {
4313 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4314 #if SUPPORT_G2VP9
4315 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4316 #endif
4317
4318 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4319 return FALSE;
4320 MsOS_ReadMemory();
4321 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4322 MS_U32 u32NewWrPtr;
4323
4324 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4325 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4326 {
4327 u32NewWrPtr = 0;
4328 }
4329
4330 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4331
4332 stEntry->u32Offset = stVpuPkt->u32Offset;
4333
4334 #if SUPPORT_G2VP9
4335 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4336 {
4337 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4338 }
4339 #endif
4340
4341 stEntry->u32Length = stVpuPkt->u32Length;
4342 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4343 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4344 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4345
4346 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4347
4348 pstVBBU->u32WrPtr = u32NewWrPtr;
4349
4350 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4351
4352 MsOS_FlushMemory();
4353
4354 return TRUE;
4355 }
4356
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4357 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4358 {
4359 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4360
4361 if (CHECK_NULL_PTR(pstVBBU))
4362 return FALSE;
4363 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4364 }
4365
4366 ///-----------------------------------------------------------------------------
4367 /// specify the command send to Mail box or DRAM
4368 /// @return TRUE or FALSE
4369 /// - TRUE, Mail box
4370 /// - FALSE, Dram
4371 /// @param u32Cmd \b IN: Command is going to be sned
4372 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4373 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4374 {
4375 MS_BOOL bResult = TRUE;
4376
4377 switch (u32Cmd)
4378 {
4379 // *********** Runtime action Command
4380 /* case E_HVD_CMD_RELEASE_DISPQ:
4381 case E_HVD_CMD_UPDATE_DISPQ:
4382 case E_HVD_CMD_FLUSH_DEC_Q:
4383 case E_HVD_CMD_FLUSH:
4384 case E_HVD_CMD_PLAY:
4385 case E_HVD_CMD_PAUSE:
4386 case E_HVD_CMD_STOP:
4387 case E_HVD_CMD_STEP_DECODE:
4388 case E_HVD_CMD_SKIP_DEC:
4389 case E_HVD_CMD_DISP_I_DIRECT:*/
4390 // *********** Dual-Stream Create Task Command
4391 case E_DUAL_CMD_TASK0_HVD_BBU:
4392 case E_DUAL_CMD_TASK0_HVD_TSP:
4393 case E_DUAL_CMD_TASK0_MVD_SLQ:
4394 case E_DUAL_CMD_TASK0_MVD_TSP:
4395 case E_DUAL_CMD_TASK1_HVD_BBU:
4396 case E_DUAL_CMD_TASK1_HVD_TSP:
4397 case E_DUAL_CMD_MODE:
4398 #ifndef _WIN32
4399 case E_DUAL_CMD_TASK1_MVD_SLQ:
4400 case E_DUAL_CMD_TASK1_MVD_TSP:
4401 #endif
4402 case E_DUAL_CMD_DEL_TASK:
4403 case E_DUAL_CMD_SINGLE_TASK:
4404 case E_DUAL_VERSION:
4405 case E_DUAL_R2_CMD_EXIT:
4406 case E_DUAL_CMD_STC_MODE:
4407 #ifdef VDEC3
4408 case E_DUAL_R2_CMD_FBADDR:
4409 case E_DUAL_R2_CMD_FBSIZE:
4410 // *********** N-Streams
4411 case E_NST_CMD_TASK_HVD_TSP:
4412 case E_NST_CMD_TASK_HVD_BBU:
4413 case E_NST_CMD_TASK_MVD_TSP:
4414 case E_NST_CMD_TASK_MVD_SLQ:
4415 case E_NST_CMD_DEL_TASK:
4416 case E_NST_CMD_COMMON_MASK:
4417 case E_NST_CMD_COMMON_CMD1:
4418 #endif
4419 case E_DUAL_CMD_COMMON:
4420 {
4421 bResult = TRUE;
4422 }
4423 break;
4424 default:
4425 {
4426 bResult = FALSE;
4427 }
4428 break;
4429 }
4430
4431 return bResult;
4432 }
4433
4434 ///-----------------------------------------------------------------------------
4435 /// specify the command send to Mail box or DRAM
4436 /// @return TRUE or FALSE
4437 /// - TRUE, Mail box
4438 /// - FALSE, Dram
4439 /// @param u32Cmd \b IN: Command is going to be sned
4440 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4441 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4442 {
4443 MS_BOOL bResult = TRUE;
4444
4445 switch (u32Cmd)
4446 {
4447 // *********** Runtime action Command
4448 case E_HVD_CMD_RELEASE_DISPQ:
4449 case E_HVD_CMD_UPDATE_DISPQ:
4450 case E_HVD_CMD_FLUSH_DEC_Q:
4451 case E_HVD_CMD_PAUSE:
4452 case E_HVD_CMD_FLUSH:
4453 case E_HVD_CMD_PLAY:
4454 case E_HVD_CMD_STOP:
4455 case E_HVD_CMD_SKIP_DEC:
4456 case E_HVD_CMD_DISP_I_DIRECT:
4457 case E_HVD_CMD_STEP_DECODE:
4458 case E_HVD_CMD_INC_DISPQ_NUM:
4459 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4460 {
4461 bResult = TRUE;
4462 }
4463 break;
4464 default:
4465 {
4466 bResult = FALSE;
4467 }
4468 break;
4469 }
4470
4471 return bResult;
4472 }
4473
4474 ///-----------------------------------------------------------------------------
4475 /// Send message to HVD stream command queue
4476 /// @return TRUE or FALSE
4477 /// - TRUE, Success
4478 /// - FALSE, Failed
4479 /// @param u32DramAddr \b IN: address to be writen
4480 /// @param u32Msg \b IN: data to be writen
4481 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4482 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4483 {
4484 MS_BOOL bResult = TRUE;
4485
4486 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4487
4488 WRITE_LONG(u32DramAddr,u32Msg);
4489
4490 return bResult;
4491 }
4492
4493 ///-----------------------------------------------------------------------------
4494 /// Read task share memory to specify that task command queue is empty or not
4495 /// @return TRUE or FALSE
4496 /// - TRUE, Empty
4497 /// - FALSE, Non empty
4498 /// @param u32Id \b IN: Task information
4499 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4500 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4501 {
4502 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4503 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4504 if (!cmd_q)
4505 {
4506 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4507 return FALSE;
4508 }
4509
4510 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4511 }
4512
4513 ///-----------------------------------------------------------------------------
4514 /// Read task share memory to specify that task command queue is full or not
4515 /// @return TRUE or FALSE
4516 /// - TRUE, Full
4517 /// - FALSE, Non full
4518 /// @param u32Id \b IN: Task information
4519 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4520 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4521 {
4522 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4523 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4524 if (!cmd_q)
4525 {
4526 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4527 return TRUE;
4528 }
4529 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4530
4531 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4532 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4533
4534 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4535 }
4536
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4537 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4538 {
4539 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4540 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4541 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4542
4543 #if HVD_ENABLE_MVC
4544 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4545 {
4546 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4547 }
4548 #endif
4549
4550 if (CHECK_NULL_PTR(cmd_q))
4551 {
4552 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4553 return bResult;
4554 }
4555 MS_VIRT u32CmdQWdPtr;
4556
4557 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4558 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4559
4560 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4561 return E_HVD_COMMAND_QUEUE_FULL;
4562 else
4563 {
4564 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4565 }
4566
4567 switch (u8CmdType)
4568 {
4569 case E_HVD_CMDQ_CMD:
4570 {
4571 u32Msg |= (u8TaskID << 24);
4572 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4573
4574 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4575
4576 if (bResult)
4577 {
4578 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4579
4580 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4581 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4582
4583 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4584 }
4585 break;
4586 }
4587 case E_HVD_CMDQ_ARG:
4588 {
4589 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4590 if (bResult)
4591 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4592 break;
4593 }
4594 default:
4595 {
4596 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4597 break;
4598 }
4599 }
4600
4601 MsOS_FlushMemory();
4602
4603 return bResult;
4604 }
4605
4606 ///-----------------------------------------------------------------------------
4607 /// Read task share memory to specify that task display command queue is empty or not
4608 /// @return TRUE or FALSE
4609 /// - TRUE, Empty
4610 /// - FALSE, Non empty
4611 /// @param u32Id \b IN: Task information
4612 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4613 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4614 {
4615 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4616 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4617 if (!cmd_q)
4618 {
4619 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4620 return FALSE;
4621 }
4622
4623 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4624 }
4625
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4626 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4627 {
4628 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4629 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4630 if (!cmd_q)
4631 {
4632 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4633 return TRUE;
4634 }
4635
4636 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4637
4638 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4639 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4640
4641 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4642 }
4643
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4644 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4645 {
4646 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4647 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4648 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4649
4650 #if HVD_ENABLE_MVC
4651 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4652 {
4653 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4654 }
4655 #endif
4656
4657 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4658 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4659
4660 if (CHECK_NULL_PTR(cmd_q))
4661 {
4662 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4663 return bResult;
4664 }
4665
4666 MS_VIRT u32DISPCMDQWdPtr;
4667
4668 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4669 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4670
4671 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4672 return E_HVD_COMMAND_QUEUE_FULL;
4673 else
4674 {
4675 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4676 }
4677
4678 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4679
4680 switch (u8CmdType)
4681 {
4682 case E_HVD_CMDQ_CMD:
4683 {
4684 u32Msg |= (u8TaskID << 24);
4685 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4686
4687 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4688
4689 if (bResult)
4690 {
4691 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4692
4693 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4694 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4695
4696 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4697 }
4698 break;
4699 }
4700 case E_HVD_CMDQ_ARG:
4701 {
4702 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4703 if (bResult)
4704 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4705 break;
4706 }
4707 default:
4708 {
4709 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4710 break;
4711 }
4712 }
4713
4714 MsOS_FlushMemory();
4715
4716 return bResult;
4717 }
4718
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4719 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4720 {
4721 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4722 MS_U32 u32StAddr;
4723 MS_U8 u8TmpMiuSel;
4724
4725 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4726
4727 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4728
4729 return TRUE;
4730 }
4731 #endif
4732
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4733 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4734 {
4735 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4736
4737 if(u32address >= HAL_MIU1_BASE)
4738 {
4739 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4740 }
4741 else
4742 {
4743 pVPUHalContext->u32DynamicFBAddress = u32address;
4744 }
4745
4746 pVPUHalContext->u32DynamicFBSize = u32Size;
4747 }
4748 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4749 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4750 {
4751 MS_S32 handle;
4752 switch(eClkPortType)
4753 {
4754 case E_VPU_EX_CLKPORT_MVD:
4755 {
4756 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4757 if(bEnable)
4758 {
4759 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4760 }
4761 else
4762 {
4763 Drv_Clkm_Clk_Gate_Disable(handle);
4764 }
4765 break;
4766 }
4767 case E_VPU_EX_CLKPORT_MVD_CORE:
4768 {
4769 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4770 if(bEnable)
4771 {
4772 Drv_Clkm_Set_Clk_Source(handle, "");
4773 }
4774 else
4775 {
4776 Drv_Clkm_Clk_Gate_Disable(handle);
4777 }
4778 break;
4779 }
4780 case E_VPU_EX_CLKPORT_MVD_PAS:
4781 {
4782 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4783 if(bEnable)
4784 {
4785 Drv_Clkm_Set_Clk_Source(handle, "");
4786 }
4787 else
4788 {
4789 Drv_Clkm_Clk_Gate_Disable(handle);
4790 }
4791 break;
4792 }
4793 case E_VPU_EX_CLKPORT_HVD:
4794 {
4795 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4796 if(bEnable)
4797 {
4798 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4799 }
4800 else
4801 {
4802 Drv_Clkm_Clk_Gate_Disable(handle);
4803 }
4804 break;
4805 }
4806 case E_VPU_EX_CLKPORT_HVD_IDB:
4807 {
4808 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4809 if(bEnable)
4810 {
4811 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4812 }
4813 else
4814 {
4815 Drv_Clkm_Clk_Gate_Disable(handle);
4816 }
4817 break;
4818 }
4819 case E_VPU_EX_CLKPORT_HVD_AEC:
4820 {
4821 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4822 if(bEnable)
4823 {
4824 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4825 }
4826 else
4827 {
4828 Drv_Clkm_Clk_Gate_Disable(handle);
4829 }
4830 break;
4831 }
4832 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4833 {
4834 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4835 if(bEnable)
4836 {
4837 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4838 }
4839 else
4840 {
4841 Drv_Clkm_Clk_Gate_Disable(handle);
4842 }
4843 break;
4844 }
4845 case E_VPU_EX_CLKPORT_VP8:
4846 {
4847 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4848 if(bEnable)
4849 {
4850 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4851 }
4852 else
4853 {
4854 Drv_Clkm_Clk_Gate_Disable(handle);
4855 }
4856 break;
4857 }
4858 case E_VPU_EX_CLKPORT_EVD:
4859 {
4860 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4861 if(bEnable)
4862 {
4863 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4864 }
4865 else
4866 {
4867 Drv_Clkm_Clk_Gate_Disable(handle);
4868 }
4869 break;
4870 }
4871 case E_VPU_EX_CLKPORT_EVD_PPU:
4872 {
4873 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4874 if(bEnable)
4875 {
4876 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4877 }
4878 else
4879 {
4880 Drv_Clkm_Clk_Gate_Disable(handle);
4881 }
4882 break;
4883 }
4884 case E_VPU_EX_CLKPORT_EVD_LITE:
4885 {
4886 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4887 if(bEnable)
4888 {
4889 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4890 }
4891 else
4892 {
4893 Drv_Clkm_Clk_Gate_Disable(handle);
4894 }
4895 break;
4896 }
4897 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4898 {
4899 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4900 if(bEnable)
4901 {
4902 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4903 }
4904 else
4905 {
4906 Drv_Clkm_Clk_Gate_Disable(handle);
4907 }
4908 break;
4909 }
4910 case E_VPU_EX_CLKPORT_VD_MHEG5:
4911 {
4912 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4913 if(bEnable)
4914 {
4915 Drv_Clkm_Set_Clk_Source(handle, "");
4916 }
4917 else
4918 {
4919 Drv_Clkm_Clk_Gate_Disable(handle);
4920 }
4921 break;
4922 }
4923 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4924 {
4925 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4926 if(bEnable)
4927 {
4928 Drv_Clkm_Set_Clk_Source(handle, "");
4929 }
4930 else
4931 {
4932 Drv_Clkm_Clk_Gate_Disable(handle);
4933 }
4934 break;
4935 }
4936 }
4937 }
4938 #endif //#ifdef CONFIG_MSTAR_CLKM
4939
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4940 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4941 {
4942 MS_SIZE FrameBufferSize = 0;
4943
4944 switch(eCodecType)
4945 {
4946 case E_VPU_EX_CODEC_TYPE_MPEG2:
4947 case E_VPU_EX_CODEC_TYPE_H263:
4948 case E_VPU_EX_CODEC_TYPE_MPEG4:
4949 case E_VPU_EX_CODEC_TYPE_DIVX311:
4950 case E_VPU_EX_CODEC_TYPE_DIVX412:
4951 case E_VPU_EX_CODEC_TYPE_FLV:
4952 FrameBufferSize = 0x1E00000;
4953 break;
4954 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4955 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4956 FrameBufferSize = 0x6C00000;
4957 break;
4958 case E_VPU_EX_CODEC_TYPE_RV8:
4959 case E_VPU_EX_CODEC_TYPE_RV9:
4960 FrameBufferSize = 0x1B00000;
4961 break;
4962 case E_VPU_EX_CODEC_TYPE_VP8:
4963 FrameBufferSize = 0x1500000;
4964 break;
4965 case E_VPU_EX_CODEC_TYPE_H264:
4966 FrameBufferSize = 0x8200000;
4967 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4968 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4969 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4970 break;
4971 case E_VPU_EX_CODEC_TYPE_AVS:
4972 FrameBufferSize = 0x1B00000;
4973 break;
4974 case E_VPU_EX_CODEC_TYPE_MJPEG:
4975 FrameBufferSize = 0x2800000;
4976 break;
4977 case E_VPU_EX_CODEC_TYPE_MVC:
4978 FrameBufferSize = 0x4200000;
4979 break;
4980 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4981 FrameBufferSize = 0xB000000;
4982 break;
4983 case E_VPU_EX_CODEC_TYPE_HEVC:
4984 #if SUPPORT_MSVP9
4985 case E_VPU_EX_CODEC_TYPE_VP9:
4986 #endif
4987 FrameBufferSize = 0xA000000;
4988 break;
4989 #if !SUPPORT_MSVP9
4990 case E_VPU_EX_CODEC_TYPE_VP9:
4991 FrameBufferSize = 0x7800000;
4992 break;
4993 #endif
4994 default:
4995 FrameBufferSize = 0;
4996 break;
4997 }
4998
4999 return FrameBufferSize;
5000 }
5001
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)5002 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
5003 {
5004 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5005 }
5006
5007 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)5008 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
5009 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
5010 {
5011 MS_SIZE FrameBufferSize = 0;
5012
5013 if (!offset || !length)
5014 return FALSE;
5015
5016 total_length -= unUseSize;
5017 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
5018 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
5019
5020 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
5021
5022 if(FrameBufferSize == 0)
5023 {
5024 return FALSE;
5025 }
5026 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
5027 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
5028 if (total_length < FrameBufferSize)
5029 {
5030 *offset = unUseSize;
5031 *length = total_length;
5032 }
5033 else // todo, dual decode case
5034 {
5035 *offset = unUseSize;
5036 *length = FrameBufferSize;
5037 }
5038 return TRUE;
5039 }
5040
HAL_VPU_EX_strcmp(const char * string1,const char * string2)5041 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
5042 {
5043 int iRet, i;
5044
5045 i = 0;
5046 while(string1[i] || string2[i])
5047 {
5048 iRet = string1[i] - string2[i];
5049 if(iRet)
5050 {
5051 return iRet;
5052 }
5053 i++;
5054 }
5055 return 0;
5056 }
5057
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)5058 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
5059 {
5060 typedef enum
5061 {
5062 E_CAP_NDEC_FB_MIU_SELECT,
5063 E_CAP_NDEC_NSTREAM_FB_SIZE,
5064 E_CAP_NDEC_NSTREAM_BS_SIZE,
5065 E_CAP_NDEC_SUPPORT_SHAREBBU,
5066 E_CAP_SUPPORT_ALLOCATOR,
5067
5068 } VPU_EX_GetCapabilityCmdId;
5069
5070 typedef struct
5071 {
5072 MS_U8 u8CmdId;
5073 MS_U8 u8CmdName[32];
5074
5075 } VPU_EX_GetCapabilityCmd;
5076
5077 static VPU_EX_GetCapabilityCmd stCapCmd[] =
5078 {
5079 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
5080 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
5081 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
5082 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
5083 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
5084 };
5085
5086 MS_U32 bRet = FALSE;
5087 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
5088 MS_U32 u32CmdCnt;
5089
5090 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
5091 {
5092 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
5093 {
5094 bRet = TRUE;
5095 switch(stCapCmd[u32CmdCnt].u8CmdId)
5096 {
5097 case E_CAP_NDEC_FB_MIU_SELECT:
5098 {
5099 VPU_EX_CodecType eCodecType = *((VPU_EX_CodecType *)pParamIn);
5100 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5101 *pSupport = TRUE;
5102 }
5103 break;
5104
5105 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
5106 case E_CAP_NDEC_NSTREAM_FB_SIZE:
5107 {
5108 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5109 *pSize = 0x3500000; // 53M
5110 }
5111 break;
5112
5113 // FIXME: Patch for waiting dynamic bitstream buffer
5114 case E_CAP_NDEC_NSTREAM_BS_SIZE:
5115 {
5116 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
5117 *pSize = 0x400000; // 4M
5118 }
5119 break;
5120
5121 case E_CAP_NDEC_SUPPORT_SHAREBBU:
5122 {
5123 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
5124 *pbSupportShareBBU = TRUE;
5125 }
5126 break;
5127
5128 case E_CAP_SUPPORT_ALLOCATOR:
5129 {
5130 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
5131 *pSupport = TRUE;
5132 }
5133 break;
5134
5135 default:
5136 bRet = FALSE;
5137 break;
5138 }
5139 }
5140 }
5141
5142 return bRet;
5143 }
5144
5145 #else
5146 #include "halVPU_EX.h"
5147 #include "drvMMIO.h"
5148 #include "../hvd_v3/regHVD_EX.h"
5149 #include "halCHIP.h"
5150
5151 #if defined(MSOS_TYPE_NUTTX)
5152 extern int lib_lowprintf(const char *fmt, ...);
5153 #define PRINTF lib_lowprintf
5154 #elif defined(MSOS_TYPE_OPTEE)
5155 #define PRINTF printf
5156 #endif
5157
5158 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5159 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5160
5161 MS_U8 u8FW_Binary[] = {
5162 #include "fwVPU.dat"
5163 };
5164
5165 MS_U32 u32HVDRegOSBase;
5166
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5167 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5168 {
5169 //PRINTF("do load code,u32DestAddr %x\n",addr);
5170 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5171 MAsm_CPU_Sync();
5172 MsOS_FlushMemory();
5173
5174 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5175 {
5176 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5177 return FALSE;
5178 }
5179 return TRUE;
5180 }
5181
HAL_VPU_EX_SetLockDownRegister(void * param)5182 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5183 {
5184 #if 1
5185 MS_PHY u32StAddr_main;
5186 MS_PHY u32StAddr_sub;
5187 MS_U32 u32NonPMBankSize = 0;
5188 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5189
5190 if(param == NULL)
5191 {
5192 return FALSE;
5193 }
5194
5195 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5196
5197 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5198
5199 // ES buffer
5200 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5201 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5202
5203
5204 MS_PHY u32StartOffset;
5205 MS_U8 u8MiuSel;
5206
5207 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5208 u32StAddr_main = u32StartOffset;
5209
5210 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5211 u32StAddr_sub = u32StartOffset;
5212
5213 //Lock down register
5214 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5215 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5216
5217 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
5218 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
5219 //~
5220
5221 // Lock Down
5222 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5223 //~
5224 #endif
5225 return TRUE;
5226 }
5227
5228 #endif
5229