| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | regTSP.h | 738 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 756 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 1703 u32value = _HAL_REG32_R(&_TspCtrl[0].TsRec_Mid_PVR1_WPTR); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 756 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 1755 u32value = _HAL_REG32_R(&_TspCtrl[0].TsRec_Mid_PVR1_WPTR); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 745 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 1733 u32value = _HAL_REG32_R(&_TspCtrl[0].TsRec_Mid_PVR1_WPTR); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 3774 … REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3834 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3879 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS); in HAL_PVR_GetWritePtr()
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| H A D | regTSP.h | 643 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 777 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 1701 u32value = _HAL_REG32_R(&_TspCtrl[0].TsRec_Mid_PVR1_WPTR); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 781 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 781 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 788 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 788 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | regTSP.h | 679 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 4916 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5050 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5131 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS; in HAL_PVR_GetWritePtr()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | regTSP.h | 681 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | regTSP.h | 719 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | regTSP.h | 711 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | regTSP.h | 711 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | regTSP.h | 721 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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| H A D | halTSP.c | 5426 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5561 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5642 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS; in HAL_PVR_GetWritePtr()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 5089 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5203 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5276 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS); in HAL_PVR_GetWritePtr()
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| H A D | regTSP.h | 711 …REG32 TsRec_Mid_PVR1_WPTR; // 0xbf802b48 0x52, PVR1 mid… member
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