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Searched refs:BACKEND_REG_BASE (Results 1 – 25 of 45) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c1285 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBC_Adaptive_TS_CLK()
1288 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1290 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1489 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1507 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1421 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBT_Adaptive_TS_CLK()
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1426 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1655 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c1285 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBC_Adaptive_TS_CLK()
1288 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1290 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1489 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1490 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1494 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1497 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1504 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1507 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1421 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBT_Adaptive_TS_CLK()
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1426 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1654 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1655 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBC.c1174 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBC_Adaptive_TS_CLK()
1177 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1179 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1387 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1388 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1392 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1395 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1402 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1405 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
[all …]
H A DhalDMD_INTERN_DVBT.c1239 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBT_Adaptive_TS_CLK()
1242 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1244 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1458 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c1247 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBT_Adaptive_TS_CLK()
1250 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1252 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBT_Adaptive_TS_CLK()
1459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1464 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1467 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1480 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
H A DhalDMD_INTERN_DVBC.c1178 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x16*2+1), 0x15) ; in INTERN_DVBC_Adaptive_TS_CLK()
1181 MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE + (0x10*2), &TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1183 MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE + (0x10*2), TS_Clock_Temp) ; in INTERN_DVBC_Adaptive_TS_CLK()
1391 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1392 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1396 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1399 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1406 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1409 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBC.c1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBC.c1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBC.c1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBC.c1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBC.c1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1447 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1454 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1463 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1471 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1502 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c1407 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1408 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1415 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1422 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1425 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1428 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1431 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1436 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBC.c1846 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1847 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBC_GetPostViterbiBer()
1851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBC_GetPostViterbiBer()
1854 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBC_GetPostViterbiBer()
1861 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBC_GetPostViterbiBer()
1864 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBC_GetPostViterbiBer()
1867 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBC_GetPostViterbiBer()
1870 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBC_GetPostViterbiBer()
1878 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz); in INTERN_DVBC_GetPostViterbiBer()
1909 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBC_GetPacketErr()
[all …]
H A DhalDMD_INTERN_DVBT.c1793 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1794 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c1796 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1797 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1817 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1828 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c1763 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1764 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1768 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1771 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1778 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1781 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1784 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1787 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1792 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c1790 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, &reg_frz); in INTERN_DVBT_GetPostViterbiBer()
1791 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03); in INTERN_DVBT_GetPostViterbiBer()
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, &reg); in INTERN_DVBT_GetPostViterbiBer()
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, &reg); in INTERN_DVBT_GetPostViterbiBer()
1805 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, &reg); in INTERN_DVBT_GetPostViterbiBer()
1808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, &reg); in INTERN_DVBT_GetPostViterbiBer()
1811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, &reg); in INTERN_DVBT_GetPostViterbiBer()
1814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, &reg); in INTERN_DVBT_GetPostViterbiBer()
1819 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, &reg); in INTERN_DVBT_GetPostViterbiBer()
1822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, &reg); in INTERN_DVBT_GetPostViterbiBer()
[all …]

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