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Searched refs:params (Results 1 – 25 of 45) sorted by relevance

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/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl1_setup.c83 dw_mmc_params_t params; in bl1_platform_setup() local
97 memset(&params, 0, sizeof(dw_mmc_params_t)); in bl1_platform_setup()
98 params.reg_base = DWMMC0_BASE; in bl1_platform_setup()
99 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; in bl1_platform_setup()
100 params.desc_size = 1 << 20; in bl1_platform_setup()
101 params.clk_rate = 24 * 1000 * 1000; in bl1_platform_setup()
102 params.bus_width = MMC_BUS_WIDTH_8; in bl1_platform_setup()
103 params.flags = MMC_FLAG_CMD23; in bl1_platform_setup()
105 dw_mmc_init(&params, &mmc_info); in bl1_platform_setup()
H A Dhikey_bl2_setup.c293 dw_mmc_params_t params; in bl2_platform_setup() local
318 memset(&params, 0, sizeof(dw_mmc_params_t)); in bl2_platform_setup()
319 params.reg_base = DWMMC0_BASE; in bl2_platform_setup()
320 params.desc_base = HIKEY_MMC_DESC_BASE; in bl2_platform_setup()
321 params.desc_size = 1 << 20; in bl2_platform_setup()
322 params.clk_rate = 24 * 1000 * 1000; in bl2_platform_setup()
323 params.bus_width = MMC_BUS_WIDTH_8; in bl2_platform_setup()
324 params.flags = MMC_FLAG_CMD23; in bl2_platform_setup()
326 dw_mmc_init(&params, &mmc_info); in bl2_platform_setup()
/rk3399_ARM-atf/drivers/synopsys/ufs/
H A Ddw_ufs.c16 static int dwufs_phy_init(ufs_params_t *params) in dwufs_phy_init() argument
23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
96 static int dwufs_phy_set_pwr_mode(ufs_params_t *params) in dwufs_phy_set_pwr_mode() argument
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
106 flags = params->flags; in dwufs_phy_set_pwr_mode()
191 int dw_ufs_init(dw_ufs_params_t *params) in dw_ufs_init() argument
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
197 ufs_params.desc_base = params->desc_base; in dw_ufs_init()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dimx8mm_bl2_el3_setup.c43 imx_usdhc_params_t params; in imx8mm_usdhc_setup() local
46 params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE; in imx8mm_usdhc_setup()
58 params.clk_rate = 50000000; in imx8mm_usdhc_setup()
59 params.bus_width = MMC_BUS_WIDTH_1; in imx8mm_usdhc_setup()
60 params.flags = 0; in imx8mm_usdhc_setup()
63 imx_usdhc_init(&params, &info); in imx8mm_usdhc_setup()
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Drpi3_bl2_setup.c39 struct rpi3_sdhost_params params; in rpi3_sdhost_setup() local
41 memset(&params, 0, sizeof(struct rpi3_sdhost_params)); in rpi3_sdhost_setup()
42 params.reg_base = RPI3_SDHOST_BASE; in rpi3_sdhost_setup()
43 params.bus_width = MMC_BUS_WIDTH_1; in rpi3_sdhost_setup()
44 params.clk_rate = 50000000; in rpi3_sdhost_setup()
45 params.clk_rate_initial = (RPI3_SDHOST_MAX_CLOCK / HC_CLOCKDIVISOR_MAXVAL); in rpi3_sdhost_setup()
48 rpi3_sdhost_init(&params, &mmc_info); in rpi3_sdhost_setup()
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/
H A Dplat_bl2_el3_setup.c82 imx_usdhc_params_t params; in init_s32g_usdhc() local
84 zeromem(&params, sizeof(imx_usdhc_params_t)); in init_s32g_usdhc()
86 params.reg_base = S32G_USDHC_BASE; in init_s32g_usdhc()
87 params.clk_rate = 25000000; in init_s32g_usdhc()
88 params.bus_width = MMC_BUS_WIDTH_4; in init_s32g_usdhc()
89 params.flags = MMC_FLAG_SD_CMD6; in init_s32g_usdhc()
91 imx_usdhc_init(&params, &sd_device_info); in init_s32g_usdhc()
/rk3399_ARM-atf/plat/imx/imx7/warp7/
H A Dwarp7_bl2_el3_setup.c103 imx_usdhc_params_t params; in warp7_usdhc_setup() local
105 zeromem(&params, sizeof(imx_usdhc_params_t)); in warp7_usdhc_setup()
106 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; in warp7_usdhc_setup()
107 params.clk_rate = 25000000; in warp7_usdhc_setup()
108 params.bus_width = MMC_BUS_WIDTH_8; in warp7_usdhc_setup()
110 imx_usdhc_init(&params, &mmc_info); in warp7_usdhc_setup()
/rk3399_ARM-atf/plat/imx/imx7/picopi/
H A Dpicopi_bl2_el3_setup.c97 imx_usdhc_params_t params; in picopi_usdhc_setup() local
99 zeromem(&params, sizeof(imx_usdhc_params_t)); in picopi_usdhc_setup()
100 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; in picopi_usdhc_setup()
101 params.clk_rate = 25000000; in picopi_usdhc_setup()
102 params.bus_width = MMC_BUS_WIDTH_8; in picopi_usdhc_setup()
104 imx_usdhc_init(&params, &mmc_info); in picopi_usdhc_setup()
/rk3399_ARM-atf/drivers/synopsys/emmc/
H A Ddw_mmc.c416 void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info) in dw_mmc_init() argument
418 assert((params != 0) && in dw_mmc_init()
419 ((params->reg_base & MMC_BLOCK_MASK) == 0) && in dw_mmc_init()
420 ((params->desc_base & MMC_BLOCK_MASK) == 0) && in dw_mmc_init()
421 ((params->desc_size & MMC_BLOCK_MASK) == 0) && in dw_mmc_init()
422 (params->desc_size > 0) && in dw_mmc_init()
423 (params->clk_rate > 0) && in dw_mmc_init()
424 ((params->bus_width == MMC_BUS_WIDTH_1) || in dw_mmc_init()
425 (params->bus_width == MMC_BUS_WIDTH_4) || in dw_mmc_init()
426 (params->bus_width == MMC_BUS_WIDTH_8))); in dw_mmc_init()
[all …]
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c436 void imx_usdhc_init(imx_usdhc_params_t *params, in imx_usdhc_init() argument
441 assert((params != 0) && in imx_usdhc_init()
442 ((params->reg_base & MMC_BLOCK_MASK) == 0) && in imx_usdhc_init()
443 ((params->bus_width == MMC_BUS_WIDTH_1) || in imx_usdhc_init()
444 (params->bus_width == MMC_BUS_WIDTH_4) || in imx_usdhc_init()
445 (params->bus_width == MMC_BUS_WIDTH_8))); in imx_usdhc_init()
448 ret = mmap_add_dynamic_region(params->reg_base, params->reg_base, in imx_usdhc_init()
457 memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t)); in imx_usdhc_init()
458 mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width, in imx_usdhc_init()
459 params->flags, mmc_dev_info); in imx_usdhc_init()
/rk3399_ARM-atf/plat/brcm/board/common/
H A Dbcm_elog_ddr.c115 setup.params[0] = TMP_ELOG_METADATA_BASE; in elog_init_ddr_log()
116 setup.params[1] = (sizeof(global) + global.rec_count * sizeof(rec)); in elog_init_ddr_log()
120 flush_dcache_range((uintptr_t)setup.params[0], setup.params[1]); in elog_init_ddr_log()
/rk3399_ARM-atf/lib/xlat_tables_v2/aarch32/
H A Dxlat_tables_arch.c171 void setup_mmu_cfg(uint64_t *params, unsigned int flags, in setup_mmu_cfg() argument
257 params[MMU_CFG_MAIR] = mair; in setup_mmu_cfg()
258 params[MMU_CFG_TCR] = (uint64_t) ttbcr; in setup_mmu_cfg()
259 params[MMU_CFG_TTBR0] = ttbr0; in setup_mmu_cfg()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/
H A Dnvg.c212 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_enable_strict_checking_mode() local
215 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params); in nvg_enable_strict_checking_mode()
220 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_verify_strict_checking_mode() local
224 assert(params == (uint64_t)nvg_get_result()); in nvg_verify_strict_checking_mode()
/rk3399_ARM-atf/drivers/st/usb_dwc3/
H A Dusb_dwc3.c668 dwc3_epcmd_t cmd, dwc3_epcmd_params_t *params) in dwc3_execute_dep_cmd() argument
674 dwc3_get_ep_cmd_str(cmd), (uint32_t)cmd, (uint32_t)params->param0, in dwc3_execute_dep_cmd()
675 (uint32_t)params->param1, (uint32_t)params->param2); in dwc3_execute_dep_cmd()
677 DWC3_regwrite(dwc3_handle->usb_device, DWC3_DEPCMDPAR0(phy_epnum), params->param0); in dwc3_execute_dep_cmd()
678 DWC3_regwrite(dwc3_handle->usb_device, DWC3_DEPCMDPAR1(phy_epnum), params->param1); in dwc3_execute_dep_cmd()
679 DWC3_regwrite(dwc3_handle->usb_device, DWC3_DEPCMDPAR2(phy_epnum), params->param2); in dwc3_execute_dep_cmd()
722 dwc3_epcmd_params_t params; in dwc3_ep_start_xfer() local
765 (void)memset(&params, 0x00, sizeof(params)); in dwc3_ep_start_xfer()
768 params.param0 = upper_32_bits(dwc3_ep->trb_dma_addr); in dwc3_ep_start_xfer()
769 params.param1 = lower_32_bits(dwc3_ep->trb_dma_addr); in dwc3_ep_start_xfer()
[all …]
/rk3399_ARM-atf/drivers/cadence/emmc/
H A Dcdns_sdmmc.c718 int cdns_mmc_init(struct cdns_sdmmc_params *params, in cdns_mmc_init() argument
724 assert((params != NULL) && in cdns_mmc_init()
725 ((params->reg_base & MMC_BLOCK_MASK) == 0) && in cdns_mmc_init()
726 ((params->desc_size & MMC_BLOCK_MASK) == 0) && in cdns_mmc_init()
727 ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) && in cdns_mmc_init()
728 ((params->reg_phy & MMC_BLOCK_MASK) == 0) && in cdns_mmc_init()
729 (params->desc_size > 0) && in cdns_mmc_init()
730 (params->clk_rate > 0) && in cdns_mmc_init()
731 (params->sdmclk > 0) && in cdns_mmc_init()
732 ((params->bus_width == MMC_BUS_WIDTH_1) || in cdns_mmc_init()
[all …]
/rk3399_ARM-atf/lib/xlat_tables_v2/aarch64/
H A Dxlat_tables_arch.c241 void setup_mmu_cfg(uint64_t *params, unsigned int flags, in setup_mmu_cfg() argument
315 params[MMU_CFG_MAIR] = mair; in setup_mmu_cfg()
316 params[MMU_CFG_TCR] = tcr; in setup_mmu_cfg()
317 params[MMU_CFG_TTBR0] = ttbr0; in setup_mmu_cfg()
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl1_plat_setup.c97 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); in bl1_platform_setup() local
110 dw_mmc_init(&params, &mmc_info); in bl1_platform_setup()
H A Dbl2_plat_setup.c177 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); in bl2_early_platform_setup2() local
192 dw_mmc_init(&params, &mmc_info); in bl2_early_platform_setup2()
/rk3399_ARM-atf/plat/st/common/
H A Dbl2_io_storage.c226 struct stm32_sdmmc2_params params; in boot_mmc() local
228 zeromem(&params, sizeof(struct stm32_sdmmc2_params)); in boot_mmc()
234 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
237 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
240 params.reg_base = STM32MP_SDMMC3_BASE; in boot_mmc()
245 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
247 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
253 params.flags = MMC_FLAG_SD_CMD6; in boot_mmc()
256 params.device_info = &mmc_info; in boot_mmc()
257 if (stm32_sdmmc2_mmc_init(&params) != 0) { in boot_mmc()
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c174 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, in bl2_el3_plat_arch_setup() local
177 params.sdmclk = clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID); in bl2_el3_plat_arch_setup()
189 cdns_mmc_init(&params, &mmc_info); in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/include/drivers/synopsys/
H A Ddw_mmc.h22 void dw_mmc_init(dw_mmc_params_t *params, struct mmc_device_info *info);
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32_sdmmc2.h32 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params);
/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c588 void rpi3_sdhost_init(struct rpi3_sdhost_params *params, in rpi3_sdhost_init() argument
591 assert((params != 0) && in rpi3_sdhost_init()
592 ((params->reg_base & MMC_BLOCK_MASK) == 0)); in rpi3_sdhost_init()
594 memcpy(&rpi3_sdhost_params, params, sizeof(struct rpi3_sdhost_params)); in rpi3_sdhost_init()
625 mmc_init(&rpi3_sdhost_ops, params->clk_rate, params->bus_width, in rpi3_sdhost_init()
626 params->flags, mmc_dev_info); in rpi3_sdhost_init()
/rk3399_ARM-atf/include/lib/xlat_tables/
H A Dxlat_mmu_helpers.h66 void setup_mmu_cfg(uint64_t *params, unsigned int flags,
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c114 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); in bl2_el3_plat_arch_setup() local
124 dw_mmc_init(&params, &mmc_info); in bl2_el3_plat_arch_setup()

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