| /rk3399_ARM-atf/plat/xilinx/versal/include/ |
| H A D | platform_def.h | 38 # define BL31_BASE U(0xfffe0000) macro
41 # define BL31_BASE U(VERSAL_ATF_MEM_BASE) macro
87 #if (BL31_BASE >= (1ULL << 32U))
106 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
114 #if !IS_TFA_IN_OCM(BL31_BASE)
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| /rk3399_ARM-atf/plat/nxp/common/setup/aarch64/ |
| H A D | ls_bl2_mem_params_desc.c | 32 .ep_info.pc = BL31_BASE,
42 .image_info.image_base = BL31_BASE - CSF_HDR_SZ,
43 .image_info.image_max_size = (BL31_LIMIT - BL31_BASE) +
46 .image_info.image_base = BL31_BASE,
47 .image_info.image_max_size = (BL31_LIMIT - BL31_BASE),
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/include/ |
| H A D | platform_def.h | 43 # define BL31_BASE U(0xfffea000) macro
46 # define BL31_BASE U(0x1000) macro
50 # define BL31_BASE U(ZYNQMP_ATF_MEM_BASE) macro
105 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
113 #if !IS_TFA_IN_OCM(BL31_BASE)
181 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | plat_bl2_image_desc.c | 19 .ep_info.pc = BL31_BASE,
23 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
24 .image_info.image_base = BL31_BASE,
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| /rk3399_ARM-atf/plat/qti/kodiak/sc7280_chrome/inc/ |
| H A D | platform_def.h | 20 #define BL31_BASE 0xC0000000 macro
22 #define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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| /rk3399_ARM-atf/plat/st/stm32mp2/include/ |
| H A D | platform_def.h | 77 #define BL31_BASE 0 macro
79 #define BL31_BASE STM32MP_SYSRAM_BASE macro
82 #define BL31_LIMIT (BL31_BASE + (STM32MP_SYSRAM_SIZE / 2))
84 #define BL31_PROGBITS_LIMIT (BL31_BASE + STM32MP_BL31_SIZE)
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| /rk3399_ARM-atf/plat/qti/kodiak/rb3gen2/inc/ |
| H A D | platform_def.h | 19 #define BL31_BASE 0x1c200000 macro
21 #define BL31_LIMIT (BL31_BASE + BL31_SIZE)
|
| /rk3399_ARM-atf/plat/nxp/common/include/default/ |
| H A D | plat_default_def.h | 82 #ifndef BL31_BASE
84 #define BL31_BASE NXP_SECURE_DRAM_ADDR macro
92 #define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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| /rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/ |
| H A D | marvell_def.h | 160 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
161 #define BL2_LIMIT BL31_BASE
170 #define BL31_BASE (MARVELL_BL_RAM_BASE + \ macro
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| /rk3399_ARM-atf/plat/brcm/board/stingray/include/ |
| H A D | platform_def.h | 145 #define BL31_BASE BRCM_AP_TZC_DRAM1_BASE macro
151 #define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \ macro
160 #define SCP_BL2_BASE BL31_BASE
203 #define SECURE_DDR_BASE_ADDRESS BL31_BASE
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| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_prepare_dtb.c | 31 if (fdt_add_reserved_memory(fdt, "tf-a@40000000", BL31_BASE, in sunxi_prepare_dtb()
32 BL31_LIMIT - BL31_BASE)) { in sunxi_prepare_dtb()
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| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | bl2_plat_mem_params_desc.c | 34 .ep_info.pc = BL31_BASE,
39 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
40 .image_info.image_base = BL31_BASE,
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_bl2_mem_params_desc.c | 46 .ep_info.pc = BL31_BASE,
55 .image_info.image_base = BL31_BASE,
56 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/ |
| H A D | rd1ae_bl2_mem_params_desc.c | 27 .ep_info.pc = BL31_BASE,
36 .image_info.image_base = BL31_BASE,
37 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/ |
| H A D | corstone1000_bl2_mem_params_desc.c | 28 .ep_info.pc = BL31_BASE,
34 .image_info.image_base = BL31_BASE,
35 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/amd/versal2/include/ |
| H A D | platform_def.h | 46 # define BL31_BASE U(0xBBF00000) macro
49 # define BL31_BASE U(MEM_BASE) macro
112 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
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| /rk3399_ARM-atf/include/plat/marvell/armada/a8k/common/ |
| H A D | marvell_def.h | 196 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE)
197 #define BL2_LIMIT BL31_BASE
205 #define BL31_BASE (MARVELL_BL_RAM_BASE + \ macro
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/ |
| H A D | rdaspen_bl2_mem_params_desc.c | 19 .ep_info.pc = BL31_BASE,
28 .image_info.image_base = BL31_BASE,
29 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | bl2_plat_mem_params_desc.c | 67 .ep_info.pc = BL31_BASE,
73 .image_info.image_base = BL31_BASE,
74 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mp/ |
| H A D | imx8mp_bl2_mem_params_desc.c | 18 .ep_info.pc = BL31_BASE,
23 .image_info.image_base = BL31_BASE,
24 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mm/ |
| H A D | imx8mm_bl2_mem_params_desc.c | 18 .ep_info.pc = BL31_BASE,
23 .image_info.image_base = BL31_BASE,
24 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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| /rk3399_ARM-atf/plat/hisilicon/poplar/include/ |
| H A D | poplar_layout.h | 129 #define BL31_BASE (LLOADER_TEXT_BASE + BL31_OFFSET) macro
130 #define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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| /rk3399_ARM-atf/plat/qti/msm8916/include/ |
| H A D | platform_def.h | 20 #define BL31_LIMIT (BL31_BASE + SZ_128K)
21 #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K)
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| /rk3399_ARM-atf/plat/allwinner/common/include/ |
| H A D | platform_def.h | 18 #define BL31_BASE SUNXI_DRAM_BASE macro
28 #define BL31_BASE (SUNXI_SRAM_A2_BASE + \ macro
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| /rk3399_ARM-atf/plat/qti/msm8916/ |
| H A D | msm8916_bl31_setup.c | 41 msm8916_plat_arch_setup(BL31_BASE, BL31_END - BL31_BASE); in bl31_plat_arch_setup()
|