Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto

Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional

show more ...

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapal

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge "fix(xilinx): warn if reserved memory pre-exists in DT" into integration

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and use

fix(xilinx): warn if reserved memory pre-exists in DT

Memory reservation for tf-a does not happen in
runtime if memory reservation node pre-exists in DT.
Presence of reserved area is checked and user is
warned if it pre-exists.

Change-Id: I50e18be942777747e9074bb9d8e0305a29c28178
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

show more ...

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image ch

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image check in prepare_dtb

show more ...

fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the pr

fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the presence of the FDT header and ensure that the FDT is
open. Meanwhile, 'is_fit_image()' will be responsible for detecting
FIT images. When TF-A is built with a DTB address during compilation
and later executed from DDR memory, TF-A will dynamically reserve a
memory location in the DTB during runtime.

This approach is effective when a raw DTB is present at the specified
address location. With this change, the "is_fit_image()" function
has been introduced to verify the existence of the "/configurations"
property within the DTB.

The presence of this property is exclusive to FIT images. In case
the property is found, a warning message is displayed, and memory
space reservation for its address space in DDR is not performed by
TF-A. However, if the property is not present, TF-A continues its
usual procedure of updating the raw DTB.

Additionally, dynamic mapping has been refactored and separated into
distinct functions: "add_mmap_dynamic_region ()" and
"remove_dynamic_mmap()". This separation enhances compatibility
and maintains better code organization.

Change-Id: I9cd3f09863b44483445e58c802dee34d58dfe2e9
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

Merge changes from topic "refactor_prepare_dtb" into integration

* changes:
refactor(zynqmp): use common code for prepare_dtb
refactor(xilinx): remove multiple return paths in prepare_dtb

refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in t

refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in the compound statement that forms the body of the function.
prepare_dtb is refactored to address the same.

Change-Id: I17ca4314202d6ca8d6fb0c4ea2ed9d31a152371b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

Merge changes from topic "xlnx_mmap_dynamic_dtb" into integration

* changes:
fix(xilinx): dcache flush for dtb region
fix(xilinx): dynamic mmap region for dtb

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related ent

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.

Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c

show more ...

Merge "fix(xilinx): don't reserve 1 more byte" into integration

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for u

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.

Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>

show more ...

Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base

Merge changes from topic "xlnx_fix_plat_ocm_base" into integration

* changes:
fix(xilinx): update dtb when dtb address and tf-a ddr flow is used
fix(versal): use correct macro name for ocm base address

show more ...

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will si

fix(xilinx): update dtb when dtb address and tf-a ddr flow is used

Memory reservation in dtb will be done only when TF-A runs from
ddr and dtb load address is provided.
Otherwise prepare_dtb will simply return.
Empty definition of prepare_dtb is removed.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: Ie8a3ec51d60a7389831cfe6a112f722777930623

show more ...

Merge "fix(xilinx): add headers to resolve compile time issue" into integration

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.bel

fix(xilinx): add headers to resolve compile time issue

Add common/debug.h and libfdt.h files to the common file
for XILINX_OF_BOARD_DTB_ADDR configuration.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I577cc018eda34e186e48594a62c54eb55f11bbd3

show more ...

Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...