1dddba19aSStephan Gerhold /* 26b8f9e16SStephan Gerhold * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3dddba19aSStephan Gerhold * 4dddba19aSStephan Gerhold * SPDX-License-Identifier: BSD-3-Clause 5dddba19aSStephan Gerhold */ 6dddba19aSStephan Gerhold #ifndef PLATFORM_DEF_H 7dddba19aSStephan Gerhold #define PLATFORM_DEF_H 8dddba19aSStephan Gerhold 9dddba19aSStephan Gerhold #include <plat/common/common_def.h> 10dddba19aSStephan Gerhold 1145b2bd0aSStephan Gerhold #ifdef __aarch64__ 12dddba19aSStephan Gerhold /* 13dddba19aSStephan Gerhold * There is at least 1 MiB available for BL31. However, at the moment the 14dddba19aSStephan Gerhold * "msm8916_entry_point" variable in the data section is read through the 15dddba19aSStephan Gerhold * 64 KiB region of the "boot remapper" after reset. For simplicity, limit 16dddba19aSStephan Gerhold * the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and 17dddba19aSStephan Gerhold * the overall limit to 128 KiB. This could be increased if needed by placing 18dddba19aSStephan Gerhold * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. 19dddba19aSStephan Gerhold */ 20a27e3f76SStephan Gerhold #define BL31_LIMIT (BL31_BASE + SZ_128K) 21a27e3f76SStephan Gerhold #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) 2245b2bd0aSStephan Gerhold #endif 234181ec8cSStephan Gerhold #define BL32_LIMIT (BL32_BASE + SZ_128K) 24dddba19aSStephan Gerhold 25dddba19aSStephan Gerhold #define CACHE_WRITEBACK_GRANULE U(64) 26a27e3f76SStephan Gerhold #define PLATFORM_STACK_SIZE SZ_4K 27dddba19aSStephan Gerhold 28c28e96cdSStephan Gerhold /* CPU topology: one or two clusters with 4 cores each */ 29c28e96cdSStephan Gerhold #ifdef PLAT_msm8939 30c28e96cdSStephan Gerhold #define PLATFORM_CLUSTER_COUNT U(2) 31c28e96cdSStephan Gerhold #else 32dddba19aSStephan Gerhold #define PLATFORM_CLUSTER_COUNT U(1) 33c28e96cdSStephan Gerhold #endif 34*78aac78aSStephan Gerhold #if defined(PLAT_mdm9607) 35*78aac78aSStephan Gerhold #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(0) /* 1 */ 36*78aac78aSStephan Gerhold #else 371d7ed58fSStephan Gerhold #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) /* 4 */ 38*78aac78aSStephan Gerhold #endif 391d7ed58fSStephan Gerhold #define PLATFORM_CPUS_PER_CLUSTER (1 << PLATFORM_CPU_PER_CLUSTER_SHIFT) 40dddba19aSStephan Gerhold #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 411d7ed58fSStephan Gerhold PLATFORM_CPUS_PER_CLUSTER) 42dddba19aSStephan Gerhold 43dddba19aSStephan Gerhold /* Power management */ 44dddba19aSStephan Gerhold #define PLATFORM_SYSTEM_COUNT U(1) 45dddba19aSStephan Gerhold #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 46dddba19aSStephan Gerhold PLATFORM_CLUSTER_COUNT + \ 47dddba19aSStephan Gerhold PLATFORM_CORE_COUNT) 48dddba19aSStephan Gerhold #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 49dddba19aSStephan Gerhold #define PLAT_MAX_RET_STATE U(2) 50dddba19aSStephan Gerhold #define PLAT_MAX_OFF_STATE U(3) 51dddba19aSStephan Gerhold 52dddba19aSStephan Gerhold /* Translation tables */ 53dddba19aSStephan Gerhold #define MAX_MMAP_REGIONS 8 54dddba19aSStephan Gerhold #define MAX_XLAT_TABLES 4 55dddba19aSStephan Gerhold 56dddba19aSStephan Gerhold #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 57dddba19aSStephan Gerhold #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 58dddba19aSStephan Gerhold 596b8f9e16SStephan Gerhold /* Timer */ 60dddba19aSStephan Gerhold #define PLAT_SYSCNT_FREQ 19200000 616b8f9e16SStephan Gerhold #define IRQ_SEC_PHY_TIMER (16 + 2) /* PPI #2 */ 62dddba19aSStephan Gerhold 63af644731SStephan Gerhold /* 64af644731SStephan Gerhold * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7 65af644731SStephan Gerhold * erroneously swapped for some reason. PIDR2 is actually at 0xFD8. 66af644731SStephan Gerhold * Override the address in <drivers/arm/gicv2.h> to avoid a failing assert(). 67af644731SStephan Gerhold */ 68af644731SStephan Gerhold #define GICD_PIDR2_GICV2 U(0xFD8) 69af644731SStephan Gerhold 706b8f9e16SStephan Gerhold /* TSP */ 716b8f9e16SStephan Gerhold #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER 726b8f9e16SStephan Gerhold #define TSP_SEC_MEM_BASE BL32_BASE 736b8f9e16SStephan Gerhold #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 746b8f9e16SStephan Gerhold 75dddba19aSStephan Gerhold #endif /* PLATFORM_DEF_H */ 76