Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms

Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms
feat(msm8916): add port for MSM8939
feat(msm8916): power on L2 caches for secondary clusters
feat(msm8916): initialize CCI-400 for multiple clusters
refactor(msm8916): handle multiple CPU clusters
feat(msm8916): add port for MSM8909
feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+
style(msm8916): add missing braces to while statements

show more ...

feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p

feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31/BL33 address and UART number

Make the existing MSM8916 platform port usable for MDM9607 as well by
adding some minimal if statements where necessary plus the platform
make files for mdm9607.

Change-Id: I4dd02c8e29af6282d8d828c3027c5e333459ba36
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the e

feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the existing MSM8916 platform port usable for MSM8939 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8939.

Change-Id: I8cda83dc642f62222f984a42eec14de5df4c11e3
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

refactor(msm8916): handle multiple CPU clusters

Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured

refactor(msm8916): handle multiple CPU clusters

Some Qualcomm platforms similar to MSM8916 have multiple CPU clusters.
In this case, some of the hardware blocks are duplicated and must be
configured separately.

Refactor the code to handle additional clusters by introducing loops
and some conditionals.

No functional change for existing single cluster platforms.

Change-Id: I5b4b1ad2a1adde559d5b79b7698afe73733b2e90
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port f

Merge changes from topic "msm8916-spmin" into integration

* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port for AArch32
refactor(msm8916): detect cold boot in plat_get_my_entrypoint
feat(msm8916): add Test Secure Payload (TSP) port
build(msm8916): place bl32 directly after bl31
refactor(msm8916): separate common platform setup code

show more ...

feat(msm8916): add SP_MIN port for AArch32

Use the new shared msm8916 setup code to allow compiling the minimal
AArch32 Secure Payload (SP_MIN) as simple PSCI implementation.

AArch64 is preferred f

feat(msm8916): add SP_MIN port for AArch32

Use the new shared msm8916 setup code to allow compiling the minimal
AArch32 Secure Payload (SP_MIN) as simple PSCI implementation.

AArch64 is preferred for the Cortex-A53 cores in MSM8916 but there are
some similar platforms with AArch32-only Cortex-A7 cores that can
benefit from this in future changes.

The AArch32 assembly implementation for msm8916_helpers.S and
uartdm_console.S is a direct port of the AArch64 implementation.
Only plat_get_my_entrypoint is slightly different because there is no
need to handle the "boot remapper" on cold boot for AArch32.

Change-Id: Idf160e86fb3e685fcedec3e051400e6273997b74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

feat(msm8916): add Test Secure Payload (TSP) port

Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.

Unlike BL31, TSP only calls

feat(msm8916): add Test Secure Payload (TSP) port

Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.

Unlike BL31, TSP only calls msm8916_platform_setup() but not
msm8916_configure() because this is already done in BL31.

Change-Id: I3225ef9e61387d49870e9759ffd5b899a8805961
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

build(msm8916): place bl32 directly after bl31

At the moment there are two entirely separate memory regions for BL31
and BL32. However, since BL31 is very small (<= 128 KiB) there is
actually still

build(msm8916): place bl32 directly after bl31

At the moment there are two entirely separate memory regions for BL31
and BL32. However, since BL31 is very small (<= 128 KiB) there is
actually still plenty of space after BL31.

Drop the extra memory region for BL32 and place it directly after BL31
(i.e. BL31_LIMIT). If needed it is still possible to change it on the
make command line.

While at it, move the definitions to the bottom of the make file so
they come immediately before the related add_define calls.

Change-Id: I5184dcc2d89a92f1384508f973d56fd963e7befb
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm89

Merge changes I5bb43cb0,I6aebe2ca,Ib59df16a,I9d037ab2,I9df5a465, ... into integration

* changes:
fix(msm8916): add timeout for crash console TX flush
style(msm8916): use size macros
feat(msm8916): expose more timer frames
fix(msm8916): drop unneeded initialization of CNTACR
build(msm8916): disable unneeded workarounds
fix(msm8916): flush dcache after writing msm8916_entry_point
fix(msm8916): print \r before \n on UART console

show more ...

style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf136

style(msm8916): use size macros

Use the pre-defined size macros (SZ_*) for more clarity and to avoid
having to add comments to each size represented by hexadecimal numbers.

Change-Id: I6aebe2caf1365279670955b9b507dec7d7b04457
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding G

Merge changes from topic "msm8916" into integration

* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding GICD_PIDR2_GICV2 address
feat(msm8916): initial platform port
docs(msm8916): new port for Qualcomm Snapdragon 410

show more ...

feat(msm8916): setup hardware for non-secure world

Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secu

feat(msm8916): setup hardware for non-secure world

Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:

- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.

- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.

- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.

- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.

Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...

feat(msm8916): initial platform port

Introduce the bare mimimum base of the msm8916 BL31 port. This is
pretty much just a standard platform "skeleton" with CPU/memory
initialization and an UART driv

feat(msm8916): initial platform port

Introduce the bare mimimum base of the msm8916 BL31 port. This is
pretty much just a standard platform "skeleton" with CPU/memory
initialization and an UART driver. This allows booting into
e.g. U-Boot with working UART output.

Note that the plat/qti/msm8916 port is completely separate and does not
make use of anything in plat/qti/common at the moment. The main reason
for that is that plat/qti/common is heavily focused around having a
binary "qtiseclib" component, while the MSM8916 port is fully
open-source (and therefore somewhat limited to publicly documented
functionality).

In the future it might be possible to re-use some of the open-source
parts in plat/qti/common (e.g. spmi_arb.c or pm_ps_hold.c) but it's
not strictly required for the basic functionality supported so far.

Change-Id: I7b4375df0f947b3bd1e55b0b52b21edb6e6d175b
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

show more ...