| /rk3399_ARM-atf/plat/mediatek/drivers/cirq/ |
| H A D | mt_cirq.c | 37 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4), in mt_irq_mask_restore()
39 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8), in mt_irq_mask_restore()
41 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc), in mt_irq_mask_restore()
43 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10), in mt_irq_mask_restore()
45 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14), in mt_irq_mask_restore()
47 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18), in mt_irq_mask_restore()
49 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c), in mt_irq_mask_restore()
51 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20), in mt_irq_mask_restore()
53 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24), in mt_irq_mask_restore()
55 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28), in mt_irq_mask_restore()
[all …]
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| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_def.h | 61 #define DEVICE1_BASE BASE_GICD_BASE
64 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
68 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
147 #define BASE_GICD_BASE UL(0x2f000000) macro
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| /rk3399_ARM-atf/plat/qti/qcs615/inc/ |
| H A D | platform_def.h | 128 #define BASE_GICD_BASE 0x17A00000 macro
134 #define QTI_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/qti/sc7180/inc/ |
| H A D | platform_def.h | 127 #define BASE_GICD_BASE 0x17A00000 macro
133 #define QTI_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/qti/kodiak/inc/ |
| H A D | kodiak_def.h | 128 #define BASE_GICD_BASE 0x17A00000 macro
134 #define QTI_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/include/ |
| H A D | plat_macros.S | 23 mov_imm x16, BASE_GICD_BASE
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| H A D | platform_def.h | 130 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/mediatek/mt8173/ |
| H A D | plat_mt_gic.c | 26 BASE_GICD_BASE, in plat_mt_gic_init()
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| /rk3399_ARM-atf/include/plat/nuvoton/common/ |
| H A D | plat_macros.S | 24 mov_imm x16, BASE_GICD_BASE
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| /rk3399_ARM-atf/include/plat/nuvoton/npcm845x/ |
| H A D | platform_def.h | 141 #define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) macro
147 #define DEVICE1_BASE BASE_GICD_BASE
172 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/mediatek/drivers/gicv3/ |
| H A D | mt_gic_v3.c | 56 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
70 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
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| /rk3399_ARM-atf/plat/nuvoton/common/ |
| H A D | plat_nuvoton_gic.c | 20 .gicd_base = BASE_GICD_BASE,
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| /rk3399_ARM-atf/plat/rockchip/rk3399/ |
| H A D | rk3399_def.h | 29 #define BASE_GICD_BASE (GIC500_BASE) macro
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| /rk3399_ARM-atf/plat/arm/board/fvp/include/ |
| H A D | plat_macros.S | 33 mov_imm x16, BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/rockchip/rk3399/include/ |
| H A D | platform_def.h | 89 #define PLAT_RK_GICD_BASE BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/mediatek/mt8183/include/ |
| H A D | platform_def.h | 116 #define BASE_GICD_BASE MT_GIC_BASE macro
130 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| H A D | plat_macros.S | 35 mov_imm x26, BASE_GICD_BASE
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| /rk3399_ARM-atf/plat/mediatek/mt8173/include/ |
| H A D | plat_macros.S | 35 mov_imm x16, BASE_GICD_BASE
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| H A D | platform_def.h | 118 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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| H A D | mt8173_def.h | 68 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8192/include/ |
| H A D | platform_def.h | 82 #define BASE_GICD_BASE MT_GIC_BASE macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/include/ |
| H A D | platform_def.h | 88 #define BASE_GICD_BASE MT_GIC_BASE macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/gic600/ |
| H A D | mt_gic_v3.c | 226 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
237 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/include/ |
| H A D | platform_def.h | 96 #define BASE_GICD_BASE MT_GIC_BASE macro
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| /rk3399_ARM-atf/plat/mediatek/mt8189/include/ |
| H A D | platform_def.h | 185 #define BASE_GICD_BASE (MT_GIC_BASE) macro
|